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/freebsd/crypto/openssh/openbsd-compat/
H A Dopenssl-compat.c38 * to work with 1.0.0). Going backwards is only allowed within a patch series.
54 if (headerver >= 0x3000000f) { in ssh_compatible_openssl()
55 mask = 0xf000000fL; /* major,status */ in ssh_compatible_openssl()
60 * For versions >= 1.0.0, but <3, major,minor,status must match and in ssh_compatible_openssl()
63 mask = 0xfff0000fL; /* major,minor,status */ in ssh_compatible_openssl()
64 hfix = (headerver & 0x000ff000) >> 12; in ssh_compatible_openssl()
65 lfix = (libver & 0x000ff000) >> 12; in ssh_compatible_openssl()
68 return 0; in ssh_compatible_openssl()
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
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H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852b_rfk.c16 #define RTW8852B_RXDCK_VER 0x1
17 #define RTW8852B_IQK_VER 0x2a
22 #define RTW8852B_DPK_VER 0x0d
28 #define DPK_TXAGC_LOWER 0x2e
29 #define DPK_TXAGC_UPPER 0x3f
30 #define DPK_TXAGC_INVAL 0xff
31 #define RFREG_MASKRXBB 0x003e0
32 #define RFREG_MASKMODE 0xf0000
35 LBK_RXIQK = 0x06,
36 SYNC = 0x1
[all...]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x0000000
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/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h24 #define AR_BT_COEX_MODE 0x8170
25 #define AR_BT_TIME_EXTEND 0x000000ff
26 #define AR_BT_TIME_EXTEND_S 0
27 #define AR_BT_TXSTATE_EXTEND 0x00000100
29 #define AR_BT_TX_FRAME_EXTEND 0x00000200
31 #define AR_BT_MODE 0x00000c00
33 #define AR_BT_QUIET 0x00001000
35 #define AR_BT_QCU_THRESH 0x0001e000
37 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
39 #define AR_BT_PRIORITY_TIME 0x00fc0000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
[all...]
/freebsd/contrib/llvm-project/lldb/include/lldb/Utility/
H A DArchSpec.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
51 eMIPSAse_dsp = 0x00000001, // DSP ASE
52 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE
53 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme
54 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE
55 eMIPSAse_mdmx = 0x00000010, // MDMX ASE
56 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
57 eMIPSAse_mt = 0x00000040, // MT ASE
58 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
59 eMIPSAse_virt = 0x00000100, // VZ ASE
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/sys/x86/x86/
H A Dmsi.c64 #define MSI_INTEL_ADDR_DEST 0x000ff000
65 #define MSI_INTEL_ADDR_RH 0x00000008
66 # define MSI_INTEL_ADDR_RH_ON 0x00000008
67 # define MSI_INTEL_ADDR_RH_OFF 0x00000000
68 #define MSI_INTEL_ADDR_DM 0x00000004
69 # define MSI_INTEL_ADDR_DM_PHYSICAL 0x00000000
70 # define MSI_INTEL_ADDR_DM_LOGICAL 0x00000004
76 #define MSI_INTEL_DATA_LEVEL 0x00004000 /* Polarity. */
77 # define MSI_INTEL_DATA_DEASSERT 0x00000000
78 # define MSI_INTEL_DATA_ASSERT 0x00004000
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
/freebsd/sys/dev/hyperv/pcib/
H A Dvmbus_pcib.c92 memset(c, 0, sizeof(*c)); in init_completion()
94 c->done = 0; in init_completion()
99 c->done = 0; in reinit_completion()
120 while (c->done == 0) in wait_for_completion()
121 mtx_sleep(c, &c->lock, 0, "hvwfc", 0); in wait_for_completion()
127 * Return: 0 if completed, a non-zero value if timed out.
136 if (c->done == 0) in wait_for_completion_timeout()
137 mtx_sleep(c, &c->lock, 0, "hvwfc", timeout); in wait_for_completion_timeout()
139 if (c->done > 0) { in wait_for_completion_timeout()
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/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_int.c96 #define ATTENTION_PARITY (1 << 0)
98 #define ATTENTION_LENGTH_MASK (0x00000ff0)
108 #define ATTENTION_OFFSET_MASK (0x000ff000)
111 #define ATTENTION_BB_MASK (0x00700000)
139 0xffffffff); in ecore_mcp_attn_cb()
144 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK (0x3c000)
146 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK (0x03fc0)
148 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK (0x00020)
150 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK (0x0001e)
152 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK (0x1)
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/freebsd/sys/ofed/include/rdma/
H A Dib_verbs.h98 IB_GID_TYPE_IB = 0,
99 IB_GID_TYPE_ROCE = 0,
178 IB_DEVICE_RESIZE_MAX_WR = (1 << 0),
255 IB_ODP_SUPPORT = 1 << 0,
259 IB_ODP_SUPPORT_SEND = 1 << 0,
288 IB_TM_CAP_RNDV_RC = 1 << 0,
305 IB_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 << 0,
316 IB_CQ_MODERATE = 1 << 0,
417 IB_PORT_NOP = 0,
551 /* Management 0x00000FFF */
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2700.h38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x30202024, 0x00000000, 0x0000002f, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00014f80, 0xffffffff, 0x00122004,
[all …]
H A Dasm_2600.h38 0x0501f06c, 0x0011b000, 0x00100000, 0x00011c0f,
39 0x00000008, 0x00000008, 0x000000e7, 0x0078d0d5,
40 0x00000020, 0x00000006, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x38337878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
45 0x33312020, 0x24000000, 0x00000026, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00011c0f, 0xffffffff, 0x0011b004,
[all …]
H A Dasm_2800.h38 0x0501f078, 0x00124000, 0x00100000, 0x00017380,
39 0x00000009, 0x0000000c, 0x00000001, 0x785ad0d5,
40 0x00000080, 0x0001f626, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323320, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32387878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x31202024, 0x00000000, 0x00000092, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00017380, 0xffffffff, 0x00124004,
[all …]
/freebsd/sys/dev/bxe/
H A Decore_hsi.h33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]