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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
H A Dtegra20-acer-a500-picasso.dts37 memory@0 {
38 reg = <0x00000000 0x40000000>;
48 reg = <0x2ffe0000 0x10000>; /* 64kB */
49 console-size = <0x8000>; /* 32kB */
50 record-size = <0x400>; /* 1kB */
56 alloc-ranges = <0x30000000 0x10000000>;
57 size = <0x1000000
[all...]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe0000
[all...]
H A Dtegra20-asus-tf101.dts38 memory@0 {
39 reg = <0x00000000 0x40000000>;
49 reg = <0x2ffe0000 0x10000>; /* 64kB */
50 console-size = <0x8000>; /* 32kB */
51 record-size = <0x400>; /* 1kB */
57 alloc-ranges = <0x30000000 0x10000000>;
58 size = <0x1000000
[all...]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dfsl,vf610-dac.yaml43 reg = <0x40000000 0x00070000>;
49 reg = <0x400cc000 0x1000>;
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/contrib/ncsw/inc/
H A Dxx_common.h46 #define MODULE_UNKNOWN 0x00000000
47 #define MODULE_FM 0x00010000
48 #define MODULE_FM_MURAM 0x00020000
49 #define MODULE_FM_PCD 0x00030000
50 #define MODULE_FM_RTC 0x00040000
51 #define MODULE_FM_MAC 0x00050000
52 #define MODULE_FM_PORT 0x00060000
53 #define MODULE_MM 0x00070000
54 #define MODULE_FM_SP 0x00080000
55 #define MODULE_FM_MACSEC 0x00090000
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dmac.h32 #define WMI_HOST_RC_DS_FLAG 0x01
33 #define WMI_HOST_RC_CW40_FLAG 0x02
34 #define WMI_HOST_RC_SGI_FLAG 0x04
35 #define WMI_HOST_RC_HT_FLAG 0x08
36 #define WMI_HOST_RC_RTSCTS_FLAG 0x10
37 #define WMI_HOST_RC_TX_STBC_FLAG 0x20
38 #define WMI_HOST_RC_RX_STBC_FLAG 0xC0
40 #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100
41 #define WMI_HOST_RC_TS_FLAG 0x200
42 #define WMI_HOST_RC_UAPSD_FLAG 0x400
[all …]
/freebsd/sys/arm64/include/
H A Dvfp.h37 #define VFPCR_AHP (0x04000000) /* alt. half-precision: */
38 #define VFPCR_DN (0x02000000) /* default NaN enable */
39 #define VFPCR_FZ (0x01000000) /* flush to zero enabled */
40 #define VFPCR_INIT 0 /* Default fpcr after exec */
43 #define VFPCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
44 #define VFPCR_RMODE_RN (0x00000000) /* round nearest */
45 #define VFPCR_RMODE_RPI (0x00400000) /* round to plus infinity */
46 #define VFPCR_RMODE_RNI (0x00800000) /* round to neg infinity */
47 #define VFPCR_RMODE_RM (0x00c00000) /* round to zero */
50 #define VFPCR_STRIDE_MASK (0x00300000)
[all …]
/freebsd/sys/fs/nfs/
H A Drpcv2.h47 #define RPCAUTH_NULL 0
70 #define RPCAUTHGSS_DATA 0
79 #define RPCAUTHGSS_MAXSEQ 0x80000000
90 #define GSS_KERBV_QOP 0
107 #define RPCPROG_GSSD 0x20101010
122 #define RPCPROG_NFSUSERD 0x21010101
133 #define GSS_S_COMPLETE 0x00000000
134 #define GSS_S_CONTINUE_NEEDED 0x00000001
135 #define GSS_S_DUPLICATE_TOKEN 0x00000002
136 #define GSS_S_OLD_TOKEN 0x00000004
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dhdmi.yaml91 port@0:
102 - port@0
188 reg = <0x04a00000 0x2f0>;
200 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
213 reg = <0x009a0000 0x50c>,
214 <0x00070000 0x6158>,
215 <0x009e0000 0xfff>;
238 pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
246 #size-cells = <0>;
248 port@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/realtek/
H A Drtd1195.dtsi6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0x0>;
33 reg = <0x1>;
44 reg = <0x0000b000 0x1000>;
48 reg = <0x01b00000 0x400000>;
52 reg = <0x01ffe000 0x4000>;
[all …]
/freebsd/sys/arm/include/
H A Dvfp.h44 #define VFPSID_IMPLEMENTOR_MASK (0xff000000)
45 #define VFPSID_HARDSOFT_IMP (0x00800000)
48 #define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
49 #define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
50 #define VFP_ARCH1 0x0
51 #define VFP_ARCH2 0x1
52 #define VFP_ARCH3 0x2
54 #define VFPSID_PARTNUMBER_MASK (0x0000ff00)
56 #define VFPSID_VARIANT_MASK (0x000000f0)
57 #define VFPSID_REVISION_MASK 0x0f
[all …]
/freebsd/sys/dev/sound/pci/
H A Des137x.h34 #define ES1370_REG_CONTROL 0x00
35 #define ES1370_REG_STATUS 0x04
36 #define ES1370_REG_UART_DATA 0x08
37 #define ES1370_REG_UART_STATUS 0x09
38 #define ES1370_REG_UART_CONTROL 0x09
39 #define ES1370_REG_UART_TEST 0x0a
40 #define ES1370_REG_MEMPAGE 0x0c
41 #define ES1370_REG_CODEC 0x10
43 #define ES1370_REG_SERIAL_CONTROL 0x20
44 #define ES1370_REG_DAC1_SCOUNT 0x24
[all …]
/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0x0>;
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
53 clock-frequency = <0>;
59 reg = <0x0>;
62 d-cache-size = <0x8000>; // L1, 32K
63 i-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_enet.h41 E_ENET_IF_MII = 0x00010000, /**< MII interface */
42 E_ENET_IF_RMII = 0x00020000, /**< RMII interface */
43 E_ENET_IF_SMII = 0x00030000, /**< SMII interface */
44 E_ENET_IF_GMII = 0x00040000, /**< GMII interface */
45 E_ENET_IF_RGMII = 0x00050000, /**< RGMII interface */
46 E_ENET_IF_TBI = 0x00060000, /**< TBI interface */
47 E_ENET_IF_RTBI = 0x00070000, /**< RTBI interface */
48 E_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */
49 E_ENET_IF_XGMII = 0x00090000, /**< XGMII interface */
50 E_ENET_IF_QSGMII = 0x000a0000, /**< QSGMII interface */
[all …]
/freebsd/contrib/ntp/sntp/libopts/
H A Dag-char-map.h51 #if 0 /* mapping specification source (from autogen.map) */
81 // oct-digit "0-7"
111 #endif /* 0 -- mapping spec. source */
116 #define IS_NEWLINE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000001)
117 #define SPN_NEWLINE_CHARS(_s) spn_ag_char_map_chars(_s, 0)
118 #define BRK_NEWLINE_CHARS(_s) brk_ag_char_map_chars(_s, 0)
119 #define SPN_NEWLINE_BACK(s,e) spn_ag_char_map_back(s, e, 0)
120 #define BRK_NEWLINE_BACK(s,e) brk_ag_char_map_back(s, e, 0)
121 #define IS_NUL_BYTE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000002)
126 #define IS_DIR_SEP_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000004)
[all …]
/freebsd/sys/dev/sis/
H A Dif_sisreg.h45 #define SIS_CSR 0x00
46 #define SIS_CFG 0x04
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
49 #define SIS_ISR 0x10
50 #define SIS_IMR 0x14
51 #define SIS_IER 0x18
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]

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