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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
/linux/arch/arm/include/debug/
H A Dsa1100.S10 #define UTCR3 0x0c
11 #define UTDR 0x14
12 #define UTSR1 0x20
13 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
14 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
15 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
18 mrc p15, 0, \rp, c1, c0
20 moveq \rp, #0x80000000 @ physical base address
21 movne \rp, #0xf8000000 @ virtual address
28 add \rp, \rp, #0x00050000
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi8 #clock-cells = <0>;
17 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
20 reg = <0x58400000 0x00050000>;
32 reg = <0x58450000 0x00050000>;
45 reg = <0x585d0000 0x10000>;
57 reg = <0x585f0000 0x10000>;
/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx8-jpeg.yaml71 reg = <0x58400000 0x00050000 >;
87 reg = <0x58450000 0x00050000 >;
/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62.dtsi55 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
56 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
57 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
58 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
59 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
60 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
61 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
62 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
63 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
64 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
/linux/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_specs_47x.h11 .pvr_mask = 0xffffffff,
12 .pvr_value = 0x11a52080,
24 .pvr_mask = 0xffff0000,
25 .pvr_value = 0x7ff50000,
37 .pvr_mask = 0xffff0000,
38 .pvr_value = 0x00050000,
50 .pvr_mask = 0xffff0000,
51 .pvr_value = 0x11a50000,
63 .pvr_mask = 0x00000000,
64 .pvr_value = 0x00000000,
/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/linux/drivers/of/unittest-data/
H A Doverlay_common.dtsi19 reg = <0x00000100 0x100>;
50 reg = <0x00000100 0x100>;
60 reg = <0x00000030 0x10>;
64 reg = <0x00000040 0x10>;
72 reg = <0x00030000 0x1000>;
78 reg = <0x00040000 0x1000>;
84 reg = <0x00050000 0x1000>;
/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h36 #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
37 #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
38 #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
39 #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
43 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
49 #define IO_EXTENDED_ERROR_POINTER 0x00000048
50 #define IO_ERROR_INJECT_SELECTOR 0x00000060
51 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070
52 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078
53 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/net/smc/
H A Dsmc_llc.h18 #define SMC_LLC_FLAG_RESP 0x80
30 SMC_LLC_CONFIRM_LINK = 0x01,
31 SMC_LLC_ADD_LINK = 0x02,
32 SMC_LLC_ADD_LINK_CONT = 0x03,
33 SMC_LLC_DELETE_LINK = 0x04,
34 SMC_LLC_REQ_ADD_LINK = 0x05,
35 SMC_LLC_CONFIRM_RKEY = 0x06,
36 SMC_LLC_TEST_LINK = 0x07,
37 SMC_LLC_CONFIRM_RKEY_CONT = 0x08,
38 SMC_LLC_DELETE_RKEY = 0x09,
[all …]
/linux/sound/soc/fsl/
H A Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]
/linux/arch/arm/vfp/
H A Dvfpinstr.h10 #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
15 #define INST_CPNUM(inst) ((inst) & 0xf00)
18 #define FOP_MASK (0x00b00040)
19 #define FOP_FMAC (0x00000000)
20 #define FOP_FNMAC (0x00000040)
21 #define FOP_FMSC (0x00100000)
22 #define FOP_FNMSC (0x00100040)
23 #define FOP_FMUL (0x00200000)
24 #define FOP_FNMUL (0x00200040)
25 #define FOP_FADD (0x00300000)
[all …]
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_vf_regs.h8 #define VFGEN_RSTAT 0x00008800
9 #define VFGEN_RSTAT_VFR_STATE_S 0
10 #define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0)
13 #define VF_BASE 0x00006000
15 #define VF_ATQBAL (VF_BASE + 0x1C00)
16 #define VF_ATQBAH (VF_BASE + 0x1800)
17 #define VF_ATQLEN (VF_BASE + 0x0800)
18 #define VF_ATQLEN_ATQLEN_S 0
19 #define VF_ATQLEN_ATQLEN_M GENMASK(9, 0)
28 #define VF_ATQH (VF_BASE + 0x0400)
[all …]
/linux/lib/
H A Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_pci.h16 #define PCI_FSL_BRR1 0xbf8
17 #define PCI_FSL_BRR1_VER 0xffff
19 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
20 #define PCIE_LTSSM_L0 0x16 /* L0 state */
21 #define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
22 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
24 #define PIWAR_EN 0x80000000 /* Enable */
25 #define PIWAR_PF 0x20000000 /* prefetch */
26 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
[all …]
/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_common.h32 PISP_BAYER_ORDER_RGGB = 0,
45 PISP_IMAGE_FORMAT_BPS_8 = 0x00000000,
46 PISP_IMAGE_FORMAT_BPS_10 = 0x00000001,
47 PISP_IMAGE_FORMAT_BPS_12 = 0x00000002,
48 PISP_IMAGE_FORMAT_BPS_16 = 0x00000003,
49 PISP_IMAGE_FORMAT_BPS_MASK = 0x00000003,
51 PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED = 0x00000000,
52 PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR = 0x00000010,
53 PISP_IMAGE_FORMAT_PLANARITY_PLANAR = 0x00000020,
54 PISP_IMAGE_FORMAT_PLANARITY_MASK = 0x00000030,
[all …]
/linux/drivers/pinctrl/visconti/
H A Dpinctrl-tmpv7700.c15 #define tmpv7700_MAGIC_NUM 0x4932f70e
18 #define REG_KEY_CTRL 0x0000
19 #define REG_KEY_CMD 0x0004
20 #define REG_PINMUX1 0x3000
21 #define REG_PINMUX2 0x3004
22 #define REG_PINMUX3 0x3008
23 #define REG_PINMUX4 0x300c
24 #define REG_PINMUX5 0x3010
25 #define REG_IOSET 0x3014
26 #define REG_IO_VSEL 0x3018
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]
/linux/arch/loongarch/include/asm/
H A Dloongson.h20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
34 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
35 #define LOONGSON_GPIOIE LOONGSON_REG(0x120)
36 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
46 " st.w %[v], %[hw], 0 \n" in xconf_writel()
[all …]

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