Lines Matching +full:0 +full:x00050000
5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
21 #define NV03_PFIFO_CACHES 0x00002500
22 #define NV04_PFIFO_MODE 0x00002504
23 #define NV04_PFIFO_DMA 0x00002508
24 #define NV04_PFIFO_SIZE 0x0000250c
25 #define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)
29 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF
30 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF
31 #define NV03_PFIFO_CACHE0_PUSH0 0x00003000
32 #define NV03_PFIFO_CACHE0_PULL0 0x00003040
33 #define NV04_PFIFO_CACHE0_PULL0 0x00003050
34 #define NV04_PFIFO_CACHE0_PULL1 0x00003054
35 #define NV03_PFIFO_CACHE1_PUSH0 0x00003200
36 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204
39 #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f
40 #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f
41 #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f
42 #define NV03_PFIFO_CACHE1_PUT 0x00003210
43 #define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
44 #define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
45 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
46 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
47 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
48 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
49 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
50 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
51 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
52 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
53 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
54 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
55 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
56 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
57 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
58 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
59 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
60 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
61 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
62 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
63 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
64 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
65 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
66 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
67 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
68 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
69 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
70 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
71 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
72 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
73 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
74 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
75 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
76 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
77 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
78 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
79 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
80 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
81 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
82 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
83 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
84 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
85 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
86 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
87 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
88 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
89 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
90 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
91 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
92 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
93 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
94 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
95 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
96 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
97 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
98 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
99 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
100 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
101 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
102 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
103 # define NV_PFIFO_CACHE1_ENDIAN 0x80000000
104 # define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
105 # define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
106 #define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
107 #define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
108 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
109 #define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
110 #define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
111 #define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
112 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
113 #define NV03_PFIFO_CACHE1_PULL0 0x00003240
114 #define NV04_PFIFO_CACHE1_PULL0 0x00003250
115 # define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010
116 # define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000
117 #define NV03_PFIFO_CACHE1_PULL1 0x00003250
118 #define NV04_PFIFO_CACHE1_PULL1 0x00003254
119 #define NV04_PFIFO_CACHE1_HASH 0x00003258
120 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
121 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
122 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
123 #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
124 #define NV03_PFIFO_CACHE1_GET 0x00003270
125 #define NV04_PFIFO_CACHE1_ENGINE 0x00003280
126 #define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
127 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
128 #define NV40_PFIFO_UNK32E4 0x000032E4
129 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
130 #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
131 #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
132 #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))