Lines Matching +full:0 +full:x00050000
10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
46 #define CCSR_DMA_MR_DAHTS_8 0x00030000
47 #define CCSR_DMA_MR_SAHTS_MASK 0x0000C000
48 #define CCSR_DMA_MR_SAHTS_1 0x00000000
49 #define CCSR_DMA_MR_SAHTS_2 0x00004000
50 #define CCSR_DMA_MR_SAHTS_4 0x00008000
51 #define CCSR_DMA_MR_SAHTS_8 0x0000C000
52 #define CCSR_DMA_MR_DAHE 0x00002000
53 #define CCSR_DMA_MR_SAHE 0x00001000
54 #define CCSR_DMA_MR_SRW 0x00000400
55 #define CCSR_DMA_MR_EOSIE 0x00000200
56 #define CCSR_DMA_MR_EOLNIE 0x00000100
57 #define CCSR_DMA_MR_EOLSIE 0x00000080
58 #define CCSR_DMA_MR_EIE 0x00000040
59 #define CCSR_DMA_MR_XFE 0x00000020
60 #define CCSR_DMA_MR_CDSM_SWSM 0x00000010
61 #define CCSR_DMA_MR_CA 0x00000008
62 #define CCSR_DMA_MR_CTM 0x00000004
63 #define CCSR_DMA_MR_CC 0x00000002
64 #define CCSR_DMA_MR_CS 0x00000001
66 #define CCSR_DMA_SR_TE 0x00000080
67 #define CCSR_DMA_SR_CH 0x00000020
68 #define CCSR_DMA_SR_PE 0x00000010
69 #define CCSR_DMA_SR_EOLNI 0x00000008
70 #define CCSR_DMA_SR_CB 0x00000004
71 #define CCSR_DMA_SR_EOSI 0x00000002
72 #define CCSR_DMA_SR_EOLSI 0x00000001
77 return (x >> 32) & 0xf; in CCSR_DMA_ECLNDAR_ADDR()
80 #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
81 #define CCSR_DMA_CLNDAR_EOSIE 0x00000008
84 #define CCSR_DMA_ATR_PBATMU 0x20000000
85 #define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000
86 #define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000
87 #define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000
88 #define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000
89 #define CCSR_DMA_ATR_PCIORDER 0x02000000
90 #define CCSR_DMA_ATR_SME 0x01000000
91 #define CCSR_DMA_ATR_NOSNOOP 0x00040000
92 #define CCSR_DMA_ATR_SNOOP 0x00050000
93 #define CCSR_DMA_ATR_ESAD_MASK 0x0000000F