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12

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_renderstate.c11 0x00000020,
12 0x00000024,
13 0x0000002c,
14 0x000001e0,
15 0x000001e4,
20 0x69040000,
21 0x790d0001,
22 0x00000000,
23 0x00000000,
24 0x78180000,
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dclc57e.h27 #define NVC57E_SET_SIZE (0x00000224)
28 #define NVC57E_SET_SIZE_WIDTH 15:0
30 #define NVC57E_SET_STORAGE (0x00000228)
31 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0
32 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
33 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
34 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
35 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
36 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
37 #define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
[all …]
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/linux/drivers/media/pci/cx23885/
H A Dcx23885-reg.h13 0x00000000 -> 0x00009000 TX SRAM (Fifos)
14 0x00010000 -> 0x00013c00 RX SRAM CMDS + CDT
16 EACH CMDS struct is 0x80 bytes long
18 DMAx_PTR1 = 0x03040 address of first cluster
19 DMAx_PTR2 = 0x10600 address of the CDT
24 DWORD 0 -> ptr to cluster
30 0 IntialProgramCounterLow
41 #define RISC_CNT_INC 0x00010000
42 #define RISC_CNT_RESET 0x00030000
43 #define RISC_IRQ1 0x01000000
[all …]
/linux/drivers/net/wireless/ath/ath6kl/
H A Dtarget.h26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
[all …]
/linux/drivers/net/ethernet/sfc/
H A Def10_regs.h40 #define ER_DZ_BIU_HW_REV_ID 0x00000000
41 #define ERF_DZ_HW_REV_ID_LBN 0
45 #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010
48 #define ERF_DZ_MC_SFT_STATUS_LBN 0
52 #define ER_DZ_BIU_INT_ISR 0x00000090
53 #define ERF_DZ_ISR_REG_LBN 0
57 #define ER_DZ_MC_DB_LWRD 0x00000200
58 #define ERF_DZ_MC_DOORBELL_L_LBN 0
62 #define ER_DZ_MC_DB_HWRD 0x00000204
63 #define ERF_DZ_MC_DOORBELL_H_LBN 0
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h6 #define MCDE_IMSCPP 0x00000104
7 #define MCDE_RISPP 0x00000114
8 #define MCDE_MISPP 0x00000124
9 #define MCDE_SISPP 0x00000134
11 #define MCDE_PP_VCMPA BIT(0)
21 #define MCDE_IMSCOVL 0x00000108
22 #define MCDE_RISOVL 0x00000118
23 #define MCDE_MISOVL 0x00000128
24 #define MCDE_SISOVL 0x00000138
27 #define MCDE_IMSCCHNL 0x0000010C
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/drivers/pci/controller/
H A Dpcie-xilinx-nwl.c30 #define BRCFG_PCIE_RX0 0x00000000
31 #define BRCFG_PCIE_RX1 0x00000004
32 #define BRCFG_INTERRUPT 0x00000010
33 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
36 #define E_BREG_CAPABILITIES 0x00000200
37 #define E_BREG_CONTROL 0x00000208
38 #define E_BREG_BASE_LO 0x00000210
39 #define E_BREG_BASE_HI 0x00000214
40 #define E_ECAM_CAPABILITIES 0x00000220
41 #define E_ECAM_CONTROL 0x00000228
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dfarch_regs.h44 #define FR_AZ_ADR_REGION 0x00000000
51 #define FRF_AZ_ADR_REGION0_LBN 0
55 #define FR_AZ_INT_EN_KER 0x00000010
62 #define FRF_AZ_DRV_INT_EN_KER_LBN 0
66 #define FR_BZ_INT_EN_CHAR 0x00000020
73 #define FRF_BZ_DRV_INT_EN_CHAR_LBN 0
77 #define FR_AZ_INT_ADR_KER 0x00000030
80 #define FRF_AZ_INT_ADR_KER_LBN 0
84 #define FR_BZ_INT_ADR_CHAR 0x00000040
87 #define FRF_BZ_INT_ADR_CHAR_LBN 0
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dfarch_regs.h44 #define FR_AZ_ADR_REGION 0x00000000
51 #define FRF_AZ_ADR_REGION0_LBN 0
55 #define FR_AZ_INT_EN_KER 0x00000010
62 #define FRF_AZ_DRV_INT_EN_KER_LBN 0
66 #define FR_BZ_INT_EN_CHAR 0x00000020
73 #define FRF_BZ_DRV_INT_EN_CHAR_LBN 0
77 #define FR_AZ_INT_ADR_KER 0x00000030
80 #define FRF_AZ_INT_ADR_KER_LBN 0
84 #define FR_BZ_INT_ADR_CHAR 0x00000040
87 #define FRF_BZ_INT_ADR_CHAR_LBN 0
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal()
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); in carl9170_init_power_cal()
[all …]
/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_regs.h46 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
51 #define A_MC_BASE_0 0x0010051000
52 #define A_MC_BASE_1 0x0010052000
53 #define MC_REGISTER_SPACING 0x1000
58 #define R_MC_CONFIG 0x0000000100
59 #define R_MC_DRAMCMD 0x0000000120
60 #define R_MC_DRAMMODE 0x0000000140
61 #define R_MC_TIMING1 0x0000000160
62 #define R_MC_TIMING2 0x0000000180
63 #define R_MC_CS_START 0x00000001A0
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c31 #define AR5008_11NA_OFDM_SHIFT 0
55 {0x000098b0, 0x1e5795e5},
56 {0x000098e0, 0x02008020},
61 {0x000098b0, 0x02108421},
62 {0x000098ec, 0x00000008},
67 {0x000098b0, 0x0e73ff17},
68 {0x000098e0, 0x00000420},
73 {0x000098f0, 0x01400018, 0x01c00018},
78 {0x0000989c, 0x00000500},
79 {0x0000989c, 0x00000800},
[all …]
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
/linux/drivers/mfd/
H A Dwm8998-tables.c22 { 0x0212, 0x0000 },
23 { 0x0211, 0x0014 },
24 { 0x04E4, 0x0E0D },
25 { 0x04E5, 0x0E0D },
26 { 0x04E6, 0x0E0D },
27 { 0x04EB, 0x060E },
28 { 0x0441, 0xC759 },
29 { 0x0442, 0x2A08 },
30 { 0x0443, 0x5CFA },
31 { 0x026E, 0x0064 },
[all …]
H A Dwm8997-tables.c18 { 0x80, 0x0003 },
19 { 0x214, 0x0008 },
20 { 0x458, 0x0000 },
21 { 0x0081, 0xE022 },
22 { 0x294, 0x0000 },
23 { 0x80, 0x0000 },
24 { 0x171, 0x0000 },
31 case 0: in wm8997_patch()
36 return 0; in wm8997_patch()
60 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[all …]
H A Dwm5102-tables.c22 { 0x80, 0x0003 },
23 { 0x221, 0x0090 },
24 { 0x211, 0x0014 },
25 { 0x212, 0x0000 },
26 { 0x214, 0x000C },
27 { 0x171, 0x0002 },
28 { 0x171, 0x0000 },
29 { 0x461, 0x8000 },
30 { 0x463, 0x50F0 },
31 { 0x465, 0x4820 },
[all …]
H A Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
H A Dwm5110-tables.c22 { 0x80, 0x3 },
23 { 0x44, 0x20 },
24 { 0x45, 0x40 },
25 { 0x46, 0x60 },
26 { 0x47, 0x80 },
27 { 0x48, 0xa0 },
28 { 0x51, 0x13 },
29 { 0x52, 0x33 },
30 { 0x53, 0x53 },
31 { 0x54, 0x73 },
[all …]
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]

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