30 #define BRCFG_PCIE_RX0			0x00000000
31 #define BRCFG_PCIE_RX1			0x00000004
32 #define BRCFG_INTERRUPT			0x00000010
33 #define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
36 #define E_BREG_CAPABILITIES		0x00000200
37 #define E_BREG_CONTROL			0x00000208
38 #define E_BREG_BASE_LO			0x00000210
39 #define E_BREG_BASE_HI			0x00000214
40 #define E_ECAM_CAPABILITIES		0x00000220
41 #define E_ECAM_CONTROL			0x00000228
42 #define E_ECAM_BASE_LO			0x00000230
43 #define E_ECAM_BASE_HI			0x00000234
46 #define I_MSII_CAPABILITIES		0x00000300
47 #define I_MSII_CONTROL			0x00000308
48 #define I_MSII_BASE_LO			0x00000310
49 #define I_MSII_BASE_HI			0x00000314
51 #define I_ISUB_CONTROL			0x000003E8
52 #define SET_ISUB_CONTROL		BIT(0)
54 #define MSGF_MISC_STATUS		0x00000400
55 #define MSGF_MISC_MASK			0x00000404
56 #define MSGF_LEG_STATUS			0x00000420
57 #define MSGF_LEG_MASK			0x00000424
58 #define MSGF_MSI_STATUS_LO		0x00000440
59 #define MSGF_MSI_STATUS_HI		0x00000444
60 #define MSGF_MSI_MASK_LO		0x00000448
61 #define MSGF_MSI_MASK_HI		0x0000044C
72 #define MSGF_MISC_SR_RXMSG_AVAIL	BIT(0)
105 #define MSGF_LEG_SR_INTA		BIT(0)
113 #define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
114 #define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
116 #define MSII_PRESENT			BIT(0)
117 #define MSII_ENABLE			BIT(0)
121 #define BRCFG_INTERRUPT_MASK		BIT(0)
122 #define BREG_PRESENT			BIT(0)
123 #define BREG_ENABLE			BIT(0)
127 #define E_ECAM_PRESENT			BIT(0)
128 #define E_ECAM_CR_ENABLE		BIT(0)
133 #define CFG_DMA_REG_BAR			GENMASK(2, 0)
134 #define CFG_PCIE_CACHE			GENMASK(7, 0)
139 #define PS_LINKUP_OFFSET		0x00000238
140 #define PCIE_PHY_LINKUP_BIT		BIT(0)
206 	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {  in nwl_wait_for_link()
208 			return 0;  in nwl_wait_for_link()
224 	} else if (devfn > 0)  in nwl_pcie_valid_device()
327 				MSGF_LEG_SR_MASKALL) != 0) {  in nwl_pcie_leg_handler()
341 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {  in nwl_pcie_handle_msi_irq()
412 	return 0;  in nwl_intx_map()
465 	if (bit < 0) {  in nwl_irq_domain_alloc()
470 	for (i = 0; i < nr_irqs; i++) {  in nwl_irq_domain_alloc()
476 	return 0;  in nwl_irq_domain_alloc()
515 	return 0;  in nwl_pcie_init_msi_irq_domain()
539 	for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {  in nwl_pcie_phy_enable()
551 	return 0;  in nwl_pcie_phy_enable()
594 	return 0;  in nwl_pcie_init_irq_domain()
609 	if (msi->irq_msi1 < 0)  in nwl_pcie_enable_msi()
617 	if (msi->irq_msi0 < 0)  in nwl_pcie_enable_msi()
647 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
658 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
665 	return 0;  in nwl_pcie_enable_msi()
738 	if (pcie->irq_misc < 0)  in nwl_pcie_bridge_init()
774 	return 0;  in nwl_pcie_bridge_init()
804 	if (pcie->irq_intx < 0)  in nwl_pcie_parse_dt()
811 	for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {  in nwl_pcie_parse_dt()
822 	return 0;  in nwl_pcie_parse_dt()
885 		if (err < 0) {  in nwl_pcie_probe()
893 		return 0;  in nwl_pcie_probe()