1*6e173d3bSMartin Habets /* SPDX-License-Identifier: GPL-2.0-only */ 2*6e173d3bSMartin Habets /**************************************************************************** 3*6e173d3bSMartin Habets * Driver for Solarflare network controllers and boards 4*6e173d3bSMartin Habets * Copyright 2005-2006 Fen Systems Ltd. 5*6e173d3bSMartin Habets * Copyright 2006-2012 Solarflare Communications Inc. 6*6e173d3bSMartin Habets */ 7*6e173d3bSMartin Habets 8*6e173d3bSMartin Habets #ifndef EFX_FARCH_REGS_H 9*6e173d3bSMartin Habets #define EFX_FARCH_REGS_H 10*6e173d3bSMartin Habets 11*6e173d3bSMartin Habets /* 12*6e173d3bSMartin Habets * Falcon hardware architecture definitions have a name prefix following 13*6e173d3bSMartin Habets * the format: 14*6e173d3bSMartin Habets * 15*6e173d3bSMartin Habets * F<type>_<min-rev><max-rev>_ 16*6e173d3bSMartin Habets * 17*6e173d3bSMartin Habets * The following <type> strings are used: 18*6e173d3bSMartin Habets * 19*6e173d3bSMartin Habets * MMIO register MC register Host memory structure 20*6e173d3bSMartin Habets * ------------------------------------------------------------- 21*6e173d3bSMartin Habets * Address R MCR 22*6e173d3bSMartin Habets * Bitfield RF MCRF SF 23*6e173d3bSMartin Habets * Enumerator FE MCFE SE 24*6e173d3bSMartin Habets * 25*6e173d3bSMartin Habets * <min-rev> is the first revision to which the definition applies: 26*6e173d3bSMartin Habets * 27*6e173d3bSMartin Habets * A: Falcon A1 (SFC4000AB) 28*6e173d3bSMartin Habets * B: Falcon B0 (SFC4000BA) 29*6e173d3bSMartin Habets * C: Siena A0 (SFL9021AA) 30*6e173d3bSMartin Habets * 31*6e173d3bSMartin Habets * If the definition has been changed or removed in later revisions 32*6e173d3bSMartin Habets * then <max-rev> is the last revision to which the definition applies; 33*6e173d3bSMartin Habets * otherwise it is "Z". 34*6e173d3bSMartin Habets */ 35*6e173d3bSMartin Habets 36*6e173d3bSMartin Habets /************************************************************************** 37*6e173d3bSMartin Habets * 38*6e173d3bSMartin Habets * Falcon/Siena registers and descriptors 39*6e173d3bSMartin Habets * 40*6e173d3bSMartin Habets ************************************************************************** 41*6e173d3bSMartin Habets */ 42*6e173d3bSMartin Habets 43*6e173d3bSMartin Habets /* ADR_REGION_REG: Address region register */ 44*6e173d3bSMartin Habets #define FR_AZ_ADR_REGION 0x00000000 45*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION3_LBN 96 46*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION3_WIDTH 18 47*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION2_LBN 64 48*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION2_WIDTH 18 49*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION1_LBN 32 50*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION1_WIDTH 18 51*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION0_LBN 0 52*6e173d3bSMartin Habets #define FRF_AZ_ADR_REGION0_WIDTH 18 53*6e173d3bSMartin Habets 54*6e173d3bSMartin Habets /* INT_EN_REG_KER: Kernel driver Interrupt enable register */ 55*6e173d3bSMartin Habets #define FR_AZ_INT_EN_KER 0x00000010 56*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 57*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 58*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_CHAR_LBN 4 59*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_CHAR_WIDTH 1 60*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_KER_LBN 3 61*6e173d3bSMartin Habets #define FRF_AZ_KER_INT_KER_WIDTH 1 62*6e173d3bSMartin Habets #define FRF_AZ_DRV_INT_EN_KER_LBN 0 63*6e173d3bSMartin Habets #define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 64*6e173d3bSMartin Habets 65*6e173d3bSMartin Habets /* INT_EN_REG_CHAR: Char Driver interrupt enable register */ 66*6e173d3bSMartin Habets #define FR_BZ_INT_EN_CHAR 0x00000020 67*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_LEVE_SEL_LBN 8 68*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 6 69*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_CHAR_LBN 4 70*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_CHAR_WIDTH 1 71*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_KER_LBN 3 72*6e173d3bSMartin Habets #define FRF_BZ_CHAR_INT_KER_WIDTH 1 73*6e173d3bSMartin Habets #define FRF_BZ_DRV_INT_EN_CHAR_LBN 0 74*6e173d3bSMartin Habets #define FRF_BZ_DRV_INT_EN_CHAR_WIDTH 1 75*6e173d3bSMartin Habets 76*6e173d3bSMartin Habets /* INT_ADR_REG_KER: Interrupt host address for Kernel driver */ 77*6e173d3bSMartin Habets #define FR_AZ_INT_ADR_KER 0x00000030 78*6e173d3bSMartin Habets #define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 79*6e173d3bSMartin Habets #define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 80*6e173d3bSMartin Habets #define FRF_AZ_INT_ADR_KER_LBN 0 81*6e173d3bSMartin Habets #define FRF_AZ_INT_ADR_KER_WIDTH 64 82*6e173d3bSMartin Habets 83*6e173d3bSMartin Habets /* INT_ADR_REG_CHAR: Interrupt host address for Char driver */ 84*6e173d3bSMartin Habets #define FR_BZ_INT_ADR_CHAR 0x00000040 85*6e173d3bSMartin Habets #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 64 86*6e173d3bSMartin Habets #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 87*6e173d3bSMartin Habets #define FRF_BZ_INT_ADR_CHAR_LBN 0 88*6e173d3bSMartin Habets #define FRF_BZ_INT_ADR_CHAR_WIDTH 64 89*6e173d3bSMartin Habets 90*6e173d3bSMartin Habets /* INT_ACK_KER: Kernel interrupt acknowledge register */ 91*6e173d3bSMartin Habets #define FR_AA_INT_ACK_KER 0x00000050 92*6e173d3bSMartin Habets #define FRF_AA_INT_ACK_KER_FIELD_LBN 0 93*6e173d3bSMartin Habets #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 94*6e173d3bSMartin Habets 95*6e173d3bSMartin Habets /* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */ 96*6e173d3bSMartin Habets #define FR_BZ_INT_ISR0 0x00000090 97*6e173d3bSMartin Habets #define FRF_BZ_INT_ISR_REG_LBN 0 98*6e173d3bSMartin Habets #define FRF_BZ_INT_ISR_REG_WIDTH 64 99*6e173d3bSMartin Habets 100*6e173d3bSMartin Habets /* HW_INIT_REG: Hardware initialization register */ 101*6e173d3bSMartin Habets #define FR_AZ_HW_INIT 0x000000c0 102*6e173d3bSMartin Habets #define FRF_BB_BDMRD_CPLF_FULL_LBN 124 103*6e173d3bSMartin Habets #define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 104*6e173d3bSMartin Habets #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 105*6e173d3bSMartin Habets #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 106*6e173d3bSMartin Habets #define FRF_CZ_TX_MRG_TAGS_LBN 120 107*6e173d3bSMartin Habets #define FRF_CZ_TX_MRG_TAGS_WIDTH 1 108*6e173d3bSMartin Habets #define FRF_AB_TRGT_MASK_ALL_LBN 100 109*6e173d3bSMartin Habets #define FRF_AB_TRGT_MASK_ALL_WIDTH 1 110*6e173d3bSMartin Habets #define FRF_AZ_DOORBELL_DROP_LBN 92 111*6e173d3bSMartin Habets #define FRF_AZ_DOORBELL_DROP_WIDTH 8 112*6e173d3bSMartin Habets #define FRF_AB_TX_RREQ_MASK_EN_LBN 76 113*6e173d3bSMartin Habets #define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 114*6e173d3bSMartin Habets #define FRF_AB_PE_EIDLE_DIS_LBN 75 115*6e173d3bSMartin Habets #define FRF_AB_PE_EIDLE_DIS_WIDTH 1 116*6e173d3bSMartin Habets #define FRF_AA_FC_BLOCKING_EN_LBN 45 117*6e173d3bSMartin Habets #define FRF_AA_FC_BLOCKING_EN_WIDTH 1 118*6e173d3bSMartin Habets #define FRF_BZ_B2B_REQ_EN_LBN 45 119*6e173d3bSMartin Habets #define FRF_BZ_B2B_REQ_EN_WIDTH 1 120*6e173d3bSMartin Habets #define FRF_AA_B2B_REQ_EN_LBN 44 121*6e173d3bSMartin Habets #define FRF_AA_B2B_REQ_EN_WIDTH 1 122*6e173d3bSMartin Habets #define FRF_BB_FC_BLOCKING_EN_LBN 44 123*6e173d3bSMartin Habets #define FRF_BB_FC_BLOCKING_EN_WIDTH 1 124*6e173d3bSMartin Habets #define FRF_AZ_POST_WR_MASK_LBN 40 125*6e173d3bSMartin Habets #define FRF_AZ_POST_WR_MASK_WIDTH 4 126*6e173d3bSMartin Habets #define FRF_AZ_TLP_TC_LBN 34 127*6e173d3bSMartin Habets #define FRF_AZ_TLP_TC_WIDTH 3 128*6e173d3bSMartin Habets #define FRF_AZ_TLP_ATTR_LBN 32 129*6e173d3bSMartin Habets #define FRF_AZ_TLP_ATTR_WIDTH 2 130*6e173d3bSMartin Habets #define FRF_AB_INTB_VEC_LBN 24 131*6e173d3bSMartin Habets #define FRF_AB_INTB_VEC_WIDTH 5 132*6e173d3bSMartin Habets #define FRF_AB_INTA_VEC_LBN 16 133*6e173d3bSMartin Habets #define FRF_AB_INTA_VEC_WIDTH 5 134*6e173d3bSMartin Habets #define FRF_AZ_WD_TIMER_LBN 8 135*6e173d3bSMartin Habets #define FRF_AZ_WD_TIMER_WIDTH 8 136*6e173d3bSMartin Habets #define FRF_AZ_US_DISABLE_LBN 5 137*6e173d3bSMartin Habets #define FRF_AZ_US_DISABLE_WIDTH 1 138*6e173d3bSMartin Habets #define FRF_AZ_TLP_EP_LBN 4 139*6e173d3bSMartin Habets #define FRF_AZ_TLP_EP_WIDTH 1 140*6e173d3bSMartin Habets #define FRF_AZ_ATTR_SEL_LBN 3 141*6e173d3bSMartin Habets #define FRF_AZ_ATTR_SEL_WIDTH 1 142*6e173d3bSMartin Habets #define FRF_AZ_TD_SEL_LBN 1 143*6e173d3bSMartin Habets #define FRF_AZ_TD_SEL_WIDTH 1 144*6e173d3bSMartin Habets #define FRF_AZ_TLP_TD_LBN 0 145*6e173d3bSMartin Habets #define FRF_AZ_TLP_TD_WIDTH 1 146*6e173d3bSMartin Habets 147*6e173d3bSMartin Habets /* EE_SPI_HCMD_REG: SPI host command register */ 148*6e173d3bSMartin Habets #define FR_AB_EE_SPI_HCMD 0x00000100 149*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 150*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 151*6e173d3bSMartin Habets #define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 152*6e173d3bSMartin Habets #define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 153*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 154*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 155*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 156*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 157*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_READ_LBN 15 158*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 159*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 160*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 161*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 162*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 163*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 164*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 165*6e173d3bSMartin Habets 166*6e173d3bSMartin Habets /* USR_EV_CFG: User Level Event Configuration register */ 167*6e173d3bSMartin Habets #define FR_CZ_USR_EV_CFG 0x00000100 168*6e173d3bSMartin Habets #define FRF_CZ_USREV_DIS_LBN 16 169*6e173d3bSMartin Habets #define FRF_CZ_USREV_DIS_WIDTH 1 170*6e173d3bSMartin Habets #define FRF_CZ_DFLT_EVQ_LBN 0 171*6e173d3bSMartin Habets #define FRF_CZ_DFLT_EVQ_WIDTH 10 172*6e173d3bSMartin Habets 173*6e173d3bSMartin Habets /* EE_SPI_HADR_REG: SPI host address register */ 174*6e173d3bSMartin Habets #define FR_AB_EE_SPI_HADR 0x00000110 175*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 176*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 177*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HADR_ADR_LBN 0 178*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 179*6e173d3bSMartin Habets 180*6e173d3bSMartin Habets /* EE_SPI_HDATA_REG: SPI host data register */ 181*6e173d3bSMartin Habets #define FR_AB_EE_SPI_HDATA 0x00000120 182*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA3_LBN 96 183*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA3_WIDTH 32 184*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA2_LBN 64 185*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA2_WIDTH 32 186*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA1_LBN 32 187*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA1_WIDTH 32 188*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA0_LBN 0 189*6e173d3bSMartin Habets #define FRF_AB_EE_SPI_HDATA0_WIDTH 32 190*6e173d3bSMartin Habets 191*6e173d3bSMartin Habets /* EE_BASE_PAGE_REG: Expansion ROM base mirror register */ 192*6e173d3bSMartin Habets #define FR_AB_EE_BASE_PAGE 0x00000130 193*6e173d3bSMartin Habets #define FRF_AB_EE_EXPROM_MASK_LBN 16 194*6e173d3bSMartin Habets #define FRF_AB_EE_EXPROM_MASK_WIDTH 13 195*6e173d3bSMartin Habets #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 196*6e173d3bSMartin Habets #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 197*6e173d3bSMartin Habets 198*6e173d3bSMartin Habets /* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */ 199*6e173d3bSMartin Habets #define FR_AB_EE_VPD_CFG0 0x00000140 200*6e173d3bSMartin Habets #define FRF_AB_EE_SF_FASTRD_EN_LBN 127 201*6e173d3bSMartin Habets #define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 202*6e173d3bSMartin Habets #define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 203*6e173d3bSMartin Habets #define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 204*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_WIP_POLL_LBN 119 205*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 206*6e173d3bSMartin Habets #define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 207*6e173d3bSMartin Habets #define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 208*6e173d3bSMartin Habets #define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 209*6e173d3bSMartin Habets #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 210*6e173d3bSMartin Habets #define FRF_AB_EE_VPDW_LENGTH_LBN 80 211*6e173d3bSMartin Habets #define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 212*6e173d3bSMartin Habets #define FRF_AB_EE_VPDW_BASE_LBN 64 213*6e173d3bSMartin Habets #define FRF_AB_EE_VPDW_BASE_WIDTH 15 214*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 215*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 216*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_BASE_LBN 32 217*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_BASE_WIDTH 24 218*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_LENGTH_LBN 16 219*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_LENGTH_WIDTH 15 220*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_AD_SIZE_LBN 8 221*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 222*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 223*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 224*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 225*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 226*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 227*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 228*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 229*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 230*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_EN_LBN 0 231*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_EN_WIDTH 1 232*6e173d3bSMartin Habets 233*6e173d3bSMartin Habets /* EE_VPD_SW_CNTL_REG: VPD access SW control register */ 234*6e173d3bSMartin Habets #define FR_AB_EE_VPD_SW_CNTL 0x00000150 235*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 236*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 237*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 238*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 239*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_ADR_LBN 0 240*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 241*6e173d3bSMartin Habets 242*6e173d3bSMartin Habets /* EE_VPD_SW_DATA_REG: VPD access SW data register */ 243*6e173d3bSMartin Habets #define FR_AB_EE_VPD_SW_DATA 0x00000160 244*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_DAT_LBN 0 245*6e173d3bSMartin Habets #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 246*6e173d3bSMartin Habets 247*6e173d3bSMartin Habets /* PBMX_DBG_IADDR_REG: Capture Module address register */ 248*6e173d3bSMartin Habets #define FR_CZ_PBMX_DBG_IADDR 0x000001f0 249*6e173d3bSMartin Habets #define FRF_CZ_PBMX_DBG_IADDR_LBN 0 250*6e173d3bSMartin Habets #define FRF_CZ_PBMX_DBG_IADDR_WIDTH 32 251*6e173d3bSMartin Habets 252*6e173d3bSMartin Habets /* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */ 253*6e173d3bSMartin Habets #define FR_BB_PCIE_CORE_INDIRECT 0x000001f0 254*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 255*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 256*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 257*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 258*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 259*6e173d3bSMartin Habets #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 260*6e173d3bSMartin Habets 261*6e173d3bSMartin Habets /* PBMX_DBG_IDATA_REG: Capture Module data register */ 262*6e173d3bSMartin Habets #define FR_CZ_PBMX_DBG_IDATA 0x000001f8 263*6e173d3bSMartin Habets #define FRF_CZ_PBMX_DBG_IDATA_LBN 0 264*6e173d3bSMartin Habets #define FRF_CZ_PBMX_DBG_IDATA_WIDTH 64 265*6e173d3bSMartin Habets 266*6e173d3bSMartin Habets /* NIC_STAT_REG: NIC status register */ 267*6e173d3bSMartin Habets #define FR_AB_NIC_STAT 0x00000200 268*6e173d3bSMartin Habets #define FRF_BB_AER_DIS_LBN 34 269*6e173d3bSMartin Habets #define FRF_BB_AER_DIS_WIDTH 1 270*6e173d3bSMartin Habets #define FRF_BB_EE_STRAP_EN_LBN 31 271*6e173d3bSMartin Habets #define FRF_BB_EE_STRAP_EN_WIDTH 1 272*6e173d3bSMartin Habets #define FRF_BB_EE_STRAP_LBN 24 273*6e173d3bSMartin Habets #define FRF_BB_EE_STRAP_WIDTH 4 274*6e173d3bSMartin Habets #define FRF_BB_REVISION_ID_LBN 17 275*6e173d3bSMartin Habets #define FRF_BB_REVISION_ID_WIDTH 7 276*6e173d3bSMartin Habets #define FRF_AB_ONCHIP_SRAM_LBN 16 277*6e173d3bSMartin Habets #define FRF_AB_ONCHIP_SRAM_WIDTH 1 278*6e173d3bSMartin Habets #define FRF_AB_SF_PRST_LBN 9 279*6e173d3bSMartin Habets #define FRF_AB_SF_PRST_WIDTH 1 280*6e173d3bSMartin Habets #define FRF_AB_EE_PRST_LBN 8 281*6e173d3bSMartin Habets #define FRF_AB_EE_PRST_WIDTH 1 282*6e173d3bSMartin Habets #define FRF_AB_ATE_MODE_LBN 3 283*6e173d3bSMartin Habets #define FRF_AB_ATE_MODE_WIDTH 1 284*6e173d3bSMartin Habets #define FRF_AB_STRAP_PINS_LBN 0 285*6e173d3bSMartin Habets #define FRF_AB_STRAP_PINS_WIDTH 3 286*6e173d3bSMartin Habets 287*6e173d3bSMartin Habets /* GPIO_CTL_REG: GPIO control register */ 288*6e173d3bSMartin Habets #define FR_AB_GPIO_CTL 0x00000210 289*6e173d3bSMartin Habets #define FRF_AB_GPIO_OUT3_LBN 112 290*6e173d3bSMartin Habets #define FRF_AB_GPIO_OUT3_WIDTH 16 291*6e173d3bSMartin Habets #define FRF_AB_GPIO_IN3_LBN 104 292*6e173d3bSMartin Habets #define FRF_AB_GPIO_IN3_WIDTH 8 293*6e173d3bSMartin Habets #define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96 294*6e173d3bSMartin Habets #define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8 295*6e173d3bSMartin Habets #define FRF_AB_GPIO_OUT2_LBN 80 296*6e173d3bSMartin Habets #define FRF_AB_GPIO_OUT2_WIDTH 16 297*6e173d3bSMartin Habets #define FRF_AB_GPIO_IN2_LBN 72 298*6e173d3bSMartin Habets #define FRF_AB_GPIO_IN2_WIDTH 8 299*6e173d3bSMartin Habets #define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64 300*6e173d3bSMartin Habets #define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8 301*6e173d3bSMartin Habets #define FRF_AB_GPIO15_OEN_LBN 63 302*6e173d3bSMartin Habets #define FRF_AB_GPIO15_OEN_WIDTH 1 303*6e173d3bSMartin Habets #define FRF_AB_GPIO14_OEN_LBN 62 304*6e173d3bSMartin Habets #define FRF_AB_GPIO14_OEN_WIDTH 1 305*6e173d3bSMartin Habets #define FRF_AB_GPIO13_OEN_LBN 61 306*6e173d3bSMartin Habets #define FRF_AB_GPIO13_OEN_WIDTH 1 307*6e173d3bSMartin Habets #define FRF_AB_GPIO12_OEN_LBN 60 308*6e173d3bSMartin Habets #define FRF_AB_GPIO12_OEN_WIDTH 1 309*6e173d3bSMartin Habets #define FRF_AB_GPIO11_OEN_LBN 59 310*6e173d3bSMartin Habets #define FRF_AB_GPIO11_OEN_WIDTH 1 311*6e173d3bSMartin Habets #define FRF_AB_GPIO10_OEN_LBN 58 312*6e173d3bSMartin Habets #define FRF_AB_GPIO10_OEN_WIDTH 1 313*6e173d3bSMartin Habets #define FRF_AB_GPIO9_OEN_LBN 57 314*6e173d3bSMartin Habets #define FRF_AB_GPIO9_OEN_WIDTH 1 315*6e173d3bSMartin Habets #define FRF_AB_GPIO8_OEN_LBN 56 316*6e173d3bSMartin Habets #define FRF_AB_GPIO8_OEN_WIDTH 1 317*6e173d3bSMartin Habets #define FRF_AB_GPIO15_OUT_LBN 55 318*6e173d3bSMartin Habets #define FRF_AB_GPIO15_OUT_WIDTH 1 319*6e173d3bSMartin Habets #define FRF_AB_GPIO14_OUT_LBN 54 320*6e173d3bSMartin Habets #define FRF_AB_GPIO14_OUT_WIDTH 1 321*6e173d3bSMartin Habets #define FRF_AB_GPIO13_OUT_LBN 53 322*6e173d3bSMartin Habets #define FRF_AB_GPIO13_OUT_WIDTH 1 323*6e173d3bSMartin Habets #define FRF_AB_GPIO12_OUT_LBN 52 324*6e173d3bSMartin Habets #define FRF_AB_GPIO12_OUT_WIDTH 1 325*6e173d3bSMartin Habets #define FRF_AB_GPIO11_OUT_LBN 51 326*6e173d3bSMartin Habets #define FRF_AB_GPIO11_OUT_WIDTH 1 327*6e173d3bSMartin Habets #define FRF_AB_GPIO10_OUT_LBN 50 328*6e173d3bSMartin Habets #define FRF_AB_GPIO10_OUT_WIDTH 1 329*6e173d3bSMartin Habets #define FRF_AB_GPIO9_OUT_LBN 49 330*6e173d3bSMartin Habets #define FRF_AB_GPIO9_OUT_WIDTH 1 331*6e173d3bSMartin Habets #define FRF_AB_GPIO8_OUT_LBN 48 332*6e173d3bSMartin Habets #define FRF_AB_GPIO8_OUT_WIDTH 1 333*6e173d3bSMartin Habets #define FRF_AB_GPIO15_IN_LBN 47 334*6e173d3bSMartin Habets #define FRF_AB_GPIO15_IN_WIDTH 1 335*6e173d3bSMartin Habets #define FRF_AB_GPIO14_IN_LBN 46 336*6e173d3bSMartin Habets #define FRF_AB_GPIO14_IN_WIDTH 1 337*6e173d3bSMartin Habets #define FRF_AB_GPIO13_IN_LBN 45 338*6e173d3bSMartin Habets #define FRF_AB_GPIO13_IN_WIDTH 1 339*6e173d3bSMartin Habets #define FRF_AB_GPIO12_IN_LBN 44 340*6e173d3bSMartin Habets #define FRF_AB_GPIO12_IN_WIDTH 1 341*6e173d3bSMartin Habets #define FRF_AB_GPIO11_IN_LBN 43 342*6e173d3bSMartin Habets #define FRF_AB_GPIO11_IN_WIDTH 1 343*6e173d3bSMartin Habets #define FRF_AB_GPIO10_IN_LBN 42 344*6e173d3bSMartin Habets #define FRF_AB_GPIO10_IN_WIDTH 1 345*6e173d3bSMartin Habets #define FRF_AB_GPIO9_IN_LBN 41 346*6e173d3bSMartin Habets #define FRF_AB_GPIO9_IN_WIDTH 1 347*6e173d3bSMartin Habets #define FRF_AB_GPIO8_IN_LBN 40 348*6e173d3bSMartin Habets #define FRF_AB_GPIO8_IN_WIDTH 1 349*6e173d3bSMartin Habets #define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 350*6e173d3bSMartin Habets #define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 351*6e173d3bSMartin Habets #define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 352*6e173d3bSMartin Habets #define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 353*6e173d3bSMartin Habets #define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 354*6e173d3bSMartin Habets #define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 355*6e173d3bSMartin Habets #define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 356*6e173d3bSMartin Habets #define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 357*6e173d3bSMartin Habets #define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 358*6e173d3bSMartin Habets #define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 359*6e173d3bSMartin Habets #define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 360*6e173d3bSMartin Habets #define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 361*6e173d3bSMartin Habets #define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 362*6e173d3bSMartin Habets #define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 363*6e173d3bSMartin Habets #define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 364*6e173d3bSMartin Habets #define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 365*6e173d3bSMartin Habets #define FRF_AB_CLK156_OUT_EN_LBN 31 366*6e173d3bSMartin Habets #define FRF_AB_CLK156_OUT_EN_WIDTH 1 367*6e173d3bSMartin Habets #define FRF_AB_USE_NIC_CLK_LBN 30 368*6e173d3bSMartin Habets #define FRF_AB_USE_NIC_CLK_WIDTH 1 369*6e173d3bSMartin Habets #define FRF_AB_GPIO5_OEN_LBN 29 370*6e173d3bSMartin Habets #define FRF_AB_GPIO5_OEN_WIDTH 1 371*6e173d3bSMartin Habets #define FRF_AB_GPIO4_OEN_LBN 28 372*6e173d3bSMartin Habets #define FRF_AB_GPIO4_OEN_WIDTH 1 373*6e173d3bSMartin Habets #define FRF_AB_GPIO3_OEN_LBN 27 374*6e173d3bSMartin Habets #define FRF_AB_GPIO3_OEN_WIDTH 1 375*6e173d3bSMartin Habets #define FRF_AB_GPIO2_OEN_LBN 26 376*6e173d3bSMartin Habets #define FRF_AB_GPIO2_OEN_WIDTH 1 377*6e173d3bSMartin Habets #define FRF_AB_GPIO1_OEN_LBN 25 378*6e173d3bSMartin Habets #define FRF_AB_GPIO1_OEN_WIDTH 1 379*6e173d3bSMartin Habets #define FRF_AB_GPIO0_OEN_LBN 24 380*6e173d3bSMartin Habets #define FRF_AB_GPIO0_OEN_WIDTH 1 381*6e173d3bSMartin Habets #define FRF_AB_GPIO7_OUT_LBN 23 382*6e173d3bSMartin Habets #define FRF_AB_GPIO7_OUT_WIDTH 1 383*6e173d3bSMartin Habets #define FRF_AB_GPIO6_OUT_LBN 22 384*6e173d3bSMartin Habets #define FRF_AB_GPIO6_OUT_WIDTH 1 385*6e173d3bSMartin Habets #define FRF_AB_GPIO5_OUT_LBN 21 386*6e173d3bSMartin Habets #define FRF_AB_GPIO5_OUT_WIDTH 1 387*6e173d3bSMartin Habets #define FRF_AB_GPIO4_OUT_LBN 20 388*6e173d3bSMartin Habets #define FRF_AB_GPIO4_OUT_WIDTH 1 389*6e173d3bSMartin Habets #define FRF_AB_GPIO3_OUT_LBN 19 390*6e173d3bSMartin Habets #define FRF_AB_GPIO3_OUT_WIDTH 1 391*6e173d3bSMartin Habets #define FRF_AB_GPIO2_OUT_LBN 18 392*6e173d3bSMartin Habets #define FRF_AB_GPIO2_OUT_WIDTH 1 393*6e173d3bSMartin Habets #define FRF_AB_GPIO1_OUT_LBN 17 394*6e173d3bSMartin Habets #define FRF_AB_GPIO1_OUT_WIDTH 1 395*6e173d3bSMartin Habets #define FRF_AB_GPIO0_OUT_LBN 16 396*6e173d3bSMartin Habets #define FRF_AB_GPIO0_OUT_WIDTH 1 397*6e173d3bSMartin Habets #define FRF_AB_GPIO7_IN_LBN 15 398*6e173d3bSMartin Habets #define FRF_AB_GPIO7_IN_WIDTH 1 399*6e173d3bSMartin Habets #define FRF_AB_GPIO6_IN_LBN 14 400*6e173d3bSMartin Habets #define FRF_AB_GPIO6_IN_WIDTH 1 401*6e173d3bSMartin Habets #define FRF_AB_GPIO5_IN_LBN 13 402*6e173d3bSMartin Habets #define FRF_AB_GPIO5_IN_WIDTH 1 403*6e173d3bSMartin Habets #define FRF_AB_GPIO4_IN_LBN 12 404*6e173d3bSMartin Habets #define FRF_AB_GPIO4_IN_WIDTH 1 405*6e173d3bSMartin Habets #define FRF_AB_GPIO3_IN_LBN 11 406*6e173d3bSMartin Habets #define FRF_AB_GPIO3_IN_WIDTH 1 407*6e173d3bSMartin Habets #define FRF_AB_GPIO2_IN_LBN 10 408*6e173d3bSMartin Habets #define FRF_AB_GPIO2_IN_WIDTH 1 409*6e173d3bSMartin Habets #define FRF_AB_GPIO1_IN_LBN 9 410*6e173d3bSMartin Habets #define FRF_AB_GPIO1_IN_WIDTH 1 411*6e173d3bSMartin Habets #define FRF_AB_GPIO0_IN_LBN 8 412*6e173d3bSMartin Habets #define FRF_AB_GPIO0_IN_WIDTH 1 413*6e173d3bSMartin Habets #define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7 414*6e173d3bSMartin Habets #define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1 415*6e173d3bSMartin Habets #define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6 416*6e173d3bSMartin Habets #define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1 417*6e173d3bSMartin Habets #define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 418*6e173d3bSMartin Habets #define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 419*6e173d3bSMartin Habets #define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 420*6e173d3bSMartin Habets #define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 421*6e173d3bSMartin Habets #define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 422*6e173d3bSMartin Habets #define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 423*6e173d3bSMartin Habets #define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 424*6e173d3bSMartin Habets #define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 425*6e173d3bSMartin Habets #define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 426*6e173d3bSMartin Habets #define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 427*6e173d3bSMartin Habets #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 428*6e173d3bSMartin Habets #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 429*6e173d3bSMartin Habets 430*6e173d3bSMartin Habets /* GLB_CTL_REG: Global control register */ 431*6e173d3bSMartin Habets #define FR_AB_GLB_CTL 0x00000220 432*6e173d3bSMartin Habets #define FRF_AB_EXT_PHY_RST_CTL_LBN 63 433*6e173d3bSMartin Habets #define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 434*6e173d3bSMartin Habets #define FRF_AB_XAUI_SD_RST_CTL_LBN 62 435*6e173d3bSMartin Habets #define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 436*6e173d3bSMartin Habets #define FRF_AB_PCIE_SD_RST_CTL_LBN 61 437*6e173d3bSMartin Habets #define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 438*6e173d3bSMartin Habets #define FRF_AA_PCIX_RST_CTL_LBN 60 439*6e173d3bSMartin Habets #define FRF_AA_PCIX_RST_CTL_WIDTH 1 440*6e173d3bSMartin Habets #define FRF_BB_BIU_RST_CTL_LBN 60 441*6e173d3bSMartin Habets #define FRF_BB_BIU_RST_CTL_WIDTH 1 442*6e173d3bSMartin Habets #define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 443*6e173d3bSMartin Habets #define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 444*6e173d3bSMartin Habets #define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 445*6e173d3bSMartin Habets #define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 446*6e173d3bSMartin Habets #define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 447*6e173d3bSMartin Habets #define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 448*6e173d3bSMartin Habets #define FRF_AB_XGRX_RST_CTL_LBN 56 449*6e173d3bSMartin Habets #define FRF_AB_XGRX_RST_CTL_WIDTH 1 450*6e173d3bSMartin Habets #define FRF_AB_XGTX_RST_CTL_LBN 55 451*6e173d3bSMartin Habets #define FRF_AB_XGTX_RST_CTL_WIDTH 1 452*6e173d3bSMartin Habets #define FRF_AB_EM_RST_CTL_LBN 54 453*6e173d3bSMartin Habets #define FRF_AB_EM_RST_CTL_WIDTH 1 454*6e173d3bSMartin Habets #define FRF_AB_EV_RST_CTL_LBN 53 455*6e173d3bSMartin Habets #define FRF_AB_EV_RST_CTL_WIDTH 1 456*6e173d3bSMartin Habets #define FRF_AB_SR_RST_CTL_LBN 52 457*6e173d3bSMartin Habets #define FRF_AB_SR_RST_CTL_WIDTH 1 458*6e173d3bSMartin Habets #define FRF_AB_RX_RST_CTL_LBN 51 459*6e173d3bSMartin Habets #define FRF_AB_RX_RST_CTL_WIDTH 1 460*6e173d3bSMartin Habets #define FRF_AB_TX_RST_CTL_LBN 50 461*6e173d3bSMartin Habets #define FRF_AB_TX_RST_CTL_WIDTH 1 462*6e173d3bSMartin Habets #define FRF_AB_EE_RST_CTL_LBN 49 463*6e173d3bSMartin Habets #define FRF_AB_EE_RST_CTL_WIDTH 1 464*6e173d3bSMartin Habets #define FRF_AB_CS_RST_CTL_LBN 48 465*6e173d3bSMartin Habets #define FRF_AB_CS_RST_CTL_WIDTH 1 466*6e173d3bSMartin Habets #define FRF_AB_HOT_RST_CTL_LBN 40 467*6e173d3bSMartin Habets #define FRF_AB_HOT_RST_CTL_WIDTH 2 468*6e173d3bSMartin Habets #define FRF_AB_RST_EXT_PHY_LBN 31 469*6e173d3bSMartin Habets #define FRF_AB_RST_EXT_PHY_WIDTH 1 470*6e173d3bSMartin Habets #define FRF_AB_RST_XAUI_SD_LBN 30 471*6e173d3bSMartin Habets #define FRF_AB_RST_XAUI_SD_WIDTH 1 472*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_SD_LBN 29 473*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_SD_WIDTH 1 474*6e173d3bSMartin Habets #define FRF_AA_RST_PCIX_LBN 28 475*6e173d3bSMartin Habets #define FRF_AA_RST_PCIX_WIDTH 1 476*6e173d3bSMartin Habets #define FRF_BB_RST_BIU_LBN 28 477*6e173d3bSMartin Habets #define FRF_BB_RST_BIU_WIDTH 1 478*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_STKY_LBN 27 479*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_STKY_WIDTH 1 480*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_NSTKY_LBN 26 481*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 482*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_CORE_LBN 25 483*6e173d3bSMartin Habets #define FRF_AB_RST_PCIE_CORE_WIDTH 1 484*6e173d3bSMartin Habets #define FRF_AB_RST_XGRX_LBN 24 485*6e173d3bSMartin Habets #define FRF_AB_RST_XGRX_WIDTH 1 486*6e173d3bSMartin Habets #define FRF_AB_RST_XGTX_LBN 23 487*6e173d3bSMartin Habets #define FRF_AB_RST_XGTX_WIDTH 1 488*6e173d3bSMartin Habets #define FRF_AB_RST_EM_LBN 22 489*6e173d3bSMartin Habets #define FRF_AB_RST_EM_WIDTH 1 490*6e173d3bSMartin Habets #define FRF_AB_RST_EV_LBN 21 491*6e173d3bSMartin Habets #define FRF_AB_RST_EV_WIDTH 1 492*6e173d3bSMartin Habets #define FRF_AB_RST_SR_LBN 20 493*6e173d3bSMartin Habets #define FRF_AB_RST_SR_WIDTH 1 494*6e173d3bSMartin Habets #define FRF_AB_RST_RX_LBN 19 495*6e173d3bSMartin Habets #define FRF_AB_RST_RX_WIDTH 1 496*6e173d3bSMartin Habets #define FRF_AB_RST_TX_LBN 18 497*6e173d3bSMartin Habets #define FRF_AB_RST_TX_WIDTH 1 498*6e173d3bSMartin Habets #define FRF_AB_RST_SF_LBN 17 499*6e173d3bSMartin Habets #define FRF_AB_RST_SF_WIDTH 1 500*6e173d3bSMartin Habets #define FRF_AB_RST_CS_LBN 16 501*6e173d3bSMartin Habets #define FRF_AB_RST_CS_WIDTH 1 502*6e173d3bSMartin Habets #define FRF_AB_INT_RST_DUR_LBN 4 503*6e173d3bSMartin Habets #define FRF_AB_INT_RST_DUR_WIDTH 3 504*6e173d3bSMartin Habets #define FRF_AB_EXT_PHY_RST_DUR_LBN 1 505*6e173d3bSMartin Habets #define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 506*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_10240US 7 507*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_5120US 6 508*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_2560US 5 509*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_1280US 4 510*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_640US 3 511*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_320US 2 512*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_160US 1 513*6e173d3bSMartin Habets #define FFE_AB_EXT_PHY_RST_DUR_80US 0 514*6e173d3bSMartin Habets #define FRF_AB_SWRST_LBN 0 515*6e173d3bSMartin Habets #define FRF_AB_SWRST_WIDTH 1 516*6e173d3bSMartin Habets 517*6e173d3bSMartin Habets /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */ 518*6e173d3bSMartin Habets #define FR_AZ_FATAL_INTR_KER 0x00000230 519*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 520*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 521*6e173d3bSMartin Habets #define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 522*6e173d3bSMartin Habets #define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 523*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 524*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 525*6e173d3bSMartin Habets #define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 526*6e173d3bSMartin Habets #define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 527*6e173d3bSMartin Habets #define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 528*6e173d3bSMartin Habets #define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 529*6e173d3bSMartin Habets #define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 530*6e173d3bSMartin Habets #define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 531*6e173d3bSMartin Habets #define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 532*6e173d3bSMartin Habets #define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 533*6e173d3bSMartin Habets #define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 534*6e173d3bSMartin Habets #define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 535*6e173d3bSMartin Habets #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 536*6e173d3bSMartin Habets #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 537*6e173d3bSMartin Habets #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 538*6e173d3bSMartin Habets #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 539*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 540*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 541*6e173d3bSMartin Habets #define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 542*6e173d3bSMartin Habets #define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 543*6e173d3bSMartin Habets #define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 544*6e173d3bSMartin Habets #define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 545*6e173d3bSMartin Habets #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 546*6e173d3bSMartin Habets #define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 547*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 548*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 549*6e173d3bSMartin Habets #define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 550*6e173d3bSMartin Habets #define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 551*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_KER_LBN 11 552*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 553*6e173d3bSMartin Habets #define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 554*6e173d3bSMartin Habets #define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 555*6e173d3bSMartin Habets #define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 556*6e173d3bSMartin Habets #define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 557*6e173d3bSMartin Habets #define FRF_AZ_MEM_PERR_INT_KER_LBN 8 558*6e173d3bSMartin Habets #define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 559*6e173d3bSMartin Habets #define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 560*6e173d3bSMartin Habets #define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 561*6e173d3bSMartin Habets #define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 562*6e173d3bSMartin Habets #define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 563*6e173d3bSMartin Habets #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 564*6e173d3bSMartin Habets #define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 565*6e173d3bSMartin Habets #define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 566*6e173d3bSMartin Habets #define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 567*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 568*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 569*6e173d3bSMartin Habets #define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 570*6e173d3bSMartin Habets #define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 571*6e173d3bSMartin Habets #define FRF_AZ_ILL_ADR_INT_KER_LBN 1 572*6e173d3bSMartin Habets #define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 573*6e173d3bSMartin Habets #define FRF_AZ_SRM_PERR_INT_KER_LBN 0 574*6e173d3bSMartin Habets #define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 575*6e173d3bSMartin Habets 576*6e173d3bSMartin Habets /* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */ 577*6e173d3bSMartin Habets #define FR_BZ_FATAL_INTR_CHAR 0x00000240 578*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 579*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 580*6e173d3bSMartin Habets #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43 581*6e173d3bSMartin Habets #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 582*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 583*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 584*6e173d3bSMartin Habets #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42 585*6e173d3bSMartin Habets #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 586*6e173d3bSMartin Habets #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41 587*6e173d3bSMartin Habets #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 588*6e173d3bSMartin Habets #define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40 589*6e173d3bSMartin Habets #define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 590*6e173d3bSMartin Habets #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39 591*6e173d3bSMartin Habets #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 592*6e173d3bSMartin Habets #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38 593*6e173d3bSMartin Habets #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 594*6e173d3bSMartin Habets #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 595*6e173d3bSMartin Habets #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 596*6e173d3bSMartin Habets #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 597*6e173d3bSMartin Habets #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 598*6e173d3bSMartin Habets #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35 599*6e173d3bSMartin Habets #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 600*6e173d3bSMartin Habets #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34 601*6e173d3bSMartin Habets #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 602*6e173d3bSMartin Habets #define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33 603*6e173d3bSMartin Habets #define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 604*6e173d3bSMartin Habets #define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32 605*6e173d3bSMartin Habets #define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 606*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 607*6e173d3bSMartin Habets #define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 608*6e173d3bSMartin Habets #define FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11 609*6e173d3bSMartin Habets #define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1 610*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 611*6e173d3bSMartin Habets #define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 612*6e173d3bSMartin Habets #define FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10 613*6e173d3bSMartin Habets #define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1 614*6e173d3bSMartin Habets #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9 615*6e173d3bSMartin Habets #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 616*6e173d3bSMartin Habets #define FRF_BZ_MEM_PERR_INT_CHAR_LBN 8 617*6e173d3bSMartin Habets #define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1 618*6e173d3bSMartin Habets #define FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7 619*6e173d3bSMartin Habets #define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1 620*6e173d3bSMartin Habets #define FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6 621*6e173d3bSMartin Habets #define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1 622*6e173d3bSMartin Habets #define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5 623*6e173d3bSMartin Habets #define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 624*6e173d3bSMartin Habets #define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4 625*6e173d3bSMartin Habets #define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 626*6e173d3bSMartin Habets #define FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3 627*6e173d3bSMartin Habets #define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1 628*6e173d3bSMartin Habets #define FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2 629*6e173d3bSMartin Habets #define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1 630*6e173d3bSMartin Habets #define FRF_BZ_ILL_ADR_INT_CHAR_LBN 1 631*6e173d3bSMartin Habets #define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1 632*6e173d3bSMartin Habets #define FRF_BZ_SRM_PERR_INT_CHAR_LBN 0 633*6e173d3bSMartin Habets #define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1 634*6e173d3bSMartin Habets 635*6e173d3bSMartin Habets /* DP_CTRL_REG: Datapath control register */ 636*6e173d3bSMartin Habets #define FR_BZ_DP_CTRL 0x00000250 637*6e173d3bSMartin Habets #define FRF_BZ_FLS_EVQ_ID_LBN 0 638*6e173d3bSMartin Habets #define FRF_BZ_FLS_EVQ_ID_WIDTH 12 639*6e173d3bSMartin Habets 640*6e173d3bSMartin Habets /* MEM_STAT_REG: Memory status register */ 641*6e173d3bSMartin Habets #define FR_AZ_MEM_STAT 0x00000260 642*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_VEC_LBN 53 643*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_VEC_WIDTH 38 644*6e173d3bSMartin Habets #define FRF_AB_MBIST_CORR_LBN 38 645*6e173d3bSMartin Habets #define FRF_AB_MBIST_CORR_WIDTH 15 646*6e173d3bSMartin Habets #define FRF_AB_MBIST_ERR_LBN 0 647*6e173d3bSMartin Habets #define FRF_AB_MBIST_ERR_WIDTH 40 648*6e173d3bSMartin Habets #define FRF_CZ_MEM_PERR_VEC_LBN 0 649*6e173d3bSMartin Habets #define FRF_CZ_MEM_PERR_VEC_WIDTH 35 650*6e173d3bSMartin Habets 651*6e173d3bSMartin Habets /* CS_DEBUG_REG: Debug register */ 652*6e173d3bSMartin Habets #define FR_AZ_CS_DEBUG 0x00000270 653*6e173d3bSMartin Habets #define FRF_AB_GLB_DEBUG2_SEL_LBN 50 654*6e173d3bSMartin Habets #define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 655*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL2_LBN 47 656*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 657*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL1_LBN 44 658*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 659*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL0_LBN 41 660*6e173d3bSMartin Habets #define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 661*6e173d3bSMartin Habets #define FRF_CZ_CS_PORT_NUM_LBN 40 662*6e173d3bSMartin Habets #define FRF_CZ_CS_PORT_NUM_WIDTH 2 663*6e173d3bSMartin Habets #define FRF_AB_MISC_DEBUG_ADDR_LBN 36 664*6e173d3bSMartin Habets #define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 665*6e173d3bSMartin Habets #define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 666*6e173d3bSMartin Habets #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 667*6e173d3bSMartin Habets #define FRF_CZ_CS_PORT_FPE_LBN 1 668*6e173d3bSMartin Habets #define FRF_CZ_CS_PORT_FPE_WIDTH 35 669*6e173d3bSMartin Habets #define FRF_AB_EM_DEBUG_ADDR_LBN 26 670*6e173d3bSMartin Habets #define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 671*6e173d3bSMartin Habets #define FRF_AB_SR_DEBUG_ADDR_LBN 21 672*6e173d3bSMartin Habets #define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 673*6e173d3bSMartin Habets #define FRF_AB_EV_DEBUG_ADDR_LBN 16 674*6e173d3bSMartin Habets #define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 675*6e173d3bSMartin Habets #define FRF_AB_RX_DEBUG_ADDR_LBN 11 676*6e173d3bSMartin Habets #define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 677*6e173d3bSMartin Habets #define FRF_AB_TX_DEBUG_ADDR_LBN 6 678*6e173d3bSMartin Habets #define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 679*6e173d3bSMartin Habets #define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 680*6e173d3bSMartin Habets #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 681*6e173d3bSMartin Habets #define FRF_AZ_CS_DEBUG_EN_LBN 0 682*6e173d3bSMartin Habets #define FRF_AZ_CS_DEBUG_EN_WIDTH 1 683*6e173d3bSMartin Habets 684*6e173d3bSMartin Habets /* DRIVER_REG: Driver scratch register [0-7] */ 685*6e173d3bSMartin Habets #define FR_AZ_DRIVER 0x00000280 686*6e173d3bSMartin Habets #define FR_AZ_DRIVER_STEP 16 687*6e173d3bSMartin Habets #define FR_AZ_DRIVER_ROWS 8 688*6e173d3bSMartin Habets #define FRF_AZ_DRIVER_DW0_LBN 0 689*6e173d3bSMartin Habets #define FRF_AZ_DRIVER_DW0_WIDTH 32 690*6e173d3bSMartin Habets 691*6e173d3bSMartin Habets /* ALTERA_BUILD_REG: Altera build register */ 692*6e173d3bSMartin Habets #define FR_AZ_ALTERA_BUILD 0x00000300 693*6e173d3bSMartin Habets #define FRF_AZ_ALTERA_BUILD_VER_LBN 0 694*6e173d3bSMartin Habets #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 695*6e173d3bSMartin Habets 696*6e173d3bSMartin Habets /* CSR_SPARE_REG: Spare register */ 697*6e173d3bSMartin Habets #define FR_AZ_CSR_SPARE 0x00000310 698*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_EN_LBN 64 699*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_EN_WIDTH 38 700*6e173d3bSMartin Habets #define FRF_CZ_MEM_PERR_EN_LBN 64 701*6e173d3bSMartin Habets #define FRF_CZ_MEM_PERR_EN_WIDTH 35 702*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72 703*6e173d3bSMartin Habets #define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2 704*6e173d3bSMartin Habets #define FRF_AZ_CSR_SPARE_BITS_LBN 0 705*6e173d3bSMartin Habets #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 706*6e173d3bSMartin Habets 707*6e173d3bSMartin Habets /* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */ 708*6e173d3bSMartin Habets #define FR_AB_PCIE_SD_CTL0123 0x00000320 709*6e173d3bSMartin Habets #define FRF_AB_PCIE_TESTSIG_H_LBN 96 710*6e173d3bSMartin Habets #define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 711*6e173d3bSMartin Habets #define FRF_AB_PCIE_TESTSIG_L_LBN 64 712*6e173d3bSMartin Habets #define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 713*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSET_LBN 56 714*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSET_WIDTH 8 715*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSETEN_H_LBN 55 716*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 717*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSETEN_L_LBN 54 718*6e173d3bSMartin Habets #define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 719*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIVMODE_H_LBN 53 720*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 721*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIVMODE_L_LBN 52 722*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 723*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARRESET_H_LBN 51 724*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARRESET_H_WIDTH 1 725*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARRESET_L_LBN 50 726*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARRESET_L_WIDTH 1 727*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 728*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 729*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 730*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 731*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBK_LBN 40 732*6e173d3bSMartin Habets #define FRF_AB_PCIE_LPBK_WIDTH 8 733*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARLPBK_LBN 32 734*6e173d3bSMartin Habets #define FRF_AB_PCIE_PARLPBK_WIDTH 8 735*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 736*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 737*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 738*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 739*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 740*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 741*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 742*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 743*6e173d3bSMartin Habets #define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 744*6e173d3bSMartin Habets #define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 745*6e173d3bSMartin Habets #define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 746*6e173d3bSMartin Habets #define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 747*6e173d3bSMartin Habets #define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 748*6e173d3bSMartin Habets #define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 749*6e173d3bSMartin Habets #define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 750*6e173d3bSMartin Habets #define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 751*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXEQCTL_H_LBN 18 752*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 753*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXEQCTL_L_LBN 16 754*6e173d3bSMartin Habets #define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 755*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 756*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXEQCTL_OFF 2 757*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXEQCTL_MIN 1 758*6e173d3bSMartin Habets #define FFE_AB_PCIE_RXEQCTL_MAX 0 759*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIDRV_LBN 8 760*6e173d3bSMartin Habets #define FRF_AB_PCIE_HIDRV_WIDTH 8 761*6e173d3bSMartin Habets #define FRF_AB_PCIE_LODRV_LBN 0 762*6e173d3bSMartin Habets #define FRF_AB_PCIE_LODRV_WIDTH 8 763*6e173d3bSMartin Habets 764*6e173d3bSMartin Habets /* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */ 765*6e173d3bSMartin Habets #define FR_AB_PCIE_SD_CTL45 0x00000330 766*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX7_LBN 60 767*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX7_WIDTH 4 768*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX6_LBN 56 769*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX6_WIDTH 4 770*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX5_LBN 52 771*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX5_WIDTH 4 772*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX4_LBN 48 773*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX4_WIDTH 4 774*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX3_LBN 44 775*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX3_WIDTH 4 776*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX2_LBN 40 777*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX2_WIDTH 4 778*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX1_LBN 36 779*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX1_WIDTH 4 780*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX0_LBN 32 781*6e173d3bSMartin Habets #define FRF_AB_PCIE_DTX0_WIDTH 4 782*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ7_LBN 28 783*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ7_WIDTH 4 784*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ6_LBN 24 785*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ6_WIDTH 4 786*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ5_LBN 20 787*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ5_WIDTH 4 788*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ4_LBN 16 789*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ4_WIDTH 4 790*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ3_LBN 12 791*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ3_WIDTH 4 792*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ2_LBN 8 793*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ2_WIDTH 4 794*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ1_LBN 4 795*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ1_WIDTH 4 796*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ0_LBN 0 797*6e173d3bSMartin Habets #define FRF_AB_PCIE_DEQ0_WIDTH 4 798*6e173d3bSMartin Habets 799*6e173d3bSMartin Habets /* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */ 800*6e173d3bSMartin Habets #define FR_AB_PCIE_PCS_CTL_STAT 0x00000340 801*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 802*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 803*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 804*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 805*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERR_LBN 40 806*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERR_WIDTH 8 807*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRH0_LBN 32 808*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 809*6e173d3bSMartin Habets #define FRF_AB_PCIE_FASTINIT_H_LBN 15 810*6e173d3bSMartin Habets #define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 811*6e173d3bSMartin Habets #define FRF_AB_PCIE_FASTINIT_L_LBN 14 812*6e173d3bSMartin Habets #define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 813*6e173d3bSMartin Habets #define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 814*6e173d3bSMartin Habets #define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 815*6e173d3bSMartin Habets #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 816*6e173d3bSMartin Habets #define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 817*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 818*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 819*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 820*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 821*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 822*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 823*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 824*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 825*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSEL_LBN 0 826*6e173d3bSMartin Habets #define FRF_AB_PCIE_PRBSSEL_WIDTH 8 827*6e173d3bSMartin Habets 828*6e173d3bSMartin Habets /* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */ 829*6e173d3bSMartin Habets #define FR_BB_DEBUG_DATA_OUT 0x00000350 830*6e173d3bSMartin Habets #define FRF_BB_DEBUG2_PORT_LBN 25 831*6e173d3bSMartin Habets #define FRF_BB_DEBUG2_PORT_WIDTH 15 832*6e173d3bSMartin Habets #define FRF_BB_DEBUG1_PORT_LBN 0 833*6e173d3bSMartin Habets #define FRF_BB_DEBUG1_PORT_WIDTH 25 834*6e173d3bSMartin Habets 835*6e173d3bSMartin Habets /* EVQ_RPTR_REGP0: Event queue read pointer register */ 836*6e173d3bSMartin Habets #define FR_BZ_EVQ_RPTR_P0 0x00000400 837*6e173d3bSMartin Habets #define FR_BZ_EVQ_RPTR_P0_STEP 8192 838*6e173d3bSMartin Habets #define FR_BZ_EVQ_RPTR_P0_ROWS 1024 839*6e173d3bSMartin Habets /* EVQ_RPTR_REG_KER: Event queue read pointer register */ 840*6e173d3bSMartin Habets #define FR_AA_EVQ_RPTR_KER 0x00011b00 841*6e173d3bSMartin Habets #define FR_AA_EVQ_RPTR_KER_STEP 4 842*6e173d3bSMartin Habets #define FR_AA_EVQ_RPTR_KER_ROWS 4 843*6e173d3bSMartin Habets /* EVQ_RPTR_REG: Event queue read pointer register */ 844*6e173d3bSMartin Habets #define FR_BZ_EVQ_RPTR 0x00fa0000 845*6e173d3bSMartin Habets #define FR_BZ_EVQ_RPTR_STEP 16 846*6e173d3bSMartin Habets #define FR_BB_EVQ_RPTR_ROWS 4096 847*6e173d3bSMartin Habets #define FR_CZ_EVQ_RPTR_ROWS 1024 848*6e173d3bSMartin Habets /* EVQ_RPTR_REGP123: Event queue read pointer register */ 849*6e173d3bSMartin Habets #define FR_BB_EVQ_RPTR_P123 0x01000400 850*6e173d3bSMartin Habets #define FR_BB_EVQ_RPTR_P123_STEP 8192 851*6e173d3bSMartin Habets #define FR_BB_EVQ_RPTR_P123_ROWS 3072 852*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RPTR_VLD_LBN 15 853*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 854*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RPTR_LBN 0 855*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RPTR_WIDTH 15 856*6e173d3bSMartin Habets 857*6e173d3bSMartin Habets /* TIMER_COMMAND_REGP0: Timer Command Registers */ 858*6e173d3bSMartin Habets #define FR_BZ_TIMER_COMMAND_P0 0x00000420 859*6e173d3bSMartin Habets #define FR_BZ_TIMER_COMMAND_P0_STEP 8192 860*6e173d3bSMartin Habets #define FR_BZ_TIMER_COMMAND_P0_ROWS 1024 861*6e173d3bSMartin Habets /* TIMER_COMMAND_REG_KER: Timer Command Registers */ 862*6e173d3bSMartin Habets #define FR_AA_TIMER_COMMAND_KER 0x00000420 863*6e173d3bSMartin Habets #define FR_AA_TIMER_COMMAND_KER_STEP 8192 864*6e173d3bSMartin Habets #define FR_AA_TIMER_COMMAND_KER_ROWS 4 865*6e173d3bSMartin Habets /* TIMER_COMMAND_REGP123: Timer Command Registers */ 866*6e173d3bSMartin Habets #define FR_BB_TIMER_COMMAND_P123 0x01000420 867*6e173d3bSMartin Habets #define FR_BB_TIMER_COMMAND_P123_STEP 8192 868*6e173d3bSMartin Habets #define FR_BB_TIMER_COMMAND_P123_ROWS 3072 869*6e173d3bSMartin Habets #define FRF_CZ_TC_TIMER_MODE_LBN 14 870*6e173d3bSMartin Habets #define FRF_CZ_TC_TIMER_MODE_WIDTH 2 871*6e173d3bSMartin Habets #define FRF_AB_TC_TIMER_MODE_LBN 12 872*6e173d3bSMartin Habets #define FRF_AB_TC_TIMER_MODE_WIDTH 2 873*6e173d3bSMartin Habets #define FRF_CZ_TC_TIMER_VAL_LBN 0 874*6e173d3bSMartin Habets #define FRF_CZ_TC_TIMER_VAL_WIDTH 14 875*6e173d3bSMartin Habets #define FRF_AB_TC_TIMER_VAL_LBN 0 876*6e173d3bSMartin Habets #define FRF_AB_TC_TIMER_VAL_WIDTH 12 877*6e173d3bSMartin Habets 878*6e173d3bSMartin Habets /* DRV_EV_REG: Driver generated event register */ 879*6e173d3bSMartin Habets #define FR_AZ_DRV_EV 0x00000440 880*6e173d3bSMartin Habets #define FRF_AZ_DRV_EV_QID_LBN 64 881*6e173d3bSMartin Habets #define FRF_AZ_DRV_EV_QID_WIDTH 12 882*6e173d3bSMartin Habets #define FRF_AZ_DRV_EV_DATA_LBN 0 883*6e173d3bSMartin Habets #define FRF_AZ_DRV_EV_DATA_WIDTH 64 884*6e173d3bSMartin Habets 885*6e173d3bSMartin Habets /* EVQ_CTL_REG: Event queue control register */ 886*6e173d3bSMartin Habets #define FR_AZ_EVQ_CTL 0x00000450 887*6e173d3bSMartin Habets #define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 888*6e173d3bSMartin Habets #define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 889*6e173d3bSMartin Habets #define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 890*6e173d3bSMartin Habets #define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 891*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 892*6e173d3bSMartin Habets #define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 893*6e173d3bSMartin Habets #define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 894*6e173d3bSMartin Habets #define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 895*6e173d3bSMartin Habets #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 896*6e173d3bSMartin Habets #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 897*6e173d3bSMartin Habets 898*6e173d3bSMartin Habets /* EVQ_CNT1_REG: Event counter 1 register */ 899*6e173d3bSMartin Habets #define FR_AZ_EVQ_CNT1 0x00000460 900*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 901*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 902*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 903*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 904*6e173d3bSMartin Habets #define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 905*6e173d3bSMartin Habets #define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 906*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 907*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 908*6e173d3bSMartin Habets #define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 909*6e173d3bSMartin Habets #define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 910*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 911*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 912*6e173d3bSMartin Habets #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 913*6e173d3bSMartin Habets #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 914*6e173d3bSMartin Habets 915*6e173d3bSMartin Habets /* EVQ_CNT2_REG: Event counter 2 register */ 916*6e173d3bSMartin Habets #define FR_AZ_EVQ_CNT2 0x00000470 917*6e173d3bSMartin Habets #define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 918*6e173d3bSMartin Habets #define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 919*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 920*6e173d3bSMartin Habets #define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 921*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RDY_CNT_LBN 80 922*6e173d3bSMartin Habets #define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 923*6e173d3bSMartin Habets #define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 924*6e173d3bSMartin Habets #define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 925*6e173d3bSMartin Habets #define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 926*6e173d3bSMartin Habets #define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 927*6e173d3bSMartin Habets #define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 928*6e173d3bSMartin Habets #define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 929*6e173d3bSMartin Habets #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 930*6e173d3bSMartin Habets #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 931*6e173d3bSMartin Habets 932*6e173d3bSMartin Habets /* USR_EV_REG: Event mailbox register */ 933*6e173d3bSMartin Habets #define FR_CZ_USR_EV 0x00000540 934*6e173d3bSMartin Habets #define FR_CZ_USR_EV_STEP 8192 935*6e173d3bSMartin Habets #define FR_CZ_USR_EV_ROWS 1024 936*6e173d3bSMartin Habets #define FRF_CZ_USR_EV_DATA_LBN 0 937*6e173d3bSMartin Habets #define FRF_CZ_USR_EV_DATA_WIDTH 32 938*6e173d3bSMartin Habets 939*6e173d3bSMartin Habets /* BUF_TBL_CFG_REG: Buffer table configuration register */ 940*6e173d3bSMartin Habets #define FR_AZ_BUF_TBL_CFG 0x00000600 941*6e173d3bSMartin Habets #define FRF_AZ_BUF_TBL_MODE_LBN 3 942*6e173d3bSMartin Habets #define FRF_AZ_BUF_TBL_MODE_WIDTH 1 943*6e173d3bSMartin Habets 944*6e173d3bSMartin Habets /* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */ 945*6e173d3bSMartin Habets #define FR_AZ_SRM_RX_DC_CFG 0x00000610 946*6e173d3bSMartin Habets #define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 947*6e173d3bSMartin Habets #define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 948*6e173d3bSMartin Habets #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 949*6e173d3bSMartin Habets #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 950*6e173d3bSMartin Habets 951*6e173d3bSMartin Habets /* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */ 952*6e173d3bSMartin Habets #define FR_AZ_SRM_TX_DC_CFG 0x00000620 953*6e173d3bSMartin Habets #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 954*6e173d3bSMartin Habets #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 955*6e173d3bSMartin Habets 956*6e173d3bSMartin Habets /* SRM_CFG_REG: SRAM configuration register */ 957*6e173d3bSMartin Habets #define FR_AZ_SRM_CFG 0x00000630 958*6e173d3bSMartin Habets #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 959*6e173d3bSMartin Habets #define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 960*6e173d3bSMartin Habets #define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 961*6e173d3bSMartin Habets #define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 962*6e173d3bSMartin Habets #define FRF_AZ_SRM_INIT_EN_LBN 3 963*6e173d3bSMartin Habets #define FRF_AZ_SRM_INIT_EN_WIDTH 1 964*6e173d3bSMartin Habets #define FRF_AZ_SRM_NUM_BANK_LBN 2 965*6e173d3bSMartin Habets #define FRF_AZ_SRM_NUM_BANK_WIDTH 1 966*6e173d3bSMartin Habets #define FRF_AZ_SRM_BANK_SIZE_LBN 0 967*6e173d3bSMartin Habets #define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 968*6e173d3bSMartin Habets 969*6e173d3bSMartin Habets /* BUF_TBL_UPD_REG: Buffer table update register */ 970*6e173d3bSMartin Habets #define FR_AZ_BUF_TBL_UPD 0x00000650 971*6e173d3bSMartin Habets #define FRF_AZ_BUF_UPD_CMD_LBN 63 972*6e173d3bSMartin Habets #define FRF_AZ_BUF_UPD_CMD_WIDTH 1 973*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_CMD_LBN 62 974*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_CMD_WIDTH 1 975*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_END_ID_LBN 32 976*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 977*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_START_ID_LBN 0 978*6e173d3bSMartin Habets #define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 979*6e173d3bSMartin Habets 980*6e173d3bSMartin Habets /* SRM_UPD_EVQ_REG: Buffer table update register */ 981*6e173d3bSMartin Habets #define FR_AZ_SRM_UPD_EVQ 0x00000660 982*6e173d3bSMartin Habets #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 983*6e173d3bSMartin Habets #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 984*6e173d3bSMartin Habets 985*6e173d3bSMartin Habets /* SRAM_PARITY_REG: SRAM parity register. */ 986*6e173d3bSMartin Habets #define FR_AZ_SRAM_PARITY 0x00000670 987*6e173d3bSMartin Habets #define FRF_CZ_BYPASS_ECC_LBN 3 988*6e173d3bSMartin Habets #define FRF_CZ_BYPASS_ECC_WIDTH 1 989*6e173d3bSMartin Habets #define FRF_CZ_SEC_INT_LBN 2 990*6e173d3bSMartin Habets #define FRF_CZ_SEC_INT_WIDTH 1 991*6e173d3bSMartin Habets #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 992*6e173d3bSMartin Habets #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 993*6e173d3bSMartin Habets #define FRF_AB_FORCE_SRAM_PERR_LBN 0 994*6e173d3bSMartin Habets #define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 995*6e173d3bSMartin Habets #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 996*6e173d3bSMartin Habets #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 997*6e173d3bSMartin Habets 998*6e173d3bSMartin Habets /* RX_CFG_REG: Receive configuration register */ 999*6e173d3bSMartin Habets #define FR_AZ_RX_CFG 0x00000800 1000*6e173d3bSMartin Habets #define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72 1001*6e173d3bSMartin Habets #define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14 1002*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1003*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1004*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1005*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1006*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1007*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1008*6e173d3bSMartin Habets #define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1009*6e173d3bSMartin Habets #define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1010*6e173d3bSMartin Habets #define FRF_BZ_RX_TCP_SUP_LBN 48 1011*6e173d3bSMartin Habets #define FRF_BZ_RX_TCP_SUP_WIDTH 1 1012*6e173d3bSMartin Habets #define FRF_BZ_RX_INGR_EN_LBN 47 1013*6e173d3bSMartin Habets #define FRF_BZ_RX_INGR_EN_WIDTH 1 1014*6e173d3bSMartin Habets #define FRF_BZ_RX_IP_HASH_LBN 46 1015*6e173d3bSMartin Habets #define FRF_BZ_RX_IP_HASH_WIDTH 1 1016*6e173d3bSMartin Habets #define FRF_BZ_RX_HASH_ALG_LBN 45 1017*6e173d3bSMartin Habets #define FRF_BZ_RX_HASH_ALG_WIDTH 1 1018*6e173d3bSMartin Habets #define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1019*6e173d3bSMartin Habets #define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1020*6e173d3bSMartin Habets #define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1021*6e173d3bSMartin Habets #define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1022*6e173d3bSMartin Habets #define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1023*6e173d3bSMartin Habets #define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1024*6e173d3bSMartin Habets #define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1025*6e173d3bSMartin Habets #define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1026*6e173d3bSMartin Habets #define FRF_BZ_RX_OWNERR_CTL_LBN 38 1027*6e173d3bSMartin Habets #define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1028*6e173d3bSMartin Habets #define FRF_BZ_RX_XON_TX_TH_LBN 33 1029*6e173d3bSMartin Habets #define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1030*6e173d3bSMartin Habets #define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1031*6e173d3bSMartin Habets #define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1032*6e173d3bSMartin Habets #define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1033*6e173d3bSMartin Habets #define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1034*6e173d3bSMartin Habets #define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1035*6e173d3bSMartin Habets #define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1036*6e173d3bSMartin Habets #define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1037*6e173d3bSMartin Habets #define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1038*6e173d3bSMartin Habets #define FRF_AA_RX_OWNERR_CTL_LBN 30 1039*6e173d3bSMartin Habets #define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1040*6e173d3bSMartin Habets #define FRF_AA_RX_XON_TX_TH_LBN 25 1041*6e173d3bSMartin Habets #define FRF_AA_RX_XON_TX_TH_WIDTH 5 1042*6e173d3bSMartin Habets #define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1043*6e173d3bSMartin Habets #define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1044*6e173d3bSMartin Habets #define FRF_AA_RX_XOFF_TX_TH_LBN 20 1045*6e173d3bSMartin Habets #define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1046*6e173d3bSMartin Habets #define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1047*6e173d3bSMartin Habets #define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1048*6e173d3bSMartin Habets #define FRF_BZ_RX_XON_MAC_TH_LBN 10 1049*6e173d3bSMartin Habets #define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1050*6e173d3bSMartin Habets #define FRF_AA_RX_XON_MAC_TH_LBN 6 1051*6e173d3bSMartin Habets #define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1052*6e173d3bSMartin Habets #define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1053*6e173d3bSMartin Habets #define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1054*6e173d3bSMartin Habets #define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1055*6e173d3bSMartin Habets #define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1056*6e173d3bSMartin Habets #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1057*6e173d3bSMartin Habets #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1058*6e173d3bSMartin Habets 1059*6e173d3bSMartin Habets /* RX_FILTER_CTL_REG: Receive filter control registers */ 1060*6e173d3bSMartin Habets #define FR_BZ_RX_FILTER_CTL 0x00000810 1061*6e173d3bSMartin Habets #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1062*6e173d3bSMartin Habets #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1063*6e173d3bSMartin Habets #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1064*6e173d3bSMartin Habets #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1065*6e173d3bSMartin Habets #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1066*6e173d3bSMartin Habets #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1067*6e173d3bSMartin Habets #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1068*6e173d3bSMartin Habets #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1069*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1070*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1071*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1072*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1073*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1074*6e173d3bSMartin Habets #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1075*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1076*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1077*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1078*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1079*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1080*6e173d3bSMartin Habets #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1081*6e173d3bSMartin Habets #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1082*6e173d3bSMartin Habets #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1083*6e173d3bSMartin Habets #define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 32 1084*6e173d3bSMartin Habets #define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1085*6e173d3bSMartin Habets #define FRF_BZ_NUM_KER_LBN 24 1086*6e173d3bSMartin Habets #define FRF_BZ_NUM_KER_WIDTH 2 1087*6e173d3bSMartin Habets #define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 16 1088*6e173d3bSMartin Habets #define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1089*6e173d3bSMartin Habets #define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 8 1090*6e173d3bSMartin Habets #define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1091*6e173d3bSMartin Habets #define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 0 1092*6e173d3bSMartin Habets #define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1093*6e173d3bSMartin Habets 1094*6e173d3bSMartin Habets /* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */ 1095*6e173d3bSMartin Habets #define FR_AZ_RX_FLUSH_DESCQ 0x00000820 1096*6e173d3bSMartin Habets #define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1097*6e173d3bSMartin Habets #define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1098*6e173d3bSMartin Habets #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1099*6e173d3bSMartin Habets #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1100*6e173d3bSMartin Habets 1101*6e173d3bSMartin Habets /* RX_DESC_UPD_REGP0: Receive descriptor update register. */ 1102*6e173d3bSMartin Habets #define FR_BZ_RX_DESC_UPD_P0 0x00000830 1103*6e173d3bSMartin Habets #define FR_BZ_RX_DESC_UPD_P0_STEP 8192 1104*6e173d3bSMartin Habets #define FR_BZ_RX_DESC_UPD_P0_ROWS 1024 1105*6e173d3bSMartin Habets /* RX_DESC_UPD_REG_KER: Receive descriptor update register. */ 1106*6e173d3bSMartin Habets #define FR_AA_RX_DESC_UPD_KER 0x00000830 1107*6e173d3bSMartin Habets #define FR_AA_RX_DESC_UPD_KER_STEP 8192 1108*6e173d3bSMartin Habets #define FR_AA_RX_DESC_UPD_KER_ROWS 4 1109*6e173d3bSMartin Habets /* RX_DESC_UPD_REGP123: Receive descriptor update register. */ 1110*6e173d3bSMartin Habets #define FR_BB_RX_DESC_UPD_P123 0x01000830 1111*6e173d3bSMartin Habets #define FR_BB_RX_DESC_UPD_P123_STEP 8192 1112*6e173d3bSMartin Habets #define FR_BB_RX_DESC_UPD_P123_ROWS 3072 1113*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_WPTR_LBN 96 1114*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1115*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1116*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1117*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_LBN 0 1118*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_WIDTH 64 1119*6e173d3bSMartin Habets 1120*6e173d3bSMartin Habets /* RX_DC_CFG_REG: Receive descriptor cache configuration register */ 1121*6e173d3bSMartin Habets #define FR_AZ_RX_DC_CFG 0x00000840 1122*6e173d3bSMartin Habets #define FRF_AB_RX_MAX_PF_LBN 2 1123*6e173d3bSMartin Habets #define FRF_AB_RX_MAX_PF_WIDTH 2 1124*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_SIZE_LBN 0 1125*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_SIZE_WIDTH 2 1126*6e173d3bSMartin Habets #define FFE_AZ_RX_DC_SIZE_64 3 1127*6e173d3bSMartin Habets #define FFE_AZ_RX_DC_SIZE_32 2 1128*6e173d3bSMartin Habets #define FFE_AZ_RX_DC_SIZE_16 1 1129*6e173d3bSMartin Habets #define FFE_AZ_RX_DC_SIZE_8 0 1130*6e173d3bSMartin Habets 1131*6e173d3bSMartin Habets /* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */ 1132*6e173d3bSMartin Habets #define FR_AZ_RX_DC_PF_WM 0x00000850 1133*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_PF_HWM_LBN 6 1134*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1135*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_PF_LWM_LBN 0 1136*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1137*6e173d3bSMartin Habets 1138*6e173d3bSMartin Habets /* RX_RSS_TKEY_REG: RSS Toeplitz hash key */ 1139*6e173d3bSMartin Habets #define FR_BZ_RX_RSS_TKEY 0x00000860 1140*6e173d3bSMartin Habets #define FRF_BZ_RX_RSS_TKEY_HI_LBN 64 1141*6e173d3bSMartin Habets #define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64 1142*6e173d3bSMartin Habets #define FRF_BZ_RX_RSS_TKEY_LO_LBN 0 1143*6e173d3bSMartin Habets #define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64 1144*6e173d3bSMartin Habets 1145*6e173d3bSMartin Habets /* RX_NODESC_DROP_REG: Receive dropped packet counter register */ 1146*6e173d3bSMartin Habets #define FR_AZ_RX_NODESC_DROP 0x00000880 1147*6e173d3bSMartin Habets #define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0 1148*6e173d3bSMartin Habets #define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32 1149*6e173d3bSMartin Habets #define FRF_AB_RX_NODESC_DROP_CNT_LBN 0 1150*6e173d3bSMartin Habets #define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16 1151*6e173d3bSMartin Habets 1152*6e173d3bSMartin Habets /* RX_SELF_RST_REG: Receive self reset register */ 1153*6e173d3bSMartin Habets #define FR_AA_RX_SELF_RST 0x00000890 1154*6e173d3bSMartin Habets #define FRF_AA_RX_ISCSI_DIS_LBN 17 1155*6e173d3bSMartin Habets #define FRF_AA_RX_ISCSI_DIS_WIDTH 1 1156*6e173d3bSMartin Habets #define FRF_AA_RX_SW_RST_REG_LBN 16 1157*6e173d3bSMartin Habets #define FRF_AA_RX_SW_RST_REG_WIDTH 1 1158*6e173d3bSMartin Habets #define FRF_AA_RX_NODESC_WAIT_DIS_LBN 9 1159*6e173d3bSMartin Habets #define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 1 1160*6e173d3bSMartin Habets #define FRF_AA_RX_SELF_RST_EN_LBN 8 1161*6e173d3bSMartin Habets #define FRF_AA_RX_SELF_RST_EN_WIDTH 1 1162*6e173d3bSMartin Habets #define FRF_AA_RX_MAX_PF_LAT_LBN 4 1163*6e173d3bSMartin Habets #define FRF_AA_RX_MAX_PF_LAT_WIDTH 4 1164*6e173d3bSMartin Habets #define FRF_AA_RX_MAX_LU_LAT_LBN 0 1165*6e173d3bSMartin Habets #define FRF_AA_RX_MAX_LU_LAT_WIDTH 4 1166*6e173d3bSMartin Habets 1167*6e173d3bSMartin Habets /* RX_DEBUG_REG: undocumented register */ 1168*6e173d3bSMartin Habets #define FR_AZ_RX_DEBUG 0x000008a0 1169*6e173d3bSMartin Habets #define FRF_AZ_RX_DEBUG_LBN 0 1170*6e173d3bSMartin Habets #define FRF_AZ_RX_DEBUG_WIDTH 64 1171*6e173d3bSMartin Habets 1172*6e173d3bSMartin Habets /* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */ 1173*6e173d3bSMartin Habets #define FR_AZ_RX_PUSH_DROP 0x000008b0 1174*6e173d3bSMartin Habets #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1175*6e173d3bSMartin Habets #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1176*6e173d3bSMartin Habets 1177*6e173d3bSMartin Habets /* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */ 1178*6e173d3bSMartin Habets #define FR_CZ_RX_RSS_IPV6_REG1 0x000008d0 1179*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1180*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1181*6e173d3bSMartin Habets 1182*6e173d3bSMartin Habets /* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */ 1183*6e173d3bSMartin Habets #define FR_CZ_RX_RSS_IPV6_REG2 0x000008e0 1184*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1185*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1186*6e173d3bSMartin Habets 1187*6e173d3bSMartin Habets /* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */ 1188*6e173d3bSMartin Habets #define FR_CZ_RX_RSS_IPV6_REG3 0x000008f0 1189*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1190*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1191*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1192*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1193*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1194*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1195*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1196*6e173d3bSMartin Habets #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1197*6e173d3bSMartin Habets 1198*6e173d3bSMartin Habets /* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */ 1199*6e173d3bSMartin Habets #define FR_AZ_TX_FLUSH_DESCQ 0x00000a00 1200*6e173d3bSMartin Habets #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1201*6e173d3bSMartin Habets #define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1202*6e173d3bSMartin Habets #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1203*6e173d3bSMartin Habets #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1204*6e173d3bSMartin Habets 1205*6e173d3bSMartin Habets /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */ 1206*6e173d3bSMartin Habets #define FR_BZ_TX_DESC_UPD_P0 0x00000a10 1207*6e173d3bSMartin Habets #define FR_BZ_TX_DESC_UPD_P0_STEP 8192 1208*6e173d3bSMartin Habets #define FR_BZ_TX_DESC_UPD_P0_ROWS 1024 1209*6e173d3bSMartin Habets /* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */ 1210*6e173d3bSMartin Habets #define FR_AA_TX_DESC_UPD_KER 0x00000a10 1211*6e173d3bSMartin Habets #define FR_AA_TX_DESC_UPD_KER_STEP 8192 1212*6e173d3bSMartin Habets #define FR_AA_TX_DESC_UPD_KER_ROWS 8 1213*6e173d3bSMartin Habets /* TX_DESC_UPD_REGP123: Transmit descriptor update register. */ 1214*6e173d3bSMartin Habets #define FR_BB_TX_DESC_UPD_P123 0x01000a10 1215*6e173d3bSMartin Habets #define FR_BB_TX_DESC_UPD_P123_STEP 8192 1216*6e173d3bSMartin Habets #define FR_BB_TX_DESC_UPD_P123_ROWS 3072 1217*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_WPTR_LBN 96 1218*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1219*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1220*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1221*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_LBN 0 1222*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_WIDTH 95 1223*6e173d3bSMartin Habets 1224*6e173d3bSMartin Habets /* TX_DC_CFG_REG: Transmit descriptor cache configuration register */ 1225*6e173d3bSMartin Habets #define FR_AZ_TX_DC_CFG 0x00000a20 1226*6e173d3bSMartin Habets #define FRF_AZ_TX_DC_SIZE_LBN 0 1227*6e173d3bSMartin Habets #define FRF_AZ_TX_DC_SIZE_WIDTH 2 1228*6e173d3bSMartin Habets #define FFE_AZ_TX_DC_SIZE_32 2 1229*6e173d3bSMartin Habets #define FFE_AZ_TX_DC_SIZE_16 1 1230*6e173d3bSMartin Habets #define FFE_AZ_TX_DC_SIZE_8 0 1231*6e173d3bSMartin Habets 1232*6e173d3bSMartin Habets /* TX_CHKSM_CFG_REG: Transmit checksum configuration register */ 1233*6e173d3bSMartin Habets #define FR_AA_TX_CHKSM_CFG 0x00000a30 1234*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1235*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1236*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1237*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1238*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1239*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1240*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1241*6e173d3bSMartin Habets #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1242*6e173d3bSMartin Habets 1243*6e173d3bSMartin Habets /* TX_CFG_REG: Transmit configuration register */ 1244*6e173d3bSMartin Habets #define FR_AZ_TX_CFG 0x00000a50 1245*6e173d3bSMartin Habets #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1246*6e173d3bSMartin Habets #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1247*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1248*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1249*6e173d3bSMartin Habets #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1250*6e173d3bSMartin Habets #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1251*6e173d3bSMartin Habets #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1252*6e173d3bSMartin Habets #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1253*6e173d3bSMartin Habets #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1254*6e173d3bSMartin Habets #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1255*6e173d3bSMartin Habets #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1256*6e173d3bSMartin Habets #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1257*6e173d3bSMartin Habets #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1258*6e173d3bSMartin Habets #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1259*6e173d3bSMartin Habets #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1260*6e173d3bSMartin Habets #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1261*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1262*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1263*6e173d3bSMartin Habets #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1264*6e173d3bSMartin Habets #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1265*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1266*6e173d3bSMartin Habets #define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1267*6e173d3bSMartin Habets #define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1268*6e173d3bSMartin Habets #define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1269*6e173d3bSMartin Habets #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1270*6e173d3bSMartin Habets #define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1271*6e173d3bSMartin Habets #define FRF_AZ_TX_P1_PRI_EN_LBN 4 1272*6e173d3bSMartin Habets #define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1273*6e173d3bSMartin Habets #define FRF_AZ_TX_OWNERR_CTL_LBN 2 1274*6e173d3bSMartin Habets #define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1275*6e173d3bSMartin Habets #define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1276*6e173d3bSMartin Habets #define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1277*6e173d3bSMartin Habets #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1278*6e173d3bSMartin Habets #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1279*6e173d3bSMartin Habets 1280*6e173d3bSMartin Habets /* TX_PUSH_DROP_REG: Transmit push dropped register */ 1281*6e173d3bSMartin Habets #define FR_AZ_TX_PUSH_DROP 0x00000a60 1282*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1283*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1284*6e173d3bSMartin Habets 1285*6e173d3bSMartin Habets /* TX_RESERVED_REG: Transmit configuration register */ 1286*6e173d3bSMartin Habets #define FR_AZ_TX_RESERVED 0x00000a80 1287*6e173d3bSMartin Habets #define FRF_AZ_TX_EVT_CNT_LBN 121 1288*6e173d3bSMartin Habets #define FRF_AZ_TX_EVT_CNT_WIDTH 7 1289*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1290*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1291*6e173d3bSMartin Habets #define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1292*6e173d3bSMartin Habets #define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1293*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_EN_LBN 89 1294*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_EN_WIDTH 1 1295*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1296*6e173d3bSMartin Habets #define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1297*6e173d3bSMartin Habets #define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1298*6e173d3bSMartin Habets #define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1299*6e173d3bSMartin Habets #define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1300*6e173d3bSMartin Habets #define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1301*6e173d3bSMartin Habets #define FRF_AZ_TX_DMAQ_ST_LBN 78 1302*6e173d3bSMartin Habets #define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1303*6e173d3bSMartin Habets #define FRF_AZ_TX_RX_SPACER_LBN 64 1304*6e173d3bSMartin Habets #define FRF_AZ_TX_RX_SPACER_WIDTH 8 1305*6e173d3bSMartin Habets #define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1306*6e173d3bSMartin Habets #define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1307*6e173d3bSMartin Habets #define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1308*6e173d3bSMartin Habets #define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1309*6e173d3bSMartin Habets #define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1310*6e173d3bSMartin Habets #define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1311*6e173d3bSMartin Habets #define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1312*6e173d3bSMartin Habets #define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1313*6e173d3bSMartin Habets #define FRF_AZ_TX_XP_TIMER_LBN 52 1314*6e173d3bSMartin Habets #define FRF_AZ_TX_XP_TIMER_WIDTH 5 1315*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_SPACER_LBN 44 1316*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1317*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1318*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1319*6e173d3bSMartin Habets #define FRF_AZ_TX_ONLY1TAG_LBN 21 1320*6e173d3bSMartin Habets #define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1321*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1322*6e173d3bSMartin Habets #define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1323*6e173d3bSMartin Habets #define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1324*6e173d3bSMartin Habets #define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1325*6e173d3bSMartin Habets #define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1326*6e173d3bSMartin Habets #define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1327*6e173d3bSMartin Habets #define FRF_AA_TX_DMA_FF_THR_LBN 16 1328*6e173d3bSMartin Habets #define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1329*6e173d3bSMartin Habets #define FRF_AZ_TX_DMA_SPACER_LBN 8 1330*6e173d3bSMartin Habets #define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1331*6e173d3bSMartin Habets #define FRF_AA_TX_TCP_DIS_LBN 7 1332*6e173d3bSMartin Habets #define FRF_AA_TX_TCP_DIS_WIDTH 1 1333*6e173d3bSMartin Habets #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1334*6e173d3bSMartin Habets #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1335*6e173d3bSMartin Habets #define FRF_AA_TX_IP_DIS_LBN 6 1336*6e173d3bSMartin Habets #define FRF_AA_TX_IP_DIS_WIDTH 1 1337*6e173d3bSMartin Habets #define FRF_AZ_TX_MAX_CPL_LBN 2 1338*6e173d3bSMartin Habets #define FRF_AZ_TX_MAX_CPL_WIDTH 2 1339*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_CPL_16 3 1340*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_CPL_8 2 1341*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_CPL_4 1 1342*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1343*6e173d3bSMartin Habets #define FRF_AZ_TX_MAX_PREF_LBN 0 1344*6e173d3bSMartin Habets #define FRF_AZ_TX_MAX_PREF_WIDTH 2 1345*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_PREF_32 3 1346*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_PREF_16 2 1347*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_PREF_8 1 1348*6e173d3bSMartin Habets #define FFE_AZ_TX_MAX_PREF_OFF 0 1349*6e173d3bSMartin Habets 1350*6e173d3bSMartin Habets /* TX_PACE_REG: Transmit pace control register */ 1351*6e173d3bSMartin Habets #define FR_BZ_TX_PACE 0x00000a90 1352*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_SB_NOT_AF_LBN 19 1353*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 10 1354*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_SB_AF_LBN 9 1355*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_SB_AF_WIDTH 10 1356*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_FB_BASE_LBN 5 1357*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_FB_BASE_WIDTH 4 1358*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_BIN_TH_LBN 0 1359*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_BIN_TH_WIDTH 5 1360*6e173d3bSMartin Habets 1361*6e173d3bSMartin Habets /* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */ 1362*6e173d3bSMartin Habets #define FR_BZ_TX_PACE_DROP_QID 0x00000aa0 1363*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 0 1364*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1365*6e173d3bSMartin Habets 1366*6e173d3bSMartin Habets /* TX_VLAN_REG: Transmit VLAN tag register */ 1367*6e173d3bSMartin Habets #define FR_BB_TX_VLAN 0x00000ae0 1368*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN_EN_LBN 127 1369*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN_EN_WIDTH 1 1370*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_PORT1_EN_LBN 125 1371*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 1 1372*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_PORT0_EN_LBN 124 1373*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 1 1374*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_LBN 112 1375*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN7_WIDTH 12 1376*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_PORT1_EN_LBN 109 1377*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 1 1378*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_PORT0_EN_LBN 108 1379*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 1 1380*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_LBN 96 1381*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN6_WIDTH 12 1382*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_PORT1_EN_LBN 93 1383*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 1 1384*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_PORT0_EN_LBN 92 1385*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 1 1386*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_LBN 80 1387*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN5_WIDTH 12 1388*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_PORT1_EN_LBN 77 1389*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 1 1390*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_PORT0_EN_LBN 76 1391*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 1 1392*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_LBN 64 1393*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN4_WIDTH 12 1394*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_PORT1_EN_LBN 61 1395*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 1 1396*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_PORT0_EN_LBN 60 1397*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 1 1398*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_LBN 48 1399*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN3_WIDTH 12 1400*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_PORT1_EN_LBN 45 1401*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 1 1402*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_PORT0_EN_LBN 44 1403*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 1 1404*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_LBN 32 1405*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN2_WIDTH 12 1406*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_PORT1_EN_LBN 29 1407*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 1 1408*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_PORT0_EN_LBN 28 1409*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 1 1410*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_LBN 16 1411*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN1_WIDTH 12 1412*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_PORT1_EN_LBN 13 1413*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 1 1414*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_PORT0_EN_LBN 12 1415*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 1 1416*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_LBN 0 1417*6e173d3bSMartin Habets #define FRF_BB_TX_VLAN0_WIDTH 12 1418*6e173d3bSMartin Habets 1419*6e173d3bSMartin Habets /* TX_IPFIL_PORTEN_REG: Transmit filter control register */ 1420*6e173d3bSMartin Habets #define FR_BZ_TX_IPFIL_PORTEN 0x00000af0 1421*6e173d3bSMartin Habets #define FRF_BZ_TX_MADR0_FIL_EN_LBN 64 1422*6e173d3bSMartin Habets #define FRF_BZ_TX_MADR0_FIL_EN_WIDTH 1 1423*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL31_PORT_EN_LBN 62 1424*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 1 1425*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL30_PORT_EN_LBN 60 1426*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 1 1427*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL29_PORT_EN_LBN 58 1428*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 1 1429*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL28_PORT_EN_LBN 56 1430*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 1 1431*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL27_PORT_EN_LBN 54 1432*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 1 1433*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL26_PORT_EN_LBN 52 1434*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 1 1435*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL25_PORT_EN_LBN 50 1436*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 1 1437*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL24_PORT_EN_LBN 48 1438*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 1 1439*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL23_PORT_EN_LBN 46 1440*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 1 1441*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL22_PORT_EN_LBN 44 1442*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 1 1443*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL21_PORT_EN_LBN 42 1444*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 1 1445*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL20_PORT_EN_LBN 40 1446*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 1 1447*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL19_PORT_EN_LBN 38 1448*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 1 1449*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL18_PORT_EN_LBN 36 1450*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 1 1451*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL17_PORT_EN_LBN 34 1452*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 1 1453*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL16_PORT_EN_LBN 32 1454*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 1 1455*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL15_PORT_EN_LBN 30 1456*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 1 1457*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL14_PORT_EN_LBN 28 1458*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 1 1459*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL13_PORT_EN_LBN 26 1460*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 1 1461*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL12_PORT_EN_LBN 24 1462*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 1 1463*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL11_PORT_EN_LBN 22 1464*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 1 1465*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL10_PORT_EN_LBN 20 1466*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 1 1467*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL9_PORT_EN_LBN 18 1468*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 1 1469*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL8_PORT_EN_LBN 16 1470*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 1 1471*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL7_PORT_EN_LBN 14 1472*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 1 1473*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL6_PORT_EN_LBN 12 1474*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 1 1475*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL5_PORT_EN_LBN 10 1476*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 1 1477*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL4_PORT_EN_LBN 8 1478*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 1 1479*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL3_PORT_EN_LBN 6 1480*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 1 1481*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL2_PORT_EN_LBN 4 1482*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 1 1483*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL1_PORT_EN_LBN 2 1484*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 1 1485*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL0_PORT_EN_LBN 0 1486*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 1 1487*6e173d3bSMartin Habets 1488*6e173d3bSMartin Habets /* TX_IPFIL_TBL: Transmit IP source address filter table */ 1489*6e173d3bSMartin Habets #define FR_BB_TX_IPFIL_TBL 0x00000b00 1490*6e173d3bSMartin Habets #define FR_BB_TX_IPFIL_TBL_STEP 16 1491*6e173d3bSMartin Habets #define FR_BB_TX_IPFIL_TBL_ROWS 16 1492*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL_MASK_1_LBN 96 1493*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL_MASK_1_WIDTH 32 1494*6e173d3bSMartin Habets #define FRF_BB_TX_IP_SRC_ADR_1_LBN 64 1495*6e173d3bSMartin Habets #define FRF_BB_TX_IP_SRC_ADR_1_WIDTH 32 1496*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL_MASK_0_LBN 32 1497*6e173d3bSMartin Habets #define FRF_BB_TX_IPFIL_MASK_0_WIDTH 32 1498*6e173d3bSMartin Habets #define FRF_BB_TX_IP_SRC_ADR_0_LBN 0 1499*6e173d3bSMartin Habets #define FRF_BB_TX_IP_SRC_ADR_0_WIDTH 32 1500*6e173d3bSMartin Habets 1501*6e173d3bSMartin Habets /* MD_TXD_REG: PHY management transmit data register */ 1502*6e173d3bSMartin Habets #define FR_AB_MD_TXD 0x00000c00 1503*6e173d3bSMartin Habets #define FRF_AB_MD_TXD_LBN 0 1504*6e173d3bSMartin Habets #define FRF_AB_MD_TXD_WIDTH 16 1505*6e173d3bSMartin Habets 1506*6e173d3bSMartin Habets /* MD_RXD_REG: PHY management receive data register */ 1507*6e173d3bSMartin Habets #define FR_AB_MD_RXD 0x00000c10 1508*6e173d3bSMartin Habets #define FRF_AB_MD_RXD_LBN 0 1509*6e173d3bSMartin Habets #define FRF_AB_MD_RXD_WIDTH 16 1510*6e173d3bSMartin Habets 1511*6e173d3bSMartin Habets /* MD_CS_REG: PHY management configuration & status register */ 1512*6e173d3bSMartin Habets #define FR_AB_MD_CS 0x00000c20 1513*6e173d3bSMartin Habets #define FRF_AB_MD_RD_EN_CMD_LBN 15 1514*6e173d3bSMartin Habets #define FRF_AB_MD_RD_EN_CMD_WIDTH 1 1515*6e173d3bSMartin Habets #define FRF_AB_MD_WR_EN_CMD_LBN 14 1516*6e173d3bSMartin Habets #define FRF_AB_MD_WR_EN_CMD_WIDTH 1 1517*6e173d3bSMartin Habets #define FRF_AB_MD_ADDR_CMD_LBN 13 1518*6e173d3bSMartin Habets #define FRF_AB_MD_ADDR_CMD_WIDTH 1 1519*6e173d3bSMartin Habets #define FRF_AB_MD_PT_LBN 7 1520*6e173d3bSMartin Habets #define FRF_AB_MD_PT_WIDTH 3 1521*6e173d3bSMartin Habets #define FRF_AB_MD_PL_LBN 6 1522*6e173d3bSMartin Habets #define FRF_AB_MD_PL_WIDTH 1 1523*6e173d3bSMartin Habets #define FRF_AB_MD_INT_CLR_LBN 5 1524*6e173d3bSMartin Habets #define FRF_AB_MD_INT_CLR_WIDTH 1 1525*6e173d3bSMartin Habets #define FRF_AB_MD_GC_LBN 4 1526*6e173d3bSMartin Habets #define FRF_AB_MD_GC_WIDTH 1 1527*6e173d3bSMartin Habets #define FRF_AB_MD_PRSP_LBN 3 1528*6e173d3bSMartin Habets #define FRF_AB_MD_PRSP_WIDTH 1 1529*6e173d3bSMartin Habets #define FRF_AB_MD_RIC_LBN 2 1530*6e173d3bSMartin Habets #define FRF_AB_MD_RIC_WIDTH 1 1531*6e173d3bSMartin Habets #define FRF_AB_MD_RDC_LBN 1 1532*6e173d3bSMartin Habets #define FRF_AB_MD_RDC_WIDTH 1 1533*6e173d3bSMartin Habets #define FRF_AB_MD_WRC_LBN 0 1534*6e173d3bSMartin Habets #define FRF_AB_MD_WRC_WIDTH 1 1535*6e173d3bSMartin Habets 1536*6e173d3bSMartin Habets /* MD_PHY_ADR_REG: PHY management PHY address register */ 1537*6e173d3bSMartin Habets #define FR_AB_MD_PHY_ADR 0x00000c30 1538*6e173d3bSMartin Habets #define FRF_AB_MD_PHY_ADR_LBN 0 1539*6e173d3bSMartin Habets #define FRF_AB_MD_PHY_ADR_WIDTH 16 1540*6e173d3bSMartin Habets 1541*6e173d3bSMartin Habets /* MD_ID_REG: PHY management ID register */ 1542*6e173d3bSMartin Habets #define FR_AB_MD_ID 0x00000c40 1543*6e173d3bSMartin Habets #define FRF_AB_MD_PRT_ADR_LBN 11 1544*6e173d3bSMartin Habets #define FRF_AB_MD_PRT_ADR_WIDTH 5 1545*6e173d3bSMartin Habets #define FRF_AB_MD_DEV_ADR_LBN 6 1546*6e173d3bSMartin Habets #define FRF_AB_MD_DEV_ADR_WIDTH 5 1547*6e173d3bSMartin Habets 1548*6e173d3bSMartin Habets /* MD_STAT_REG: PHY management status & mask register */ 1549*6e173d3bSMartin Habets #define FR_AB_MD_STAT 0x00000c50 1550*6e173d3bSMartin Habets #define FRF_AB_MD_PINT_LBN 4 1551*6e173d3bSMartin Habets #define FRF_AB_MD_PINT_WIDTH 1 1552*6e173d3bSMartin Habets #define FRF_AB_MD_DONE_LBN 3 1553*6e173d3bSMartin Habets #define FRF_AB_MD_DONE_WIDTH 1 1554*6e173d3bSMartin Habets #define FRF_AB_MD_BSERR_LBN 2 1555*6e173d3bSMartin Habets #define FRF_AB_MD_BSERR_WIDTH 1 1556*6e173d3bSMartin Habets #define FRF_AB_MD_LNFL_LBN 1 1557*6e173d3bSMartin Habets #define FRF_AB_MD_LNFL_WIDTH 1 1558*6e173d3bSMartin Habets #define FRF_AB_MD_BSY_LBN 0 1559*6e173d3bSMartin Habets #define FRF_AB_MD_BSY_WIDTH 1 1560*6e173d3bSMartin Habets 1561*6e173d3bSMartin Habets /* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */ 1562*6e173d3bSMartin Habets #define FR_AB_MAC_STAT_DMA 0x00000c60 1563*6e173d3bSMartin Habets #define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 1564*6e173d3bSMartin Habets #define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 1565*6e173d3bSMartin Habets #define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 1566*6e173d3bSMartin Habets #define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 1567*6e173d3bSMartin Habets 1568*6e173d3bSMartin Habets /* MAC_CTRL_REG: Port MAC control register */ 1569*6e173d3bSMartin Habets #define FR_AB_MAC_CTRL 0x00000c80 1570*6e173d3bSMartin Habets #define FRF_AB_MAC_XOFF_VAL_LBN 16 1571*6e173d3bSMartin Habets #define FRF_AB_MAC_XOFF_VAL_WIDTH 16 1572*6e173d3bSMartin Habets #define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 1573*6e173d3bSMartin Habets #define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 1574*6e173d3bSMartin Habets #define FRF_AB_MAC_XG_DISTXCRC_LBN 5 1575*6e173d3bSMartin Habets #define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 1576*6e173d3bSMartin Habets #define FRF_AB_MAC_BCAD_ACPT_LBN 4 1577*6e173d3bSMartin Habets #define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 1578*6e173d3bSMartin Habets #define FRF_AB_MAC_UC_PROM_LBN 3 1579*6e173d3bSMartin Habets #define FRF_AB_MAC_UC_PROM_WIDTH 1 1580*6e173d3bSMartin Habets #define FRF_AB_MAC_LINK_STATUS_LBN 2 1581*6e173d3bSMartin Habets #define FRF_AB_MAC_LINK_STATUS_WIDTH 1 1582*6e173d3bSMartin Habets #define FRF_AB_MAC_SPEED_LBN 0 1583*6e173d3bSMartin Habets #define FRF_AB_MAC_SPEED_WIDTH 2 1584*6e173d3bSMartin Habets #define FFE_AB_MAC_SPEED_10G 3 1585*6e173d3bSMartin Habets #define FFE_AB_MAC_SPEED_1G 2 1586*6e173d3bSMartin Habets #define FFE_AB_MAC_SPEED_100M 1 1587*6e173d3bSMartin Habets #define FFE_AB_MAC_SPEED_10M 0 1588*6e173d3bSMartin Habets 1589*6e173d3bSMartin Habets /* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */ 1590*6e173d3bSMartin Habets #define FR_BB_GEN_MODE 0x00000c90 1591*6e173d3bSMartin Habets #define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 1592*6e173d3bSMartin Habets #define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 1593*6e173d3bSMartin Habets #define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 1594*6e173d3bSMartin Habets #define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 1595*6e173d3bSMartin Habets #define FRF_BB_XFP_PHY_INT_MASK_LBN 1 1596*6e173d3bSMartin Habets #define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 1597*6e173d3bSMartin Habets #define FRF_BB_XG_PHY_INT_MASK_LBN 0 1598*6e173d3bSMartin Habets #define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 1599*6e173d3bSMartin Habets 1600*6e173d3bSMartin Habets /* MAC_MC_HASH_REG0: Multicast address hash table */ 1601*6e173d3bSMartin Habets #define FR_AB_MAC_MC_HASH_REG0 0x00000ca0 1602*6e173d3bSMartin Habets #define FRF_AB_MAC_MCAST_HASH0_LBN 0 1603*6e173d3bSMartin Habets #define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 1604*6e173d3bSMartin Habets 1605*6e173d3bSMartin Habets /* MAC_MC_HASH_REG1: Multicast address hash table */ 1606*6e173d3bSMartin Habets #define FR_AB_MAC_MC_HASH_REG1 0x00000cb0 1607*6e173d3bSMartin Habets #define FRF_AB_MAC_MCAST_HASH1_LBN 0 1608*6e173d3bSMartin Habets #define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 1609*6e173d3bSMartin Habets 1610*6e173d3bSMartin Habets /* GM_CFG1_REG: GMAC configuration register 1 */ 1611*6e173d3bSMartin Habets #define FR_AB_GM_CFG1 0x00000e00 1612*6e173d3bSMartin Habets #define FRF_AB_GM_SW_RST_LBN 31 1613*6e173d3bSMartin Habets #define FRF_AB_GM_SW_RST_WIDTH 1 1614*6e173d3bSMartin Habets #define FRF_AB_GM_SIM_RST_LBN 30 1615*6e173d3bSMartin Habets #define FRF_AB_GM_SIM_RST_WIDTH 1 1616*6e173d3bSMartin Habets #define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 1617*6e173d3bSMartin Habets #define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 1618*6e173d3bSMartin Habets #define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 1619*6e173d3bSMartin Habets #define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 1620*6e173d3bSMartin Habets #define FRF_AB_GM_RST_RX_FUNC_LBN 17 1621*6e173d3bSMartin Habets #define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 1622*6e173d3bSMartin Habets #define FRF_AB_GM_RST_TX_FUNC_LBN 16 1623*6e173d3bSMartin Habets #define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 1624*6e173d3bSMartin Habets #define FRF_AB_GM_LOOP_LBN 8 1625*6e173d3bSMartin Habets #define FRF_AB_GM_LOOP_WIDTH 1 1626*6e173d3bSMartin Habets #define FRF_AB_GM_RX_FC_EN_LBN 5 1627*6e173d3bSMartin Habets #define FRF_AB_GM_RX_FC_EN_WIDTH 1 1628*6e173d3bSMartin Habets #define FRF_AB_GM_TX_FC_EN_LBN 4 1629*6e173d3bSMartin Habets #define FRF_AB_GM_TX_FC_EN_WIDTH 1 1630*6e173d3bSMartin Habets #define FRF_AB_GM_SYNC_RXEN_LBN 3 1631*6e173d3bSMartin Habets #define FRF_AB_GM_SYNC_RXEN_WIDTH 1 1632*6e173d3bSMartin Habets #define FRF_AB_GM_RX_EN_LBN 2 1633*6e173d3bSMartin Habets #define FRF_AB_GM_RX_EN_WIDTH 1 1634*6e173d3bSMartin Habets #define FRF_AB_GM_SYNC_TXEN_LBN 1 1635*6e173d3bSMartin Habets #define FRF_AB_GM_SYNC_TXEN_WIDTH 1 1636*6e173d3bSMartin Habets #define FRF_AB_GM_TX_EN_LBN 0 1637*6e173d3bSMartin Habets #define FRF_AB_GM_TX_EN_WIDTH 1 1638*6e173d3bSMartin Habets 1639*6e173d3bSMartin Habets /* GM_CFG2_REG: GMAC configuration register 2 */ 1640*6e173d3bSMartin Habets #define FR_AB_GM_CFG2 0x00000e10 1641*6e173d3bSMartin Habets #define FRF_AB_GM_PAMBL_LEN_LBN 12 1642*6e173d3bSMartin Habets #define FRF_AB_GM_PAMBL_LEN_WIDTH 4 1643*6e173d3bSMartin Habets #define FRF_AB_GM_IF_MODE_LBN 8 1644*6e173d3bSMartin Habets #define FRF_AB_GM_IF_MODE_WIDTH 2 1645*6e173d3bSMartin Habets #define FFE_AB_IF_MODE_BYTE_MODE 2 1646*6e173d3bSMartin Habets #define FFE_AB_IF_MODE_NIBBLE_MODE 1 1647*6e173d3bSMartin Habets #define FRF_AB_GM_HUGE_FRM_EN_LBN 5 1648*6e173d3bSMartin Habets #define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 1649*6e173d3bSMartin Habets #define FRF_AB_GM_LEN_CHK_LBN 4 1650*6e173d3bSMartin Habets #define FRF_AB_GM_LEN_CHK_WIDTH 1 1651*6e173d3bSMartin Habets #define FRF_AB_GM_PAD_CRC_EN_LBN 2 1652*6e173d3bSMartin Habets #define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 1653*6e173d3bSMartin Habets #define FRF_AB_GM_CRC_EN_LBN 1 1654*6e173d3bSMartin Habets #define FRF_AB_GM_CRC_EN_WIDTH 1 1655*6e173d3bSMartin Habets #define FRF_AB_GM_FD_LBN 0 1656*6e173d3bSMartin Habets #define FRF_AB_GM_FD_WIDTH 1 1657*6e173d3bSMartin Habets 1658*6e173d3bSMartin Habets /* GM_IPG_REG: GMAC IPG register */ 1659*6e173d3bSMartin Habets #define FR_AB_GM_IPG 0x00000e20 1660*6e173d3bSMartin Habets #define FRF_AB_GM_NONB2B_IPG1_LBN 24 1661*6e173d3bSMartin Habets #define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 1662*6e173d3bSMartin Habets #define FRF_AB_GM_NONB2B_IPG2_LBN 16 1663*6e173d3bSMartin Habets #define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 1664*6e173d3bSMartin Habets #define FRF_AB_GM_MIN_IPG_ENF_LBN 8 1665*6e173d3bSMartin Habets #define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 1666*6e173d3bSMartin Habets #define FRF_AB_GM_B2B_IPG_LBN 0 1667*6e173d3bSMartin Habets #define FRF_AB_GM_B2B_IPG_WIDTH 7 1668*6e173d3bSMartin Habets 1669*6e173d3bSMartin Habets /* GM_HD_REG: GMAC half duplex register */ 1670*6e173d3bSMartin Habets #define FR_AB_GM_HD 0x00000e30 1671*6e173d3bSMartin Habets #define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 1672*6e173d3bSMartin Habets #define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 1673*6e173d3bSMartin Habets #define FRF_AB_GM_ALT_BOFF_EN_LBN 19 1674*6e173d3bSMartin Habets #define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 1675*6e173d3bSMartin Habets #define FRF_AB_GM_BP_NO_BOFF_LBN 18 1676*6e173d3bSMartin Habets #define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 1677*6e173d3bSMartin Habets #define FRF_AB_GM_DIS_BOFF_LBN 17 1678*6e173d3bSMartin Habets #define FRF_AB_GM_DIS_BOFF_WIDTH 1 1679*6e173d3bSMartin Habets #define FRF_AB_GM_EXDEF_TX_EN_LBN 16 1680*6e173d3bSMartin Habets #define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 1681*6e173d3bSMartin Habets #define FRF_AB_GM_RTRY_LIMIT_LBN 12 1682*6e173d3bSMartin Habets #define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 1683*6e173d3bSMartin Habets #define FRF_AB_GM_COL_WIN_LBN 0 1684*6e173d3bSMartin Habets #define FRF_AB_GM_COL_WIN_WIDTH 10 1685*6e173d3bSMartin Habets 1686*6e173d3bSMartin Habets /* GM_MAX_FLEN_REG: GMAC maximum frame length register */ 1687*6e173d3bSMartin Habets #define FR_AB_GM_MAX_FLEN 0x00000e40 1688*6e173d3bSMartin Habets #define FRF_AB_GM_MAX_FLEN_LBN 0 1689*6e173d3bSMartin Habets #define FRF_AB_GM_MAX_FLEN_WIDTH 16 1690*6e173d3bSMartin Habets 1691*6e173d3bSMartin Habets /* GM_TEST_REG: GMAC test register */ 1692*6e173d3bSMartin Habets #define FR_AB_GM_TEST 0x00000e70 1693*6e173d3bSMartin Habets #define FRF_AB_GM_MAX_BOFF_LBN 3 1694*6e173d3bSMartin Habets #define FRF_AB_GM_MAX_BOFF_WIDTH 1 1695*6e173d3bSMartin Habets #define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 1696*6e173d3bSMartin Habets #define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 1697*6e173d3bSMartin Habets #define FRF_AB_GM_TEST_PAUSE_LBN 1 1698*6e173d3bSMartin Habets #define FRF_AB_GM_TEST_PAUSE_WIDTH 1 1699*6e173d3bSMartin Habets #define FRF_AB_GM_SHORT_SLOT_LBN 0 1700*6e173d3bSMartin Habets #define FRF_AB_GM_SHORT_SLOT_WIDTH 1 1701*6e173d3bSMartin Habets 1702*6e173d3bSMartin Habets /* GM_ADR1_REG: GMAC station address register 1 */ 1703*6e173d3bSMartin Habets #define FR_AB_GM_ADR1 0x00000f00 1704*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B0_LBN 24 1705*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B0_WIDTH 8 1706*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B1_LBN 16 1707*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B1_WIDTH 8 1708*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B2_LBN 8 1709*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B2_WIDTH 8 1710*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B3_LBN 0 1711*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B3_WIDTH 8 1712*6e173d3bSMartin Habets 1713*6e173d3bSMartin Habets /* GM_ADR2_REG: GMAC station address register 2 */ 1714*6e173d3bSMartin Habets #define FR_AB_GM_ADR2 0x00000f10 1715*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B4_LBN 24 1716*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B4_WIDTH 8 1717*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B5_LBN 16 1718*6e173d3bSMartin Habets #define FRF_AB_GM_ADR_B5_WIDTH 8 1719*6e173d3bSMartin Habets 1720*6e173d3bSMartin Habets /* GMF_CFG0_REG: GMAC FIFO configuration register 0 */ 1721*6e173d3bSMartin Habets #define FR_AB_GMF_CFG0 0x00000f20 1722*6e173d3bSMartin Habets #define FRF_AB_GMF_FTFENRPLY_LBN 20 1723*6e173d3bSMartin Habets #define FRF_AB_GMF_FTFENRPLY_WIDTH 1 1724*6e173d3bSMartin Habets #define FRF_AB_GMF_STFENRPLY_LBN 19 1725*6e173d3bSMartin Habets #define FRF_AB_GMF_STFENRPLY_WIDTH 1 1726*6e173d3bSMartin Habets #define FRF_AB_GMF_FRFENRPLY_LBN 18 1727*6e173d3bSMartin Habets #define FRF_AB_GMF_FRFENRPLY_WIDTH 1 1728*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFENRPLY_LBN 17 1729*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFENRPLY_WIDTH 1 1730*6e173d3bSMartin Habets #define FRF_AB_GMF_WTMENRPLY_LBN 16 1731*6e173d3bSMartin Habets #define FRF_AB_GMF_WTMENRPLY_WIDTH 1 1732*6e173d3bSMartin Habets #define FRF_AB_GMF_FTFENREQ_LBN 12 1733*6e173d3bSMartin Habets #define FRF_AB_GMF_FTFENREQ_WIDTH 1 1734*6e173d3bSMartin Habets #define FRF_AB_GMF_STFENREQ_LBN 11 1735*6e173d3bSMartin Habets #define FRF_AB_GMF_STFENREQ_WIDTH 1 1736*6e173d3bSMartin Habets #define FRF_AB_GMF_FRFENREQ_LBN 10 1737*6e173d3bSMartin Habets #define FRF_AB_GMF_FRFENREQ_WIDTH 1 1738*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFENREQ_LBN 9 1739*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFENREQ_WIDTH 1 1740*6e173d3bSMartin Habets #define FRF_AB_GMF_WTMENREQ_LBN 8 1741*6e173d3bSMartin Habets #define FRF_AB_GMF_WTMENREQ_WIDTH 1 1742*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTFT_LBN 4 1743*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTFT_WIDTH 1 1744*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTST_LBN 3 1745*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTST_WIDTH 1 1746*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTFR_LBN 2 1747*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTFR_WIDTH 1 1748*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTSR_LBN 1 1749*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTSR_WIDTH 1 1750*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTWT_LBN 0 1751*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTRSTWT_WIDTH 1 1752*6e173d3bSMartin Habets 1753*6e173d3bSMartin Habets /* GMF_CFG1_REG: GMAC FIFO configuration register 1 */ 1754*6e173d3bSMartin Habets #define FR_AB_GMF_CFG1 0x00000f30 1755*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGFRTH_LBN 16 1756*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGFRTH_WIDTH 5 1757*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGXOFFRTX_LBN 0 1758*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 1759*6e173d3bSMartin Habets 1760*6e173d3bSMartin Habets /* GMF_CFG2_REG: GMAC FIFO configuration register 2 */ 1761*6e173d3bSMartin Habets #define FR_AB_GMF_CFG2 0x00000f40 1762*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHWM_LBN 16 1763*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHWM_WIDTH 6 1764*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGLWM_LBN 0 1765*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGLWM_WIDTH 6 1766*6e173d3bSMartin Habets 1767*6e173d3bSMartin Habets /* GMF_CFG3_REG: GMAC FIFO configuration register 3 */ 1768*6e173d3bSMartin Habets #define FR_AB_GMF_CFG3 0x00000f50 1769*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHWMFT_LBN 16 1770*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHWMFT_WIDTH 6 1771*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGFTTH_LBN 0 1772*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGFTTH_WIDTH 6 1773*6e173d3bSMartin Habets 1774*6e173d3bSMartin Habets /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */ 1775*6e173d3bSMartin Habets #define FR_AB_GMF_CFG4 0x00000f60 1776*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRM_LBN 0 1777*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 1778*6e173d3bSMartin Habets 1779*6e173d3bSMartin Habets /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */ 1780*6e173d3bSMartin Habets #define FR_AB_GMF_CFG5 0x00000f70 1781*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHDPLX_LBN 22 1782*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGHDPLX_WIDTH 1 1783*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFULL_LBN 21 1784*6e173d3bSMartin Habets #define FRF_AB_GMF_SRFULL_WIDTH 1 1785*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 1786*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 1787*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGBYTMODE_LBN 19 1788*6e173d3bSMartin Habets #define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 1789*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTDRPLT64_LBN 18 1790*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 1791*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 1792*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 1793*6e173d3bSMartin Habets 1794*6e173d3bSMartin Habets /* TX_SRC_MAC_TBL: Transmit IP source address filter table */ 1795*6e173d3bSMartin Habets #define FR_BB_TX_SRC_MAC_TBL 0x00001000 1796*6e173d3bSMartin Habets #define FR_BB_TX_SRC_MAC_TBL_STEP 16 1797*6e173d3bSMartin Habets #define FR_BB_TX_SRC_MAC_TBL_ROWS 16 1798*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 1799*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 1800*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 1801*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 1802*6e173d3bSMartin Habets 1803*6e173d3bSMartin Habets /* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */ 1804*6e173d3bSMartin Habets #define FR_BB_TX_SRC_MAC_CTL 0x00001100 1805*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_DROP_CTR_LBN 16 1806*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 1807*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_FLTR_EN_LBN 15 1808*6e173d3bSMartin Habets #define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 1809*6e173d3bSMartin Habets #define FRF_BB_TX_DROP_CTR_CLR_LBN 12 1810*6e173d3bSMartin Habets #define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 1811*6e173d3bSMartin Habets #define FRF_BB_TX_MAC_QID_SEL_LBN 0 1812*6e173d3bSMartin Habets #define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 1813*6e173d3bSMartin Habets 1814*6e173d3bSMartin Habets /* XM_ADR_LO_REG: XGMAC address register low */ 1815*6e173d3bSMartin Habets #define FR_AB_XM_ADR_LO 0x00001200 1816*6e173d3bSMartin Habets #define FRF_AB_XM_ADR_LO_LBN 0 1817*6e173d3bSMartin Habets #define FRF_AB_XM_ADR_LO_WIDTH 32 1818*6e173d3bSMartin Habets 1819*6e173d3bSMartin Habets /* XM_ADR_HI_REG: XGMAC address register high */ 1820*6e173d3bSMartin Habets #define FR_AB_XM_ADR_HI 0x00001210 1821*6e173d3bSMartin Habets #define FRF_AB_XM_ADR_HI_LBN 0 1822*6e173d3bSMartin Habets #define FRF_AB_XM_ADR_HI_WIDTH 16 1823*6e173d3bSMartin Habets 1824*6e173d3bSMartin Habets /* XM_GLB_CFG_REG: XGMAC global configuration */ 1825*6e173d3bSMartin Habets #define FR_AB_XM_GLB_CFG 0x00001220 1826*6e173d3bSMartin Habets #define FRF_AB_XM_RMTFLT_GEN_LBN 17 1827*6e173d3bSMartin Habets #define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 1828*6e173d3bSMartin Habets #define FRF_AB_XM_DEBUG_MODE_LBN 16 1829*6e173d3bSMartin Habets #define FRF_AB_XM_DEBUG_MODE_WIDTH 1 1830*6e173d3bSMartin Habets #define FRF_AB_XM_RX_STAT_EN_LBN 11 1831*6e173d3bSMartin Habets #define FRF_AB_XM_RX_STAT_EN_WIDTH 1 1832*6e173d3bSMartin Habets #define FRF_AB_XM_TX_STAT_EN_LBN 10 1833*6e173d3bSMartin Habets #define FRF_AB_XM_TX_STAT_EN_WIDTH 1 1834*6e173d3bSMartin Habets #define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 1835*6e173d3bSMartin Habets #define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 1836*6e173d3bSMartin Habets #define FRF_AB_XM_WAN_MODE_LBN 5 1837*6e173d3bSMartin Habets #define FRF_AB_XM_WAN_MODE_WIDTH 1 1838*6e173d3bSMartin Habets #define FRF_AB_XM_INTCLR_MODE_LBN 3 1839*6e173d3bSMartin Habets #define FRF_AB_XM_INTCLR_MODE_WIDTH 1 1840*6e173d3bSMartin Habets #define FRF_AB_XM_CORE_RST_LBN 0 1841*6e173d3bSMartin Habets #define FRF_AB_XM_CORE_RST_WIDTH 1 1842*6e173d3bSMartin Habets 1843*6e173d3bSMartin Habets /* XM_TX_CFG_REG: XGMAC transmit configuration */ 1844*6e173d3bSMartin Habets #define FR_AB_XM_TX_CFG 0x00001230 1845*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PROG_LBN 24 1846*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PROG_WIDTH 1 1847*6e173d3bSMartin Habets #define FRF_AB_XM_IPG_LBN 16 1848*6e173d3bSMartin Habets #define FRF_AB_XM_IPG_WIDTH 4 1849*6e173d3bSMartin Habets #define FRF_AB_XM_FCNTL_LBN 10 1850*6e173d3bSMartin Habets #define FRF_AB_XM_FCNTL_WIDTH 1 1851*6e173d3bSMartin Habets #define FRF_AB_XM_TXCRC_LBN 8 1852*6e173d3bSMartin Habets #define FRF_AB_XM_TXCRC_WIDTH 1 1853*6e173d3bSMartin Habets #define FRF_AB_XM_EDRC_LBN 6 1854*6e173d3bSMartin Habets #define FRF_AB_XM_EDRC_WIDTH 1 1855*6e173d3bSMartin Habets #define FRF_AB_XM_AUTO_PAD_LBN 5 1856*6e173d3bSMartin Habets #define FRF_AB_XM_AUTO_PAD_WIDTH 1 1857*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PRMBL_LBN 2 1858*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PRMBL_WIDTH 1 1859*6e173d3bSMartin Habets #define FRF_AB_XM_TXEN_LBN 1 1860*6e173d3bSMartin Habets #define FRF_AB_XM_TXEN_WIDTH 1 1861*6e173d3bSMartin Habets #define FRF_AB_XM_TX_RST_LBN 0 1862*6e173d3bSMartin Habets #define FRF_AB_XM_TX_RST_WIDTH 1 1863*6e173d3bSMartin Habets 1864*6e173d3bSMartin Habets /* XM_RX_CFG_REG: XGMAC receive configuration */ 1865*6e173d3bSMartin Habets #define FR_AB_XM_RX_CFG 0x00001240 1866*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_LENERR_LBN 26 1867*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_LENERR_WIDTH 1 1868*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_CRC_ERR_LBN 25 1869*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 1870*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 1871*6e173d3bSMartin Habets #define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 1872*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_BCAST_LBN 20 1873*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_BCAST_WIDTH 1 1874*6e173d3bSMartin Habets #define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 1875*6e173d3bSMartin Habets #define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 1876*6e173d3bSMartin Habets #define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 1877*6e173d3bSMartin Habets #define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 1878*6e173d3bSMartin Habets #define FRF_AB_XM_AUTO_DEPAD_LBN 8 1879*6e173d3bSMartin Habets #define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 1880*6e173d3bSMartin Habets #define FRF_AB_XM_RXCRC_LBN 3 1881*6e173d3bSMartin Habets #define FRF_AB_XM_RXCRC_WIDTH 1 1882*6e173d3bSMartin Habets #define FRF_AB_XM_RX_PRMBL_LBN 2 1883*6e173d3bSMartin Habets #define FRF_AB_XM_RX_PRMBL_WIDTH 1 1884*6e173d3bSMartin Habets #define FRF_AB_XM_RXEN_LBN 1 1885*6e173d3bSMartin Habets #define FRF_AB_XM_RXEN_WIDTH 1 1886*6e173d3bSMartin Habets #define FRF_AB_XM_RX_RST_LBN 0 1887*6e173d3bSMartin Habets #define FRF_AB_XM_RX_RST_WIDTH 1 1888*6e173d3bSMartin Habets 1889*6e173d3bSMartin Habets /* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */ 1890*6e173d3bSMartin Habets #define FR_AB_XM_MGT_INT_MASK 0x00001250 1891*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STA_INTR_LBN 16 1892*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 1893*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 1894*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 1895*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 1896*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 1897*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 1898*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 1899*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_RMTFLT_LBN 1 1900*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 1901*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_LCLFLT_LBN 0 1902*6e173d3bSMartin Habets #define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 1903*6e173d3bSMartin Habets 1904*6e173d3bSMartin Habets /* XM_FC_REG: XGMAC flow control register */ 1905*6e173d3bSMartin Habets #define FR_AB_XM_FC 0x00001270 1906*6e173d3bSMartin Habets #define FRF_AB_XM_PAUSE_TIME_LBN 16 1907*6e173d3bSMartin Habets #define FRF_AB_XM_PAUSE_TIME_WIDTH 16 1908*6e173d3bSMartin Habets #define FRF_AB_XM_RX_MAC_STAT_LBN 11 1909*6e173d3bSMartin Habets #define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 1910*6e173d3bSMartin Habets #define FRF_AB_XM_TX_MAC_STAT_LBN 10 1911*6e173d3bSMartin Habets #define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 1912*6e173d3bSMartin Habets #define FRF_AB_XM_MCNTL_PASS_LBN 8 1913*6e173d3bSMartin Habets #define FRF_AB_XM_MCNTL_PASS_WIDTH 2 1914*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 1915*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 1916*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 1917*6e173d3bSMartin Habets #define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 1918*6e173d3bSMartin Habets #define FRF_AB_XM_ZPAUSE_LBN 2 1919*6e173d3bSMartin Habets #define FRF_AB_XM_ZPAUSE_WIDTH 1 1920*6e173d3bSMartin Habets #define FRF_AB_XM_XMIT_PAUSE_LBN 1 1921*6e173d3bSMartin Habets #define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 1922*6e173d3bSMartin Habets #define FRF_AB_XM_DIS_FCNTL_LBN 0 1923*6e173d3bSMartin Habets #define FRF_AB_XM_DIS_FCNTL_WIDTH 1 1924*6e173d3bSMartin Habets 1925*6e173d3bSMartin Habets /* XM_PAUSE_TIME_REG: XGMAC pause time register */ 1926*6e173d3bSMartin Habets #define FR_AB_XM_PAUSE_TIME 0x00001290 1927*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 1928*6e173d3bSMartin Habets #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 1929*6e173d3bSMartin Habets #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 1930*6e173d3bSMartin Habets #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 1931*6e173d3bSMartin Habets 1932*6e173d3bSMartin Habets /* XM_TX_PARAM_REG: XGMAC transmit parameter register */ 1933*6e173d3bSMartin Habets #define FR_AB_XM_TX_PARAM 0x000012d0 1934*6e173d3bSMartin Habets #define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 1935*6e173d3bSMartin Habets #define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 1936*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 1937*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 1938*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 1939*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 1940*6e173d3bSMartin Habets #define FRF_AB_XM_PAD_CHAR_LBN 0 1941*6e173d3bSMartin Habets #define FRF_AB_XM_PAD_CHAR_WIDTH 8 1942*6e173d3bSMartin Habets 1943*6e173d3bSMartin Habets /* XM_RX_PARAM_REG: XGMAC receive parameter register */ 1944*6e173d3bSMartin Habets #define FR_AB_XM_RX_PARAM 0x000012e0 1945*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 1946*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 1947*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 1948*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 1949*6e173d3bSMartin Habets 1950*6e173d3bSMartin Habets /* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */ 1951*6e173d3bSMartin Habets #define FR_AB_XM_MGT_INT_MSK 0x000012f0 1952*6e173d3bSMartin Habets #define FRF_AB_XM_STAT_CNTR_OF_LBN 9 1953*6e173d3bSMartin Habets #define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 1954*6e173d3bSMartin Habets #define FRF_AB_XM_STAT_CNTR_HF_LBN 8 1955*6e173d3bSMartin Habets #define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 1956*6e173d3bSMartin Habets #define FRF_AB_XM_PRMBLE_ERR_LBN 2 1957*6e173d3bSMartin Habets #define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 1958*6e173d3bSMartin Habets #define FRF_AB_XM_RMTFLT_LBN 1 1959*6e173d3bSMartin Habets #define FRF_AB_XM_RMTFLT_WIDTH 1 1960*6e173d3bSMartin Habets #define FRF_AB_XM_LCLFLT_LBN 0 1961*6e173d3bSMartin Habets #define FRF_AB_XM_LCLFLT_WIDTH 1 1962*6e173d3bSMartin Habets 1963*6e173d3bSMartin Habets /* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */ 1964*6e173d3bSMartin Habets #define FR_AB_XX_PWR_RST 0x00001300 1965*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDND_SIG_LBN 31 1966*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDND_SIG_WIDTH 1 1967*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNC_SIG_LBN 30 1968*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 1969*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNB_SIG_LBN 29 1970*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 1971*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNA_SIG_LBN 28 1972*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 1973*6e173d3bSMartin Habets #define FRF_AB_XX_SIM_MODE_LBN 27 1974*6e173d3bSMartin Habets #define FRF_AB_XX_SIM_MODE_WIDTH 1 1975*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 1976*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 1977*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 1978*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 1979*6e173d3bSMartin Habets #define FRF_AB_XX_RESETD_SIG_LBN 23 1980*6e173d3bSMartin Habets #define FRF_AB_XX_RESETD_SIG_WIDTH 1 1981*6e173d3bSMartin Habets #define FRF_AB_XX_RESETC_SIG_LBN 22 1982*6e173d3bSMartin Habets #define FRF_AB_XX_RESETC_SIG_WIDTH 1 1983*6e173d3bSMartin Habets #define FRF_AB_XX_RESETB_SIG_LBN 21 1984*6e173d3bSMartin Habets #define FRF_AB_XX_RESETB_SIG_WIDTH 1 1985*6e173d3bSMartin Habets #define FRF_AB_XX_RESETA_SIG_LBN 20 1986*6e173d3bSMartin Habets #define FRF_AB_XX_RESETA_SIG_WIDTH 1 1987*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 1988*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 1989*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 1990*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 1991*6e173d3bSMartin Habets #define FRF_AB_XX_SD_RST_ACT_LBN 16 1992*6e173d3bSMartin Habets #define FRF_AB_XX_SD_RST_ACT_WIDTH 1 1993*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDND_EN_LBN 15 1994*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDND_EN_WIDTH 1 1995*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNC_EN_LBN 14 1996*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNC_EN_WIDTH 1 1997*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNB_EN_LBN 13 1998*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNB_EN_WIDTH 1 1999*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNA_EN_LBN 12 2000*6e173d3bSMartin Habets #define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2001*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2002*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2003*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2004*6e173d3bSMartin Habets #define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2005*6e173d3bSMartin Habets #define FRF_AB_XX_RESETD_EN_LBN 7 2006*6e173d3bSMartin Habets #define FRF_AB_XX_RESETD_EN_WIDTH 1 2007*6e173d3bSMartin Habets #define FRF_AB_XX_RESETC_EN_LBN 6 2008*6e173d3bSMartin Habets #define FRF_AB_XX_RESETC_EN_WIDTH 1 2009*6e173d3bSMartin Habets #define FRF_AB_XX_RESETB_EN_LBN 5 2010*6e173d3bSMartin Habets #define FRF_AB_XX_RESETB_EN_WIDTH 1 2011*6e173d3bSMartin Habets #define FRF_AB_XX_RESETA_EN_LBN 4 2012*6e173d3bSMartin Habets #define FRF_AB_XX_RESETA_EN_WIDTH 1 2013*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2014*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2015*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2016*6e173d3bSMartin Habets #define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2017*6e173d3bSMartin Habets #define FRF_AB_XX_RST_XX_EN_LBN 0 2018*6e173d3bSMartin Habets #define FRF_AB_XX_RST_XX_EN_WIDTH 1 2019*6e173d3bSMartin Habets 2020*6e173d3bSMartin Habets /* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */ 2021*6e173d3bSMartin Habets #define FR_AB_XX_SD_CTL 0x00001310 2022*6e173d3bSMartin Habets #define FRF_AB_XX_TERMADJ1_LBN 17 2023*6e173d3bSMartin Habets #define FRF_AB_XX_TERMADJ1_WIDTH 1 2024*6e173d3bSMartin Habets #define FRF_AB_XX_TERMADJ0_LBN 16 2025*6e173d3bSMartin Habets #define FRF_AB_XX_TERMADJ0_WIDTH 1 2026*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVD_LBN 15 2027*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVD_WIDTH 1 2028*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVD_LBN 14 2029*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVD_WIDTH 1 2030*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVC_LBN 13 2031*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVC_WIDTH 1 2032*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVC_LBN 12 2033*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVC_WIDTH 1 2034*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVB_LBN 11 2035*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVB_WIDTH 1 2036*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVB_LBN 10 2037*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVB_WIDTH 1 2038*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVA_LBN 9 2039*6e173d3bSMartin Habets #define FRF_AB_XX_HIDRVA_WIDTH 1 2040*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVA_LBN 8 2041*6e173d3bSMartin Habets #define FRF_AB_XX_LODRVA_WIDTH 1 2042*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKD_LBN 3 2043*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKD_WIDTH 1 2044*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKC_LBN 2 2045*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKC_WIDTH 1 2046*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKB_LBN 1 2047*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKB_WIDTH 1 2048*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKA_LBN 0 2049*6e173d3bSMartin Habets #define FRF_AB_XX_LPBKA_WIDTH 1 2050*6e173d3bSMartin Habets 2051*6e173d3bSMartin Habets /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */ 2052*6e173d3bSMartin Habets #define FR_AB_XX_TXDRV_CTL 0x00001320 2053*6e173d3bSMartin Habets #define FRF_AB_XX_DEQD_LBN 28 2054*6e173d3bSMartin Habets #define FRF_AB_XX_DEQD_WIDTH 4 2055*6e173d3bSMartin Habets #define FRF_AB_XX_DEQC_LBN 24 2056*6e173d3bSMartin Habets #define FRF_AB_XX_DEQC_WIDTH 4 2057*6e173d3bSMartin Habets #define FRF_AB_XX_DEQB_LBN 20 2058*6e173d3bSMartin Habets #define FRF_AB_XX_DEQB_WIDTH 4 2059*6e173d3bSMartin Habets #define FRF_AB_XX_DEQA_LBN 16 2060*6e173d3bSMartin Habets #define FRF_AB_XX_DEQA_WIDTH 4 2061*6e173d3bSMartin Habets #define FRF_AB_XX_DTXD_LBN 12 2062*6e173d3bSMartin Habets #define FRF_AB_XX_DTXD_WIDTH 4 2063*6e173d3bSMartin Habets #define FRF_AB_XX_DTXC_LBN 8 2064*6e173d3bSMartin Habets #define FRF_AB_XX_DTXC_WIDTH 4 2065*6e173d3bSMartin Habets #define FRF_AB_XX_DTXB_LBN 4 2066*6e173d3bSMartin Habets #define FRF_AB_XX_DTXB_WIDTH 4 2067*6e173d3bSMartin Habets #define FRF_AB_XX_DTXA_LBN 0 2068*6e173d3bSMartin Habets #define FRF_AB_XX_DTXA_WIDTH 4 2069*6e173d3bSMartin Habets 2070*6e173d3bSMartin Habets /* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */ 2071*6e173d3bSMartin Habets #define FR_AB_XX_PRBS_CTL 0x00001330 2072*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2073*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2074*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2075*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2076*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2077*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2078*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2079*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2080*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2081*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2082*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2083*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2084*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2085*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2086*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2087*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2088*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2089*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2090*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2091*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2092*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2093*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2094*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2095*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2096*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2097*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2098*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2099*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2100*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2101*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2102*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2103*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2104*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2105*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2106*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2107*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2108*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2109*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2110*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2111*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2112*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2113*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2114*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2115*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2116*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2117*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 2118*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 2119*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 2120*6e173d3bSMartin Habets 2121*6e173d3bSMartin Habets /* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */ 2122*6e173d3bSMartin Habets #define FR_AB_XX_PRBS_CHK 0x00001340 2123*6e173d3bSMartin Habets #define FRF_AB_XX_REV_LB_EN_LBN 16 2124*6e173d3bSMartin Habets #define FRF_AB_XX_REV_LB_EN_WIDTH 1 2125*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_DEG_DET_LBN 15 2126*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 2127*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 2128*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 2129*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 2130*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 2131*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_ERR_CHK_LBN 12 2132*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 2133*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_DEG_DET_LBN 11 2134*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 2135*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 2136*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 2137*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 2138*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 2139*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_ERR_CHK_LBN 8 2140*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 2141*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_DEG_DET_LBN 7 2142*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 2143*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 2144*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 2145*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 2146*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 2147*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_ERR_CHK_LBN 4 2148*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 2149*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_DEG_DET_LBN 3 2150*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 2151*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 2152*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 2153*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 2154*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 2155*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_ERR_CHK_LBN 0 2156*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 2157*6e173d3bSMartin Habets 2158*6e173d3bSMartin Habets /* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */ 2159*6e173d3bSMartin Habets #define FR_AB_XX_PRBS_ERR 0x00001350 2160*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 2161*6e173d3bSMartin Habets #define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 2162*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 2163*6e173d3bSMartin Habets #define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 2164*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 2165*6e173d3bSMartin Habets #define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 2166*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 2167*6e173d3bSMartin Habets #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 2168*6e173d3bSMartin Habets 2169*6e173d3bSMartin Habets /* XX_CORE_STAT_REG: XAUI XGXS core status register */ 2170*6e173d3bSMartin Habets #define FR_AB_XX_CORE_STAT 0x00001360 2171*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG3_LBN 31 2172*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG3_WIDTH 1 2173*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 2174*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 2175*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG2_LBN 29 2176*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG2_WIDTH 1 2177*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 2178*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 2179*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG1_LBN 27 2180*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG1_WIDTH 1 2181*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 2182*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 2183*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG0_LBN 25 2184*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG0_WIDTH 1 2185*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 2186*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 2187*6e173d3bSMartin Habets #define FRF_AB_XX_XGXS_LB_EN_LBN 23 2188*6e173d3bSMartin Habets #define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 2189*6e173d3bSMartin Habets #define FRF_AB_XX_XGMII_LB_EN_LBN 22 2190*6e173d3bSMartin Habets #define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 2191*6e173d3bSMartin Habets #define FRF_AB_XX_MATCH_FAULT_LBN 21 2192*6e173d3bSMartin Habets #define FRF_AB_XX_MATCH_FAULT_WIDTH 1 2193*6e173d3bSMartin Habets #define FRF_AB_XX_ALIGN_DONE_LBN 20 2194*6e173d3bSMartin Habets #define FRF_AB_XX_ALIGN_DONE_WIDTH 1 2195*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT3_LBN 19 2196*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT3_WIDTH 1 2197*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT2_LBN 18 2198*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT2_WIDTH 1 2199*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT1_LBN 17 2200*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT1_WIDTH 1 2201*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT0_LBN 16 2202*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT0_WIDTH 1 2203*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH3_LBN 15 2204*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 2205*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH2_LBN 14 2206*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 2207*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH1_LBN 13 2208*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 2209*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH0_LBN 12 2210*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 2211*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 2212*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 2213*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 2214*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 2215*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 2216*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 2217*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 2218*6e173d3bSMartin Habets #define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 2219*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 2220*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 2221*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 2222*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 2223*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 2224*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 2225*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 2226*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 2227*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH3_LBN 3 2228*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH3_WIDTH 1 2229*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH2_LBN 2 2230*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH2_WIDTH 1 2231*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH1_LBN 1 2232*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH1_WIDTH 1 2233*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH0_LBN 0 2234*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_CH0_WIDTH 1 2235*6e173d3bSMartin Habets 2236*6e173d3bSMartin Habets /* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */ 2237*6e173d3bSMartin Habets #define FR_AA_RX_DESC_PTR_TBL_KER 0x00011800 2238*6e173d3bSMartin Habets #define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 2239*6e173d3bSMartin Habets #define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 2240*6e173d3bSMartin Habets /* RX_DESC_PTR_TBL: Receive descriptor pointer table */ 2241*6e173d3bSMartin Habets #define FR_BZ_RX_DESC_PTR_TBL 0x00f40000 2242*6e173d3bSMartin Habets #define FR_BZ_RX_DESC_PTR_TBL_STEP 16 2243*6e173d3bSMartin Habets #define FR_BB_RX_DESC_PTR_TBL_ROWS 4096 2244*6e173d3bSMartin Habets #define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 2245*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_LBN 90 2246*6e173d3bSMartin Habets #define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 2247*6e173d3bSMartin Habets #define FRF_AA_RX_RESET_LBN 89 2248*6e173d3bSMartin Habets #define FRF_AA_RX_RESET_WIDTH 1 2249*6e173d3bSMartin Habets #define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 2250*6e173d3bSMartin Habets #define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 2251*6e173d3bSMartin Habets #define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 2252*6e173d3bSMartin Habets #define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 2253*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 2254*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 2255*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_HW_RPTR_LBN 80 2256*6e173d3bSMartin Habets #define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 2257*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 2258*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 2259*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 2260*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 2261*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 2262*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 2263*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 2264*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 2265*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 2266*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 2267*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_LABEL_LBN 5 2268*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 2269*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_SIZE_LBN 3 2270*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 2271*6e173d3bSMartin Habets #define FFE_AZ_RX_DESCQ_SIZE_4K 3 2272*6e173d3bSMartin Habets #define FFE_AZ_RX_DESCQ_SIZE_2K 2 2273*6e173d3bSMartin Habets #define FFE_AZ_RX_DESCQ_SIZE_1K 1 2274*6e173d3bSMartin Habets #define FFE_AZ_RX_DESCQ_SIZE_512 0 2275*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_TYPE_LBN 2 2276*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 2277*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 2278*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 2279*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_EN_LBN 0 2280*6e173d3bSMartin Habets #define FRF_AZ_RX_DESCQ_EN_WIDTH 1 2281*6e173d3bSMartin Habets 2282*6e173d3bSMartin Habets /* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */ 2283*6e173d3bSMartin Habets #define FR_AA_TX_DESC_PTR_TBL_KER 0x00011900 2284*6e173d3bSMartin Habets #define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 2285*6e173d3bSMartin Habets #define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 2286*6e173d3bSMartin Habets /* TX_DESC_PTR_TBL: Transmit descriptor pointer */ 2287*6e173d3bSMartin Habets #define FR_BZ_TX_DESC_PTR_TBL 0x00f50000 2288*6e173d3bSMartin Habets #define FR_BZ_TX_DESC_PTR_TBL_STEP 16 2289*6e173d3bSMartin Habets #define FR_BB_TX_DESC_PTR_TBL_ROWS 4096 2290*6e173d3bSMartin Habets #define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 2291*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 2292*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 2293*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 2294*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 2295*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 2296*6e173d3bSMartin Habets #define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 2297*6e173d3bSMartin Habets #define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 2298*6e173d3bSMartin Habets #define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 2299*6e173d3bSMartin Habets #define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 2300*6e173d3bSMartin Habets #define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 2301*6e173d3bSMartin Habets #define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 2302*6e173d3bSMartin Habets #define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 2303*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_EN_LBN 88 2304*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_EN_WIDTH 1 2305*6e173d3bSMartin Habets #define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 2306*6e173d3bSMartin Habets #define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 2307*6e173d3bSMartin Habets #define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 2308*6e173d3bSMartin Habets #define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 2309*6e173d3bSMartin Habets #define FRF_AZ_TX_DC_HW_RPTR_LBN 80 2310*6e173d3bSMartin Habets #define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 2311*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 2312*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 2313*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 2314*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 2315*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 2316*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 2317*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 2318*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 2319*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 2320*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 2321*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_LABEL_LBN 5 2322*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 2323*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_SIZE_LBN 3 2324*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 2325*6e173d3bSMartin Habets #define FFE_AZ_TX_DESCQ_SIZE_4K 3 2326*6e173d3bSMartin Habets #define FFE_AZ_TX_DESCQ_SIZE_2K 2 2327*6e173d3bSMartin Habets #define FFE_AZ_TX_DESCQ_SIZE_1K 1 2328*6e173d3bSMartin Habets #define FFE_AZ_TX_DESCQ_SIZE_512 0 2329*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_TYPE_LBN 1 2330*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 2331*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 2332*6e173d3bSMartin Habets #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 2333*6e173d3bSMartin Habets 2334*6e173d3bSMartin Habets /* EVQ_PTR_TBL_KER: Event queue pointer table */ 2335*6e173d3bSMartin Habets #define FR_AA_EVQ_PTR_TBL_KER 0x00011a00 2336*6e173d3bSMartin Habets #define FR_AA_EVQ_PTR_TBL_KER_STEP 16 2337*6e173d3bSMartin Habets #define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 2338*6e173d3bSMartin Habets /* EVQ_PTR_TBL: Event queue pointer table */ 2339*6e173d3bSMartin Habets #define FR_BZ_EVQ_PTR_TBL 0x00f60000 2340*6e173d3bSMartin Habets #define FR_BZ_EVQ_PTR_TBL_STEP 16 2341*6e173d3bSMartin Habets #define FR_CZ_EVQ_PTR_TBL_ROWS 1024 2342*6e173d3bSMartin Habets #define FR_BB_EVQ_PTR_TBL_ROWS 4096 2343*6e173d3bSMartin Habets #define FRF_BZ_EVQ_RPTR_IGN_LBN 40 2344*6e173d3bSMartin Habets #define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 2345*6e173d3bSMartin Habets #define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39 2346*6e173d3bSMartin Habets #define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1 2347*6e173d3bSMartin Habets #define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39 2348*6e173d3bSMartin Habets #define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1 2349*6e173d3bSMartin Habets #define FRF_AZ_EVQ_NXT_WPTR_LBN 24 2350*6e173d3bSMartin Habets #define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 2351*6e173d3bSMartin Habets #define FRF_AZ_EVQ_EN_LBN 23 2352*6e173d3bSMartin Habets #define FRF_AZ_EVQ_EN_WIDTH 1 2353*6e173d3bSMartin Habets #define FRF_AZ_EVQ_SIZE_LBN 20 2354*6e173d3bSMartin Habets #define FRF_AZ_EVQ_SIZE_WIDTH 3 2355*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_32K 6 2356*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_16K 5 2357*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_8K 4 2358*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_4K 3 2359*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_2K 2 2360*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_1K 1 2361*6e173d3bSMartin Habets #define FFE_AZ_EVQ_SIZE_512 0 2362*6e173d3bSMartin Habets #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 2363*6e173d3bSMartin Habets #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 2364*6e173d3bSMartin Habets 2365*6e173d3bSMartin Habets /* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */ 2366*6e173d3bSMartin Habets #define FR_AA_BUF_HALF_TBL_KER 0x00018000 2367*6e173d3bSMartin Habets #define FR_AA_BUF_HALF_TBL_KER_STEP 8 2368*6e173d3bSMartin Habets #define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 2369*6e173d3bSMartin Habets /* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */ 2370*6e173d3bSMartin Habets #define FR_BZ_BUF_HALF_TBL 0x00800000 2371*6e173d3bSMartin Habets #define FR_BZ_BUF_HALF_TBL_STEP 8 2372*6e173d3bSMartin Habets #define FR_CZ_BUF_HALF_TBL_ROWS 147456 2373*6e173d3bSMartin Habets #define FR_BB_BUF_HALF_TBL_ROWS 524288 2374*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 2375*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 2376*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 2377*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 2378*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 2379*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 2380*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 2381*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 2382*6e173d3bSMartin Habets 2383*6e173d3bSMartin Habets /* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */ 2384*6e173d3bSMartin Habets #define FR_AA_BUF_FULL_TBL_KER 0x00018000 2385*6e173d3bSMartin Habets #define FR_AA_BUF_FULL_TBL_KER_STEP 8 2386*6e173d3bSMartin Habets #define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 2387*6e173d3bSMartin Habets /* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */ 2388*6e173d3bSMartin Habets #define FR_BZ_BUF_FULL_TBL 0x00800000 2389*6e173d3bSMartin Habets #define FR_BZ_BUF_FULL_TBL_STEP 8 2390*6e173d3bSMartin Habets #define FR_CZ_BUF_FULL_TBL_ROWS 147456 2391*6e173d3bSMartin Habets #define FR_BB_BUF_FULL_TBL_ROWS 917504 2392*6e173d3bSMartin Habets #define FRF_AZ_BUF_FULL_UNUSED_LBN 51 2393*6e173d3bSMartin Habets #define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 2394*6e173d3bSMartin Habets #define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 2395*6e173d3bSMartin Habets #define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 2396*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_REGION_LBN 48 2397*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_REGION_WIDTH 2 2398*6e173d3bSMartin Habets #define FFE_AZ_BUF_ADR_REGN3 3 2399*6e173d3bSMartin Habets #define FFE_AZ_BUF_ADR_REGN2 2 2400*6e173d3bSMartin Habets #define FFE_AZ_BUF_ADR_REGN1 1 2401*6e173d3bSMartin Habets #define FFE_AZ_BUF_ADR_REGN0 0 2402*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_FBUF_LBN 14 2403*6e173d3bSMartin Habets #define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 2404*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 2405*6e173d3bSMartin Habets #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 2406*6e173d3bSMartin Habets 2407*6e173d3bSMartin Habets /* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */ 2408*6e173d3bSMartin Habets #define FR_BZ_RX_FILTER_TBL0 0x00f00000 2409*6e173d3bSMartin Habets #define FR_BZ_RX_FILTER_TBL0_STEP 32 2410*6e173d3bSMartin Habets #define FR_BZ_RX_FILTER_TBL0_ROWS 8192 2411*6e173d3bSMartin Habets /* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */ 2412*6e173d3bSMartin Habets #define FR_BB_RX_FILTER_TBL1 0x00f00010 2413*6e173d3bSMartin Habets #define FR_BB_RX_FILTER_TBL1_STEP 32 2414*6e173d3bSMartin Habets #define FR_BB_RX_FILTER_TBL1_ROWS 8192 2415*6e173d3bSMartin Habets #define FRF_BZ_RSS_EN_LBN 110 2416*6e173d3bSMartin Habets #define FRF_BZ_RSS_EN_WIDTH 1 2417*6e173d3bSMartin Habets #define FRF_BZ_SCATTER_EN_LBN 109 2418*6e173d3bSMartin Habets #define FRF_BZ_SCATTER_EN_WIDTH 1 2419*6e173d3bSMartin Habets #define FRF_BZ_TCP_UDP_LBN 108 2420*6e173d3bSMartin Habets #define FRF_BZ_TCP_UDP_WIDTH 1 2421*6e173d3bSMartin Habets #define FRF_BZ_RXQ_ID_LBN 96 2422*6e173d3bSMartin Habets #define FRF_BZ_RXQ_ID_WIDTH 12 2423*6e173d3bSMartin Habets #define FRF_BZ_DEST_IP_LBN 64 2424*6e173d3bSMartin Habets #define FRF_BZ_DEST_IP_WIDTH 32 2425*6e173d3bSMartin Habets #define FRF_BZ_DEST_PORT_TCP_LBN 48 2426*6e173d3bSMartin Habets #define FRF_BZ_DEST_PORT_TCP_WIDTH 16 2427*6e173d3bSMartin Habets #define FRF_BZ_SRC_IP_LBN 16 2428*6e173d3bSMartin Habets #define FRF_BZ_SRC_IP_WIDTH 32 2429*6e173d3bSMartin Habets #define FRF_BZ_SRC_TCP_DEST_UDP_LBN 0 2430*6e173d3bSMartin Habets #define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 16 2431*6e173d3bSMartin Habets 2432*6e173d3bSMartin Habets /* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */ 2433*6e173d3bSMartin Habets #define FR_CZ_RX_MAC_FILTER_TBL0 0x00f00010 2434*6e173d3bSMartin Habets #define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 2435*6e173d3bSMartin Habets #define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 2436*6e173d3bSMartin Habets #define FRF_CZ_RMFT_RSS_EN_LBN 75 2437*6e173d3bSMartin Habets #define FRF_CZ_RMFT_RSS_EN_WIDTH 1 2438*6e173d3bSMartin Habets #define FRF_CZ_RMFT_SCATTER_EN_LBN 74 2439*6e173d3bSMartin Habets #define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 2440*6e173d3bSMartin Habets #define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 2441*6e173d3bSMartin Habets #define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 2442*6e173d3bSMartin Habets #define FRF_CZ_RMFT_RXQ_ID_LBN 61 2443*6e173d3bSMartin Habets #define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 2444*6e173d3bSMartin Habets #define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 2445*6e173d3bSMartin Habets #define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 2446*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_LBN 12 2447*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 2448*6e173d3bSMartin Habets #define FRF_CZ_RMFT_VLAN_ID_LBN 0 2449*6e173d3bSMartin Habets #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 2450*6e173d3bSMartin Habets 2451*6e173d3bSMartin Habets /* TIMER_TBL: Timer table */ 2452*6e173d3bSMartin Habets #define FR_BZ_TIMER_TBL 0x00f70000 2453*6e173d3bSMartin Habets #define FR_BZ_TIMER_TBL_STEP 16 2454*6e173d3bSMartin Habets #define FR_CZ_TIMER_TBL_ROWS 1024 2455*6e173d3bSMartin Habets #define FR_BB_TIMER_TBL_ROWS 4096 2456*6e173d3bSMartin Habets #define FRF_CZ_TIMER_Q_EN_LBN 33 2457*6e173d3bSMartin Habets #define FRF_CZ_TIMER_Q_EN_WIDTH 1 2458*6e173d3bSMartin Habets #define FRF_CZ_INT_ARMD_LBN 32 2459*6e173d3bSMartin Habets #define FRF_CZ_INT_ARMD_WIDTH 1 2460*6e173d3bSMartin Habets #define FRF_CZ_INT_PEND_LBN 31 2461*6e173d3bSMartin Habets #define FRF_CZ_INT_PEND_WIDTH 1 2462*6e173d3bSMartin Habets #define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 2463*6e173d3bSMartin Habets #define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 2464*6e173d3bSMartin Habets #define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 2465*6e173d3bSMartin Habets #define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 2466*6e173d3bSMartin Habets #define FRF_CZ_TIMER_MODE_LBN 14 2467*6e173d3bSMartin Habets #define FRF_CZ_TIMER_MODE_WIDTH 2 2468*6e173d3bSMartin Habets #define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 2469*6e173d3bSMartin Habets #define FFE_CZ_TIMER_MODE_TRIG_START 2 2470*6e173d3bSMartin Habets #define FFE_CZ_TIMER_MODE_IMMED_START 1 2471*6e173d3bSMartin Habets #define FFE_CZ_TIMER_MODE_DIS 0 2472*6e173d3bSMartin Habets #define FRF_BB_TIMER_MODE_LBN 12 2473*6e173d3bSMartin Habets #define FRF_BB_TIMER_MODE_WIDTH 2 2474*6e173d3bSMartin Habets #define FFE_BB_TIMER_MODE_INT_HLDOFF 2 2475*6e173d3bSMartin Habets #define FFE_BB_TIMER_MODE_TRIG_START 2 2476*6e173d3bSMartin Habets #define FFE_BB_TIMER_MODE_IMMED_START 1 2477*6e173d3bSMartin Habets #define FFE_BB_TIMER_MODE_DIS 0 2478*6e173d3bSMartin Habets #define FRF_CZ_TIMER_VAL_LBN 0 2479*6e173d3bSMartin Habets #define FRF_CZ_TIMER_VAL_WIDTH 14 2480*6e173d3bSMartin Habets #define FRF_BB_TIMER_VAL_LBN 0 2481*6e173d3bSMartin Habets #define FRF_BB_TIMER_VAL_WIDTH 12 2482*6e173d3bSMartin Habets 2483*6e173d3bSMartin Habets /* TX_PACE_TBL: Transmit pacing table */ 2484*6e173d3bSMartin Habets #define FR_BZ_TX_PACE_TBL 0x00f80000 2485*6e173d3bSMartin Habets #define FR_BZ_TX_PACE_TBL_STEP 16 2486*6e173d3bSMartin Habets #define FR_CZ_TX_PACE_TBL_ROWS 1024 2487*6e173d3bSMartin Habets #define FR_BB_TX_PACE_TBL_ROWS 4096 2488*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_LBN 0 2489*6e173d3bSMartin Habets #define FRF_BZ_TX_PACE_WIDTH 5 2490*6e173d3bSMartin Habets 2491*6e173d3bSMartin Habets /* RX_INDIRECTION_TBL: RX Indirection Table */ 2492*6e173d3bSMartin Habets #define FR_BZ_RX_INDIRECTION_TBL 0x00fb0000 2493*6e173d3bSMartin Habets #define FR_BZ_RX_INDIRECTION_TBL_STEP 16 2494*6e173d3bSMartin Habets #define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 2495*6e173d3bSMartin Habets #define FRF_BZ_IT_QUEUE_LBN 0 2496*6e173d3bSMartin Habets #define FRF_BZ_IT_QUEUE_WIDTH 6 2497*6e173d3bSMartin Habets 2498*6e173d3bSMartin Habets /* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */ 2499*6e173d3bSMartin Habets #define FR_CZ_TX_FILTER_TBL0 0x00fc0000 2500*6e173d3bSMartin Habets #define FR_CZ_TX_FILTER_TBL0_STEP 16 2501*6e173d3bSMartin Habets #define FR_CZ_TX_FILTER_TBL0_ROWS 8192 2502*6e173d3bSMartin Habets #define FRF_CZ_TIFT_TCP_UDP_LBN 108 2503*6e173d3bSMartin Habets #define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 2504*6e173d3bSMartin Habets #define FRF_CZ_TIFT_TXQ_ID_LBN 96 2505*6e173d3bSMartin Habets #define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 2506*6e173d3bSMartin Habets #define FRF_CZ_TIFT_DEST_IP_LBN 64 2507*6e173d3bSMartin Habets #define FRF_CZ_TIFT_DEST_IP_WIDTH 32 2508*6e173d3bSMartin Habets #define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 2509*6e173d3bSMartin Habets #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 2510*6e173d3bSMartin Habets #define FRF_CZ_TIFT_SRC_IP_LBN 16 2511*6e173d3bSMartin Habets #define FRF_CZ_TIFT_SRC_IP_WIDTH 32 2512*6e173d3bSMartin Habets #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 2513*6e173d3bSMartin Habets #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 2514*6e173d3bSMartin Habets 2515*6e173d3bSMartin Habets /* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */ 2516*6e173d3bSMartin Habets #define FR_CZ_TX_MAC_FILTER_TBL0 0x00fe0000 2517*6e173d3bSMartin Habets #define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 2518*6e173d3bSMartin Habets #define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 2519*6e173d3bSMartin Habets #define FRF_CZ_TMFT_TXQ_ID_LBN 61 2520*6e173d3bSMartin Habets #define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 2521*6e173d3bSMartin Habets #define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 2522*6e173d3bSMartin Habets #define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 2523*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_LBN 12 2524*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 2525*6e173d3bSMartin Habets #define FRF_CZ_TMFT_VLAN_ID_LBN 0 2526*6e173d3bSMartin Habets #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 2527*6e173d3bSMartin Habets 2528*6e173d3bSMartin Habets /* MC_TREG_SMEM: MC Shared Memory */ 2529*6e173d3bSMartin Habets #define FR_CZ_MC_TREG_SMEM 0x00ff0000 2530*6e173d3bSMartin Habets #define FR_CZ_MC_TREG_SMEM_STEP 4 2531*6e173d3bSMartin Habets #define FR_CZ_MC_TREG_SMEM_ROWS 512 2532*6e173d3bSMartin Habets #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 2533*6e173d3bSMartin Habets #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 2534*6e173d3bSMartin Habets 2535*6e173d3bSMartin Habets /* MSIX_VECTOR_TABLE: MSIX Vector Table */ 2536*6e173d3bSMartin Habets #define FR_BB_MSIX_VECTOR_TABLE 0x00ff0000 2537*6e173d3bSMartin Habets #define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 2538*6e173d3bSMartin Habets #define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 2539*6e173d3bSMartin Habets /* MSIX_VECTOR_TABLE: MSIX Vector Table */ 2540*6e173d3bSMartin Habets #define FR_CZ_MSIX_VECTOR_TABLE 0x00000000 2541*6e173d3bSMartin Habets /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 2542*6e173d3bSMartin Habets #define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 2543*6e173d3bSMartin Habets #define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 2544*6e173d3bSMartin Habets #define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 2545*6e173d3bSMartin Habets #define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 2546*6e173d3bSMartin Habets #define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 2547*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 2548*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 2549*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 2550*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 2551*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 2552*6e173d3bSMartin Habets #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 2553*6e173d3bSMartin Habets 2554*6e173d3bSMartin Habets /* MSIX_PBA_TABLE: MSIX Pending Bit Array */ 2555*6e173d3bSMartin Habets #define FR_BB_MSIX_PBA_TABLE 0x00ff2000 2556*6e173d3bSMartin Habets #define FR_BZ_MSIX_PBA_TABLE_STEP 4 2557*6e173d3bSMartin Habets #define FR_BB_MSIX_PBA_TABLE_ROWS 2 2558*6e173d3bSMartin Habets /* MSIX_PBA_TABLE: MSIX Pending Bit Array */ 2559*6e173d3bSMartin Habets #define FR_CZ_MSIX_PBA_TABLE 0x00008000 2560*6e173d3bSMartin Habets /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 2561*6e173d3bSMartin Habets #define FR_CZ_MSIX_PBA_TABLE_ROWS 32 2562*6e173d3bSMartin Habets #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 2563*6e173d3bSMartin Habets #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 2564*6e173d3bSMartin Habets 2565*6e173d3bSMartin Habets /* SRM_DBG_REG: SRAM debug access */ 2566*6e173d3bSMartin Habets #define FR_BZ_SRM_DBG 0x03000000 2567*6e173d3bSMartin Habets #define FR_BZ_SRM_DBG_STEP 8 2568*6e173d3bSMartin Habets #define FR_CZ_SRM_DBG_ROWS 262144 2569*6e173d3bSMartin Habets #define FR_BB_SRM_DBG_ROWS 2097152 2570*6e173d3bSMartin Habets #define FRF_BZ_SRM_DBG_LBN 0 2571*6e173d3bSMartin Habets #define FRF_BZ_SRM_DBG_WIDTH 64 2572*6e173d3bSMartin Habets 2573*6e173d3bSMartin Habets /* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */ 2574*6e173d3bSMartin Habets #define FR_CZ_TB_MSIX_PBA_TABLE 0x00008000 2575*6e173d3bSMartin Habets #define FR_CZ_TB_MSIX_PBA_TABLE_STEP 4 2576*6e173d3bSMartin Habets #define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024 2577*6e173d3bSMartin Habets #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0 2578*6e173d3bSMartin Habets #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32 2579*6e173d3bSMartin Habets 2580*6e173d3bSMartin Habets /* DRIVER_EV */ 2581*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 2582*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 2583*6e173d3bSMartin Habets #define FSE_BZ_TX_DSC_ERROR_EV 15 2584*6e173d3bSMartin Habets #define FSE_BZ_RX_DSC_ERROR_EV 14 2585*6e173d3bSMartin Habets #define FSE_AA_RX_RECOVER_EV 11 2586*6e173d3bSMartin Habets #define FSE_AZ_TIMER_EV 10 2587*6e173d3bSMartin Habets #define FSE_AZ_TX_PKT_NON_TCP_UDP 9 2588*6e173d3bSMartin Habets #define FSE_AZ_WAKE_UP_EV 6 2589*6e173d3bSMartin Habets #define FSE_AZ_SRM_UPD_DONE_EV 5 2590*6e173d3bSMartin Habets #define FSE_AB_EVQ_NOT_EN_EV 3 2591*6e173d3bSMartin Habets #define FSE_AZ_EVQ_INIT_DONE_EV 2 2592*6e173d3bSMartin Habets #define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 2593*6e173d3bSMartin Habets #define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 2594*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 2595*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 2596*6e173d3bSMartin Habets 2597*6e173d3bSMartin Habets /* EVENT_ENTRY */ 2598*6e173d3bSMartin Habets #define FSF_AZ_EV_CODE_LBN 60 2599*6e173d3bSMartin Habets #define FSF_AZ_EV_CODE_WIDTH 4 2600*6e173d3bSMartin Habets #define FSE_CZ_EV_CODE_MCDI_EV 12 2601*6e173d3bSMartin Habets #define FSE_CZ_EV_CODE_USER_EV 8 2602*6e173d3bSMartin Habets #define FSE_AZ_EV_CODE_DRV_GEN_EV 7 2603*6e173d3bSMartin Habets #define FSE_AZ_EV_CODE_GLOBAL_EV 6 2604*6e173d3bSMartin Habets #define FSE_AZ_EV_CODE_DRIVER_EV 5 2605*6e173d3bSMartin Habets #define FSE_AZ_EV_CODE_TX_EV 2 2606*6e173d3bSMartin Habets #define FSE_AZ_EV_CODE_RX_EV 0 2607*6e173d3bSMartin Habets #define FSF_AZ_EV_DATA_LBN 0 2608*6e173d3bSMartin Habets #define FSF_AZ_EV_DATA_WIDTH 60 2609*6e173d3bSMartin Habets 2610*6e173d3bSMartin Habets /* GLOBAL_EV */ 2611*6e173d3bSMartin Habets #define FSF_BB_GLB_EV_RX_RECOVERY_LBN 12 2612*6e173d3bSMartin Habets #define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1 2613*6e173d3bSMartin Habets #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 11 2614*6e173d3bSMartin Habets #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 2615*6e173d3bSMartin Habets #define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11 2616*6e173d3bSMartin Habets #define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1 2617*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10 2618*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1 2619*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9 2620*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1 2621*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7 2622*6e173d3bSMartin Habets #define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1 2623*6e173d3bSMartin Habets 2624*6e173d3bSMartin Habets /* LEGACY_INT_VEC */ 2625*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 2626*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 2627*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_INT_Q_LBN 40 2628*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 2629*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 2630*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 2631*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 2632*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 2633*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 2634*6e173d3bSMartin Habets #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 2635*6e173d3bSMartin Habets 2636*6e173d3bSMartin Habets /* MC_XGMAC_FLTR_RULE_DEF */ 2637*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_MODE_LBN 416 2638*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_MODE_WIDTH 1 2639*6e173d3bSMartin Habets #define FSE_CZ_MC_XFRC_MODE_LAYERED 1 2640*6e173d3bSMartin Habets #define FSE_CZ_MC_XFRC_MODE_SIMPLE 0 2641*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_HASH_LBN 384 2642*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_HASH_WIDTH 32 2643*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256 2644*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128 2645*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128 2646*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128 2647*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0 2648*6e173d3bSMartin Habets #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128 2649*6e173d3bSMartin Habets 2650*6e173d3bSMartin Habets /* RX_EV */ 2651*6e173d3bSMartin Habets #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 2652*6e173d3bSMartin Habets #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 2653*6e173d3bSMartin Habets #define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 2654*6e173d3bSMartin Habets #define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 2655*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PKT_OK_LBN 56 2656*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 2657*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 2658*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 2659*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 2660*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 2661*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 2662*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 2663*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 2664*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 2665*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 2666*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 2667*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 2668*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 2669*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 2670*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 2671*6e173d3bSMartin Habets #define FSF_AA_RX_EV_DRIB_NIB_LBN 49 2672*6e173d3bSMartin Habets #define FSF_AA_RX_EV_DRIB_NIB_WIDTH 1 2673*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 2674*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 2675*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 2676*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 2677*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 2678*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 2679*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 2680*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 2681*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 2682*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 2683*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 2684*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 2685*6e173d3bSMartin Habets #define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 2686*6e173d3bSMartin Habets #define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2 2687*6e173d3bSMartin Habets #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 2688*6e173d3bSMartin Habets #define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1 2689*6e173d3bSMartin Habets #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 2690*6e173d3bSMartin Habets #define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0 2691*6e173d3bSMartin Habets #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 2692*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 2693*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 2694*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 2695*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 2696*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 2697*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 2698*6e173d3bSMartin Habets #define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 2699*6e173d3bSMartin Habets #define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 2700*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_Q_LABEL_LBN 32 2701*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 2702*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 2703*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 2704*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PORT_LBN 30 2705*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_PORT_WIDTH 1 2706*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 2707*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 2708*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_SOP_LBN 15 2709*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_SOP_WIDTH 1 2710*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 2711*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 2712*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 2713*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 2714*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 2715*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 2716*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_DESC_PTR_LBN 0 2717*6e173d3bSMartin Habets #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 2718*6e173d3bSMartin Habets 2719*6e173d3bSMartin Habets /* RX_KER_DESC */ 2720*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 2721*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 2722*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_REGION_LBN 46 2723*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 2724*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 2725*6e173d3bSMartin Habets #define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 2726*6e173d3bSMartin Habets 2727*6e173d3bSMartin Habets /* RX_USER_DESC */ 2728*6e173d3bSMartin Habets #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 2729*6e173d3bSMartin Habets #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 2730*6e173d3bSMartin Habets #define FSF_AZ_RX_USER_BUF_ID_LBN 0 2731*6e173d3bSMartin Habets #define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 2732*6e173d3bSMartin Habets 2733*6e173d3bSMartin Habets /* TX_EV */ 2734*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PKT_ERR_LBN 38 2735*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 2736*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 2737*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 2738*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_Q_LABEL_LBN 32 2739*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 2740*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PORT_LBN 16 2741*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_PORT_WIDTH 1 2742*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 2743*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 2744*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 2745*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 2746*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_COMP_LBN 12 2747*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_COMP_WIDTH 1 2748*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_DESC_PTR_LBN 0 2749*6e173d3bSMartin Habets #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 2750*6e173d3bSMartin Habets 2751*6e173d3bSMartin Habets /* TX_KER_DESC */ 2752*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_CONT_LBN 62 2753*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_CONT_WIDTH 1 2754*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 2755*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 2756*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BUF_REGION_LBN 46 2757*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 2758*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 2759*6e173d3bSMartin Habets #define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 2760*6e173d3bSMartin Habets 2761*6e173d3bSMartin Habets /* TX_USER_DESC */ 2762*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 2763*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 2764*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_CONT_LBN 46 2765*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_CONT_WIDTH 1 2766*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 2767*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 2768*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BUF_ID_LBN 13 2769*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 2770*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 2771*6e173d3bSMartin Habets #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 2772*6e173d3bSMartin Habets 2773*6e173d3bSMartin Habets /* USER_EV */ 2774*6e173d3bSMartin Habets #define FSF_CZ_USER_QID_LBN 32 2775*6e173d3bSMartin Habets #define FSF_CZ_USER_QID_WIDTH 10 2776*6e173d3bSMartin Habets #define FSF_CZ_USER_EV_REG_VALUE_LBN 0 2777*6e173d3bSMartin Habets #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 2778*6e173d3bSMartin Habets 2779*6e173d3bSMartin Habets /************************************************************************** 2780*6e173d3bSMartin Habets * 2781*6e173d3bSMartin Habets * Falcon B0 PCIe core indirect registers 2782*6e173d3bSMartin Habets * 2783*6e173d3bSMartin Habets ************************************************************************** 2784*6e173d3bSMartin Habets */ 2785*6e173d3bSMartin Habets 2786*6e173d3bSMartin Habets #define FPCR_BB_PCIE_DEVICE_CTRL_STAT 0x68 2787*6e173d3bSMartin Habets 2788*6e173d3bSMartin Habets #define FPCR_BB_PCIE_LINK_CTRL_STAT 0x70 2789*6e173d3bSMartin Habets 2790*6e173d3bSMartin Habets #define FPCR_BB_ACK_RPL_TIMER 0x700 2791*6e173d3bSMartin Habets #define FPCRF_BB_ACK_TL_LBN 0 2792*6e173d3bSMartin Habets #define FPCRF_BB_ACK_TL_WIDTH 16 2793*6e173d3bSMartin Habets #define FPCRF_BB_RPL_TL_LBN 16 2794*6e173d3bSMartin Habets #define FPCRF_BB_RPL_TL_WIDTH 16 2795*6e173d3bSMartin Habets 2796*6e173d3bSMartin Habets #define FPCR_BB_ACK_FREQ 0x70C 2797*6e173d3bSMartin Habets #define FPCRF_BB_ACK_FREQ_LBN 0 2798*6e173d3bSMartin Habets #define FPCRF_BB_ACK_FREQ_WIDTH 7 2799*6e173d3bSMartin Habets 2800*6e173d3bSMartin Habets /************************************************************************** 2801*6e173d3bSMartin Habets * 2802*6e173d3bSMartin Habets * Pseudo-registers and fields 2803*6e173d3bSMartin Habets * 2804*6e173d3bSMartin Habets ************************************************************************** 2805*6e173d3bSMartin Habets */ 2806*6e173d3bSMartin Habets 2807*6e173d3bSMartin Habets /* Interrupt acknowledge work-around register (A0/A1 only) */ 2808*6e173d3bSMartin Habets #define FR_AA_WORK_AROUND_BROKEN_PCI_READS 0x0070 2809*6e173d3bSMartin Habets 2810*6e173d3bSMartin Habets /* EE_SPI_HCMD_REG: SPI host command register */ 2811*6e173d3bSMartin Habets /* Values for the EE_SPI_HCMD_SF_SEL register field */ 2812*6e173d3bSMartin Habets #define FFE_AB_SPI_DEVICE_EEPROM 0 2813*6e173d3bSMartin Habets #define FFE_AB_SPI_DEVICE_FLASH 1 2814*6e173d3bSMartin Habets 2815*6e173d3bSMartin Habets /* NIC_STAT_REG: NIC status register */ 2816*6e173d3bSMartin Habets #define FRF_AB_STRAP_10G_LBN 2 2817*6e173d3bSMartin Habets #define FRF_AB_STRAP_10G_WIDTH 1 2818*6e173d3bSMartin Habets #define FRF_AA_STRAP_PCIE_LBN 0 2819*6e173d3bSMartin Habets #define FRF_AA_STRAP_PCIE_WIDTH 1 2820*6e173d3bSMartin Habets 2821*6e173d3bSMartin Habets /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */ 2822*6e173d3bSMartin Habets #define FRF_AZ_FATAL_INTR_LBN 0 2823*6e173d3bSMartin Habets #define FRF_AZ_FATAL_INTR_WIDTH 12 2824*6e173d3bSMartin Habets 2825*6e173d3bSMartin Habets /* SRM_CFG_REG: SRAM configuration register */ 2826*6e173d3bSMartin Habets /* We treat the number of SRAM banks and bank size as a single field */ 2827*6e173d3bSMartin Habets #define FRF_AZ_SRM_NB_SZ_LBN FRF_AZ_SRM_BANK_SIZE_LBN 2828*6e173d3bSMartin Habets #define FRF_AZ_SRM_NB_SZ_WIDTH \ 2829*6e173d3bSMartin Habets (FRF_AZ_SRM_BANK_SIZE_WIDTH + FRF_AZ_SRM_NUM_BANK_WIDTH) 2830*6e173d3bSMartin Habets #define FFE_AB_SRM_NB1_SZ2M 0 2831*6e173d3bSMartin Habets #define FFE_AB_SRM_NB1_SZ4M 1 2832*6e173d3bSMartin Habets #define FFE_AB_SRM_NB1_SZ8M 2 2833*6e173d3bSMartin Habets #define FFE_AB_SRM_NB_SZ_DEF 3 2834*6e173d3bSMartin Habets #define FFE_AB_SRM_NB2_SZ4M 4 2835*6e173d3bSMartin Habets #define FFE_AB_SRM_NB2_SZ8M 5 2836*6e173d3bSMartin Habets #define FFE_AB_SRM_NB2_SZ16M 6 2837*6e173d3bSMartin Habets #define FFE_AB_SRM_NB_SZ_RES 7 2838*6e173d3bSMartin Habets 2839*6e173d3bSMartin Habets /* RX_DESC_UPD_REGP0: Receive descriptor update register. */ 2840*6e173d3bSMartin Habets /* We write just the last dword of these registers */ 2841*6e173d3bSMartin Habets #define FR_AZ_RX_DESC_UPD_DWORD_P0 \ 2842*6e173d3bSMartin Habets (BUILD_BUG_ON_ZERO(FR_AA_RX_DESC_UPD_KER != FR_BZ_RX_DESC_UPD_P0) + \ 2843*6e173d3bSMartin Habets FR_BZ_RX_DESC_UPD_P0 + 3 * 4) 2844*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32) 2845*6e173d3bSMartin Habets #define FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH FRF_AZ_RX_DESC_WPTR_WIDTH 2846*6e173d3bSMartin Habets 2847*6e173d3bSMartin Habets /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */ 2848*6e173d3bSMartin Habets #define FR_AZ_TX_DESC_UPD_DWORD_P0 \ 2849*6e173d3bSMartin Habets (BUILD_BUG_ON_ZERO(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0) + \ 2850*6e173d3bSMartin Habets FR_BZ_TX_DESC_UPD_P0 + 3 * 4) 2851*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32) 2852*6e173d3bSMartin Habets #define FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH FRF_AZ_TX_DESC_WPTR_WIDTH 2853*6e173d3bSMartin Habets 2854*6e173d3bSMartin Habets /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */ 2855*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN 12 2856*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH 1 2857*6e173d3bSMartin Habets 2858*6e173d3bSMartin Habets /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */ 2859*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN 12 2860*6e173d3bSMartin Habets #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 2861*6e173d3bSMartin Habets 2862*6e173d3bSMartin Habets /* XM_TX_PARAM_REG: XGMAC transmit parameter register */ 2863*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_LBN FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 2864*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH + \ 2865*6e173d3bSMartin Habets FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH) 2866*6e173d3bSMartin Habets 2867*6e173d3bSMartin Habets /* XM_RX_PARAM_REG: XGMAC receive parameter register */ 2868*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_LBN FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 2869*6e173d3bSMartin Habets #define FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH + \ 2870*6e173d3bSMartin Habets FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH) 2871*6e173d3bSMartin Habets 2872*6e173d3bSMartin Habets /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */ 2873*6e173d3bSMartin Habets /* Default values */ 2874*6e173d3bSMartin Habets #define FFE_AB_XX_TXDRV_DEQ_DEF 0xe /* deq=.6 */ 2875*6e173d3bSMartin Habets #define FFE_AB_XX_TXDRV_DTX_DEF 0x5 /* 1.25 */ 2876*6e173d3bSMartin Habets #define FFE_AB_XX_SD_CTL_DRV_DEF 0 /* 20mA */ 2877*6e173d3bSMartin Habets 2878*6e173d3bSMartin Habets /* XX_CORE_STAT_REG: XAUI XGXS core status register */ 2879*6e173d3bSMartin Habets /* XGXS all-lanes status fields */ 2880*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT_LBN FRF_AB_XX_SYNC_STAT0_LBN 2881*6e173d3bSMartin Habets #define FRF_AB_XX_SYNC_STAT_WIDTH 4 2882*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_LBN FRF_AB_XX_COMMA_DET_CH0_LBN 2883*6e173d3bSMartin Habets #define FRF_AB_XX_COMMA_DET_WIDTH 4 2884*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_LBN FRF_AB_XX_CHAR_ERR_CH0_LBN 2885*6e173d3bSMartin Habets #define FRF_AB_XX_CHAR_ERR_WIDTH 4 2886*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_LBN FRF_AB_XX_DISPERR_CH0_LBN 2887*6e173d3bSMartin Habets #define FRF_AB_XX_DISPERR_WIDTH 4 2888*6e173d3bSMartin Habets #define FFE_AB_XX_STAT_ALL_LANES 0xf 2889*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG_LBN FRF_AB_XX_FORCE_SIG0_VAL_LBN 2890*6e173d3bSMartin Habets #define FRF_AB_XX_FORCE_SIG_WIDTH 8 2891*6e173d3bSMartin Habets #define FFE_AB_XX_FORCE_SIG_ALL_LANES 0xff 2892*6e173d3bSMartin Habets 2893*6e173d3bSMartin Habets /* RX_MAC_FILTER_TBL0 */ 2894*6e173d3bSMartin Habets /* RMFT_DEST_MAC is wider than 32 bits */ 2895*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_LO_LBN FRF_CZ_RMFT_DEST_MAC_LBN 2896*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_LO_WIDTH 32 2897*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_HI_LBN (FRF_CZ_RMFT_DEST_MAC_LBN + 32) 2898*6e173d3bSMartin Habets #define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH (FRF_CZ_RMFT_DEST_MAC_WIDTH - 32) 2899*6e173d3bSMartin Habets 2900*6e173d3bSMartin Habets /* TX_MAC_FILTER_TBL0 */ 2901*6e173d3bSMartin Habets /* TMFT_SRC_MAC is wider than 32 bits */ 2902*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_LO_LBN FRF_CZ_TMFT_SRC_MAC_LBN 2903*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_LO_WIDTH 32 2904*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_HI_LBN (FRF_CZ_TMFT_SRC_MAC_LBN + 32) 2905*6e173d3bSMartin Habets #define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH (FRF_CZ_TMFT_SRC_MAC_WIDTH - 32) 2906*6e173d3bSMartin Habets 2907*6e173d3bSMartin Habets /* TX_PACE_TBL */ 2908*6e173d3bSMartin Habets /* Values >20 are documented as reserved, but will result in a queue going 2909*6e173d3bSMartin Habets * into the fast bin with a pace value of zero. */ 2910*6e173d3bSMartin Habets #define FFE_BZ_TX_PACE_OFF 0 2911*6e173d3bSMartin Habets #define FFE_BZ_TX_PACE_RESERVED 21 2912*6e173d3bSMartin Habets 2913*6e173d3bSMartin Habets /* DRIVER_EV */ 2914*6e173d3bSMartin Habets /* Sub-fields of an RX flush completion event */ 2915*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 2916*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 2917*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 2918*6e173d3bSMartin Habets #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 2919*6e173d3bSMartin Habets 2920*6e173d3bSMartin Habets /* EVENT_ENTRY */ 2921*6e173d3bSMartin Habets /* Magic number field for event test */ 2922*6e173d3bSMartin Habets #define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0 2923*6e173d3bSMartin Habets #define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32 2924*6e173d3bSMartin Habets 2925*6e173d3bSMartin Habets /* RX packet prefix */ 2926*6e173d3bSMartin Habets #define FS_BZ_RX_PREFIX_HASH_OFST 12 2927*6e173d3bSMartin Habets #define FS_BZ_RX_PREFIX_SIZE 16 2928*6e173d3bSMartin Habets 2929*6e173d3bSMartin Habets #endif /* EFX_FARCH_REGS_H */ 2930