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/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DSPARCV9.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
44 defaultMaxPageSize = 0x100000; in SPARCV9()
45 defaultImageBase = 0x100000; in SPARCV9()
105 write32be(loc, (read32be(loc) & ~0x3fffffff) | ((val >> 2) & 0x3fffffff)); in relocate()
110 write32be(loc, (read32be(loc) & ~0x003fffff) | (val & 0x003fffff)); in relocate()
116 write32be(loc, (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff)); in relocate()
121 write32be(loc, (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff)); in relocate()
126 write32be(loc, (read32be(loc) & ~0x0007ffff) | ((val >> 2) & 0x0007ffff)); in relocate()
131 write32be(loc, (read32be(loc) & ~0x000003ff) | (val & 0x000003ff)); in relocate()
135 write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff)); in relocate()
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/et/
H A Dif_etreg.h57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
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H A Dif_etvar.h74 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
83 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF
85 #define ET_TDCTRL2_LAST_FRAG 0x00000001
86 #define ET_TDCTRL2_FIRST_FRAG 0x00000002
87 #define ET_TDCTRL2_INTR 0x00000004
88 #define ET_TDCTRL2_CTRL_WORD 0x00000008
89 #define ET_TDCTRL2_HDX_BACKP 0x00000010
90 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020
91 #define ET_TDCTRL2_FRAME_ERR 0x00000040
92 #define ET_TDCTRL2_NO_CRC 0x00000080
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
36 #define AR_CR_RXD 0x00000020 // Receive disable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
[all …]
/freebsd/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
[all...]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/freebsd/libexec/mknetid/
H A Dhash.h50 #define HASH_MASK 0x000003FF
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfman_common.h40 #define NIA_ORDER_RESTOR 0x00800000
41 #define NIA_ENG_FM_CTL 0x00000000
42 #define NIA_ENG_PRS 0x00440000
43 #define NIA_ENG_KG 0x00480000
44 #define NIA_ENG_PLCR 0x004C0000
45 #define NIA_ENG_BMI 0x00500000
46 #define NIA_ENG_QMI_ENQ 0x00540000
47 #define NIA_ENG_QMI_DEQ 0x00580000
48 #define NIA_ENG_MASK 0x007C0000
50 #define NIA_FM_CTL_AC_CC 0x00000006
[all …]
/freebsd/sys/powerpc/powermac/
H A Data_macio.c58 #define ATA_MACIO_ALTOFFSET 0x160
68 #define USE_DBDMA_IRQ 0
73 #define ATA_MACIO_TIMINGREG 0x200
89 { 600, 180 }, /* PIO 0 */
97 { 480, 240 }, /* WDMA 0 */
103 { 120, 180 }, /* UDMA 0 */
160 if (strcmp(type, "ata") != 0 && in ata_macio_probe()
161 strcmp(type, "ide") != 0) in ata_macio_probe()
167 if (strcmp(name,"ata-4") == 0) { in ata_macio_probe()
192 rid = 0; in ata_macio_attach()
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_axi_reg.h53 /* [0x0] */
56 /* [0x8] */
58 /* [0xc] */
60 /* [0x10] */
62 /* [0x14] */
64 /* [0x18] */
66 /* [0x1c] */
68 /* [0x20] */
70 /* [0x24] */
72 /* [0x28] */
[all …]
H A Dal_hal_udma_regs_s2m.h59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
63 /* [0x8] Descriptor read master configuration */
65 /* [0xc] Descriptor read master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Completion descriptors write master configuration */
77 /* [0x24] AXI outstanding read configuration */
[all …]
/freebsd/contrib/llvm-project/libunwind/include/mach-o/
H A Dcompact_unwind_encoding.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
45 UNWIND_IS_NOT_FUNCTION_START = 0x80000000,
46 UNWIND_HAS_LSDA = 0x40000000,
47 UNWIND_PERSONALITY_MASK = 0x30000000,
60 // 4-bits: 0=old, 1=ebp based, 2=stack-imm, 3=stack-ind, 4=DWARF
71 UNWIND_X86_MODE_MASK = 0x0F000000,
72 UNWIND_X86_MODE_EBP_FRAME = 0x01000000,
73 UNWIND_X86_MODE_STACK_IMMD = 0x02000000,
74 UNWIND_X86_MODE_STACK_IND = 0x03000000,
75 UNWIND_X86_MODE_DWARF = 0x0400000
[all...]
/freebsd/sys/dev/safe/
H A Dsafereg.h37 #define BS_BAR 0x10 /* DMA base address register */
38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
[all …]
/freebsd/sys/dev/sfxge/common/
H A Dsiena_nic.c60 if (req.emr_rc != 0) { in siena_nic_get_partn_mask()
72 return (0); in siena_nic_get_partn_mask()
104 &capabilities, mac_addr)) != 0) in siena_board_cfg()
167 if (rc != 0) { in siena_board_cfg()
188 encp->enc_fw_assisted_tso_v2_n_contexts = 0; in siena_board_cfg()
205 encp->enc_filter_action_mark_max = 0; in siena_board_cfg()
207 return (0); in siena_board_cfg()
227 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) in siena_phy_cfg()
236 return (0); in siena_phy_cfg()
244 #define SIENA_BIU_MAGIC0 0x01234567
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_targ.h125 CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */
129 #define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01)
130 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80)
131 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0)
133 #define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80)
135 #define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF)
136 #define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */
149 U16 Reserved2; /* 0Ch */
150 U16 IOCStatus; /* 0Eh */
165 U8 PriorityReason; /* 0Ch */
[all …]
/freebsd/contrib/expat/lib/
H A Dnametab.h34 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
35 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
36 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x04000000,
37 0x87FFFFFE, 0x07FFFFFE, 0x00000000, 0x00000000, 0xFF7FFFFF, 0xFF7FFFFF,
38 0xFFFFFFFF, 0x7FF3FFFF, 0xFFFFFDFE, 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
39 0xFFFFE00F, 0xFC31FFFF, 0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF,
40 0xFFFFFFFF, 0xF80001FF, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0xFFFFD740, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD,
42 0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, 0xFFFF0003, 0xFFFFFFFF,
43 0xFFFF199F, 0x033FCFFF, 0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE,
[all …]

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