Lines Matching +full:0 +full:x000003ff
74 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
83 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF
85 #define ET_TDCTRL2_LAST_FRAG 0x00000001
86 #define ET_TDCTRL2_FIRST_FRAG 0x00000002
87 #define ET_TDCTRL2_INTR 0x00000004
88 #define ET_TDCTRL2_CTRL_WORD 0x00000008
89 #define ET_TDCTRL2_HDX_BACKP 0x00000010
90 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020
91 #define ET_TDCTRL2_FRAME_ERR 0x00000040
92 #define ET_TDCTRL2_NO_CRC 0x00000080
93 #define ET_TDCTRL2_MAC_OVRRD 0x00000100
94 #define ET_TDCTRL2_PAD_PACKET 0x00000200
95 #define ET_TDCTRL2_JUMBO_PACKET 0x00000400
96 #define ET_TDCTRL2_INS_VLAN 0x00000800
97 #define ET_TDCTRL2_CSUM_IP 0x00001000
98 #define ET_TDCTRL2_CSUM_TCP 0x00002000
99 #define ET_TDCTRL2_CSUM_UDP 0x00004000
107 #define ET_RDCTRL_BUFIDX_MASK 0x000003FF
114 #define ET_RXST_INFO1_HASH_PASS 0x00000001
115 #define ET_RXST_INFO1_IPCSUM 0x00000002
116 #define ET_RXST_INFO1_IPCSUM_OK 0x00000004
117 #define ET_RXST_INFO1_TCPCSUM 0x00000008
118 #define ET_RXST_INFO1_TCPCSUM_OK 0x00000010
119 #define ET_RXST_INFO1_WOL 0x00000020
120 #define ET_RXST_INFO1_RXMAC_ERR 0x00000040
121 #define ET_RXST_INFO1_DROP 0x00000080
122 #define ET_RXST_INFO1_FRAME_TRUNC 0x00000100
123 #define ET_RXST_INFO1_JUMBO 0x00000200
124 #define ET_RXST_INFO1_VLAN 0x00000400
125 #define ET_RXST_INFO1_PREV_FRMAE_DROP 0x00010000
126 #define ET_RXST_INFO1_SHORT 0x00020000
127 #define ET_RXST_INFO1_BAD_CARRIER 0x00040000
128 #define ET_RXST_INFO1_CODE_ERR 0x00080000
129 #define ET_RXST_INFO1_CRC_ERR 0x00100000
130 #define ET_RXST_INFO1_LEN_MISMATCH 0x00200000
131 #define ET_RXST_INFO1_TOO_LONG 0x00400000
132 #define ET_RXST_INFO1_OK 0x00800000
133 #define ET_RXST_INFO1_MULTICAST 0x01000000
134 #define ET_RXST_INFO1_BROADCAST 0x02000000
135 #define ET_RXST_INFO1_DRIBBLE 0x04000000
136 #define ET_RXST_INFO1_CTL_FRAME 0x08000000
137 #define ET_RXST_INFO1_PAUSE_FRAME 0x10000000
138 #define ET_RXST_INFO1_UNKWN_CTL_FRAME 0x20000000
139 #define ET_RXST_INFO1_VLAN_TAG 0x40000000
140 #define ET_RXST_INFO1_LONG_EVENT 0x80000000
142 #define ET_RXST_INFO2_LEN_MASK 0x0000FFFF
143 #define ET_RXST_INFO2_LEN_SHIFT 0
144 #define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000
146 #define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000
154 #define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000
156 #define ET_RXS_STATRING_WRAP 0x10000000
341 #define ET_FLAG_PCIE 0x0001
342 #define ET_FLAG_MSI 0x0002
343 #define ET_FLAG_FASTETHER 0x0004
344 #define ET_FLAG_TXRX_ENABLED 0x0100
345 #define ET_FLAG_JUMBO 0x0200
346 #define ET_FLAG_LINK 0x8000