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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
30 "#address-cells":
[all …]
/freebsd/sys/dev/sfxge/common/
H A Dsiena_nic.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
60 if (req.emr_rc != 0) { in siena_nic_get_partn_mask()
72 return (0); in siena_nic_get_partn_mask()
88 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_board_cfg()
97 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; in siena_board_cfg()
99 /* External port identifier using one-based port numbering */ in siena_board_cfg()
100 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port; in siena_board_cfg()
104 &capabilities, mac_addr)) != 0) in siena_board_cfg()
[all …]
H A Dsiena_flash.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * - parsed by MC boot ROM and firmware
42 * - reserved (but not parsed) by PHY firmware
43 * - opaque to driver
46 #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20)
48 #define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */
49 #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */
51 #define SIENA_MC_BOOT_HDR_LEN (0x200)
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/freebsd/sys/x86/include/
H A Dapicreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * Pentium P54C+ Built-in APIC
39 * Base Address of Built-in APIC in memory location
40 * is 0xfee00000.
55 * 0A0 Processor Priority Register R
56 * 0B0 EOI Register W
57 * 0C0 RRR Remote read R
58 * 0D0 Logical Destination R/W
59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W
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/freebsd/sys/arm/arm/
H A Ddisassem.c3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
71 * 2 - print Operand 2 of a data processing instruction
72 * d - destination register (bits 12-15)
73 * n - n register (bits 16-19)
74 * s - s register (bits 8-11)
75 * o - indirect register rn (bits 16-19) (used by swap)
76 * m - m register (bits 0-3)
77 * a - address operand of ldr/str instruction
78 * l - register list for ldm/stm instruction
[all …]
/freebsd/sys/dev/isci/
H A Disci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
59 uint32_t g_isci_debug_level = 0;
75 { 0, 0 }
84 DRIVER_MODULE(isci, pci, isci_pci_driver, 0,
[all...]
/freebsd/sys/dev/bxe/
H A D57712_init_values.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
H A D57711_init_values.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
H A D57710_init_values.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_log_sas.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors.
37 * ------------ *
40 *-------------------------------------------------------------------------*
46 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
47 #define SAS_LOGINFO_MASK 0xFFFF0000
50 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
52 /* Bits 31-28: MPI_IOCLOGINFO_TYPE_SAS (3) */
53 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
[all …]
H A Dmpi.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors.
40 * ---------------
43 * -------- -------- ------------------------------------------------------
44 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
45 * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition.
46 * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR.
47 * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions.
50 * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition.
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/freebsd/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-sparcv9.pl2 # Copyright 2016-2021 The OpenSSL Project Authors. All Rights Reserved.
31 # (*) Comparison to compiler-generated code is really problematic,
34 # improvement on T4 for gcc-4.6. Well, in T4 case it's a bit
37 # (**) Pre-III performance should be even worse; floating-point
38 # performance for UltraSPARC I-IV on the other hand is reported
39 # to be 4.25 for hand-coded assembly, but they are just too old
41 # (***) Multi-process benchmark saturates at ~12.5x single-process
42 # result on 8-core processor, or ~21GBps per 2.85GHz socket.
45 my $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
49 my ($ctx,$inp,$len,$padbit,$shl,$shr) = map("%i$_",(0..5));
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/freebsd/sys/dev/mpi3mr/mpi/
H A Dmpi30_transport.h2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved.
5 * Support: <fbsd-storage-driver.pdl@broadcom.com>
42 * ---------------
45 * -------- ----------- ------------------------------------------------------
46 * 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H.
47 * 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I.
48 * 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J.
49 * 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L.
50 * 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
41 if (MI->isCompare()) in lowerRILow()
43 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
44 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
47 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2400.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2014 by Qlogic, Inc.
33 0x0401f1be, 0x00112000, 0x00100000, 0x0000c79b,
34 0x00000008, 0x00000007, 0x00000000, 0x00009496,
35 0x00000003, 0x00000000, 0x20434f50, 0x59524947,
36 0x48542032, 0x30313720, 0x514c4f47, 0x49432043,
37 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
38 0x32347878, 0x20466972, 0x6d776172, 0x65202020,
39 0x56657273, 0x696f6e20, 0x2020382e, 0x30372e30,
[all …]
H A Dasm_2800.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2023 by Qlogic, Inc.
38 0x0501f078, 0x00124000, 0x00100000, 0x00017380,
39 0x00000009, 0x0000000c, 0x00000001, 0x785ad0d5,
40 0x00000080, 0x0001f626, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323320, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32387878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
[all …]
H A Dasm_2700.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2022 by Qlogic, Inc.
38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
[all …]
H A Dasm_2500.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2019 by Qlogic, Inc.
38 0x0501f06b, 0x00115000, 0x00100000, 0x0000c8ea,
39 0x00000008, 0x00000008, 0x000000cf, 0x00109095,
40 0x00000004, 0x00000000, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32357878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
[all …]
H A Dasm_2600.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2019 by Qlogic, Inc.
38 0x0501f06c, 0x0011b000, 0x00100000, 0x00011c0f,
39 0x00000008, 0x00000008, 0x000000e7, 0x0078d0d5,
40 0x00000020, 0x00000006, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x38337878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/Port/
H A Dfm_port.h2 * Copyright 2008-2012 Freescale Semiconductor Inc.
63 #define BMI_PORT_REGS_OFFSET 0
64 #define QMI_PORT_REGS_OFFSET 0x400
65 #define PRS_PORT_REGS_OFFSET 0x800
75 #define DEFAULT_PORT_deqByteCnt_10G 0x1400
76 #define DEFAULT_PORT_deqByteCnt_1G 0x400
82 #define DEFAULT_PORT_cheksumLastBytesIgnore 0
97 #define DEFAULT_PORT_BufMargins_endMargins 0
107 #define DEFAULT_notSupported 0xff
113 #define DEFAULT_PORT_txFifoMinFillLevel 0
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
16 0x83000000, 0x00000000, 0x4000000
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/freebsd/sys/netinet/
H A Din.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
40 #define IPPROTO_IP 0 /* dummy for IP */
45 #define INADDR_ANY ((in_addr_t)0x00000000)
46 #define INADDR_BROADCAST ((in_addr_t)0xffffffff) /* must be masked */
139 #define IPPROTO_HOPOPTS 0 /* IP6 hop-by-hop options */
159 #define IPPROTO_TRUNK1 23 /* Trunk-1 */
160 #define IPPROTO_TRUNK2 24 /* Trunk-2 */
161 #define IPPROTO_LEAF1 25 /* Leaf-1 */
162 #define IPPROTO_LEAF2 26 /* Leaf-2 */
[all …]
/freebsd/sys/dev/mpr/mpi/
H A Dmpi2.h1 /*-
2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
12 * 3. Neither the name of the author nor the names of any co-contributors
28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
32 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
45 * with MPI v2.0 products. Unless otherwise noted, names beginning with
46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
49 * ---------------
52 * -------- -------- ------------------------------------------------------
53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
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/freebsd/sys/dev/mps/mpi/
H A Dmpi2.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2015 LSI Corp.
5 * Copyright (c) 2013-2015 Avago Technologies
29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
33 * Copyright (c) 2006-2015 LSI Corporation.
34 * Copyright (c) 2013-2015 Avago Technologies
46 * ---------------
49 * -------- -------- ------------------------------------------------------
50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
[all …]
/freebsd/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
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