Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
1 /*-
2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
12 * 3. Neither the name of the author nor the names of any co-contributors
28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
32 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
45 * with MPI v2.0 products. Unless otherwise noted, names beginning with
46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
49 * ---------------
52 * -------- -------- ------------------------------------------------------
53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
54 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
55 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
56 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Moved ReplyPostHostIndex register to offset 0x6C of the
62 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
66 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
67 * Removed the MPI-defined Fault Codes and extended the
68 * product specific codes up to 0xEFFF.
70 * and changed the flush value to 0x0.
75 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
83 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
92 * Added MSI-x index mask and shift for Reply Post Host
95 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
97 * Added defines for product-specific range of message
98 * function codes, 0xF0 to 0xFF.
99 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
101 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
102 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
106 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
107 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
108 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
109 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
111 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
112 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
116 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
120 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
121 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
123 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
124 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
125 * 11-18-14 02.00.36 Updated copyright information.
127 * 03-16-15 02.00.37 Updated for MPI v2.6.
134 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
135 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT
136 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
138 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
139 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
140 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
145 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
146 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
147 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
148 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT.
149 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
150 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT.
151 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT.
152 * 07-22-18 02.00.51 Added SECURE_BOOT define.
154 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT.
155 * --------------------------------------------------------------------------
167 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
169 #define MPI2_VERSION_MINOR_MASK (0x00FF)
170 #define MPI2_VERSION_MINOR_SHIFT (0)
173 #define MPI2_VERSION_MAJOR (0x02)
175 /* minor version for MPI v2.0 compatible products */
176 #define MPI2_VERSION_MINOR (0x00)
179 #define MPI2_VERSION_02_00 (0x0200)
182 #define MPI25_VERSION_MINOR (0x05)
185 #define MPI2_VERSION_02_05 (0x0205)
188 #define MPI26_VERSION_MINOR (0x06)
191 #define MPI2_VERSION_02_06 (0x0206)
194 #define MPI2_HEADER_VERSION_UNIT (0x34)
195 #define MPI2_HEADER_VERSION_DEV (0x00)
196 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
198 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
199 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
208 #define MPI2_IOC_STATE_RESET (0x00000000)
209 #define MPI2_IOC_STATE_READY (0x10000000)
210 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
211 #define MPI2_IOC_STATE_FAULT (0x40000000)
213 #define MPI2_IOC_STATE_MASK (0xF0000000)
217 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
218 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
228 U32 Doorbell; /* 0x00 */
229 U32 WriteSequence; /* 0x04 */
230 U32 HostDiagnostic; /* 0x08 */
231 U32 Reserved1; /* 0x0C */
232 U32 DiagRWData; /* 0x10 */
233 U32 DiagRWAddressLow; /* 0x14 */
234 U32 DiagRWAddressHigh; /* 0x18 */
235 U32 Reserved2[5]; /* 0x1C */
236 U32 HostInterruptStatus; /* 0x30 */
237 U32 HostInterruptMask; /* 0x34 */
238 U32 DCRData; /* 0x38 */
239 U32 DCRAddress; /* 0x3C */
240 U32 Reserved3[2]; /* 0x40 */
241 U32 ReplyFreeHostIndex; /* 0x48 */
242 U32 Reserved4[8]; /* 0x4C */
243 U32 ReplyPostHostIndex; /* 0x6C */
244 U32 Reserved5; /* 0x70 */
245 U32 HCBSize; /* 0x74 */
246 U32 HCBAddressLow; /* 0x78 */
247 U32 HCBAddressHigh; /* 0x7C */
248 U32 Reserved6[12]; /* 0x80 */
249 U32 Scratchpad[4]; /* 0xB0 */
250 U32 RequestDescriptorPostLow; /* 0xC0 */
251 U32 RequestDescriptorPostHigh; /* 0xC4 */
252 …U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier vers…
253 U32 Reserved7[13]; /* 0xCC */
260 #define MPI2_DOORBELL_OFFSET (0x00000000)
262 /* IOC --> System values */
263 #define MPI2_DOORBELL_USED (0x08000000)
264 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
266 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
267 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
269 /* System --> IOC values */
270 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
272 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
278 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
279 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
280 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
281 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
282 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
283 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
284 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
285 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
286 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
291 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
293 #define MPI26_DIAG_SECURE_BOOT (0x80000000)
295 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
297 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
298 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
302 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
303 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
304 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
305 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
307 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
308 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
309 #define MPI2_DIAG_HCB_MODE (0x00000100)
310 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
311 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
312 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
313 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
314 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
315 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
320 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
321 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
322 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
327 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
328 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
330 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
331 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
332 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
338 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
339 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
340 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
342 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
348 #define MPI2_DCR_DATA_OFFSET (0x00000038)
349 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
354 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
359 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
360 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
361 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
363 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
368 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
369 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
370 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
372 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
373 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
378 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
379 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
380 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
381 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
386 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
387 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
388 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
406 U8 RequestFlags; /* 0x00 */
407 U8 MSIxIndex; /* 0x01 */
408 U16 SMID; /* 0x02 */
409 U16 LMID; /* 0x04 */
410 U16 DescriptorTypeDependent; /* 0x06 */
416 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
417 …ESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */
418 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
419 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
420 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
421 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
422 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
423 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
424 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
426 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
431 U8 RequestFlags; /* 0x00 */
432 U8 MSIxIndex; /* 0x01 */
433 U16 SMID; /* 0x02 */
434 U16 LMID; /* 0x04 */
435 U16 Reserved1; /* 0x06 */
444 U8 RequestFlags; /* 0x00 */
445 U8 MSIxIndex; /* 0x01 */
446 U16 SMID; /* 0x02 */
447 U16 LMID; /* 0x04 */
448 U16 DevHandle; /* 0x06 */
456 U8 RequestFlags; /* 0x00 */
457 U8 MSIxIndex; /* 0x01 */
458 U16 SMID; /* 0x02 */
459 U16 LMID; /* 0x04 */
460 U16 IoIndex; /* 0x06 */
469 U8 RequestFlags; /* 0x00 */
470 U8 MSIxIndex; /* 0x01 */
471 U16 SMID; /* 0x02 */
472 U16 LMID; /* 0x04 */
473 U16 Reserved; /* 0x06 */
524 U8 RequestFlags; /* 0x00 */
525 U8 MSIxIndex; /* 0x01 */
526 U16 SMID; /* 0x02 */
538 U8 ReplyFlags; /* 0x00 */
539 U8 MSIxIndex; /* 0x01 */
540 U16 DescriptorTypeDependent1; /* 0x02 */
541 U32 DescriptorTypeDependent2; /* 0x04 */
546 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
547 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
548 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
549 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
550 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
551 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
552 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
553 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
554 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
557 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
558 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
563 U8 ReplyFlags; /* 0x00 */
564 U8 MSIxIndex; /* 0x01 */
565 U16 SMID; /* 0x02 */
566 U32 ReplyFrameAddress; /* 0x04 */
570 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
575 U8 ReplyFlags; /* 0x00 */
576 U8 MSIxIndex; /* 0x01 */
577 U16 SMID; /* 0x02 */
578 U16 TaskTag; /* 0x04 */
579 U16 Reserved1; /* 0x06 */
588 U8 ReplyFlags; /* 0x00 */
589 U8 MSIxIndex; /* 0x01 */
590 U16 SMID; /* 0x02 */
591 U8 SequenceNumber; /* 0x04 */
592 U8 Reserved1; /* 0x05 */
593 U16 IoIndex; /* 0x06 */
602 U8 ReplyFlags; /* 0x00 */
603 U8 MSIxIndex; /* 0x01 */
604 U8 VP_ID; /* 0x02 */
605 U8 Flags; /* 0x03 */
606 U16 InitiatorDevHandle; /* 0x04 */
607 U16 IoIndex; /* 0x06 */
614 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
619 U8 ReplyFlags; /* 0x00 */
620 U8 MSIxIndex; /* 0x01 */
621 U16 SMID; /* 0x02 */
622 U32 Reserved; /* 0x04 */
663 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
664 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
665 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
666 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
667 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
668 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
669 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
670 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
671 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
672 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
673 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
674 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
675 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
676 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
677 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
678 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
679 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
680 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
681 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
682 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.…
683 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.…
684 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
685 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
686 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
687 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
688 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
689 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
690 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
691 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
692 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
693 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */
694 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
695 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
698 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
699 #define MPI2_FUNCTION_HANDSHAKE (0x42)
708 #define MPI2_IOCSTATUS_MASK (0x7FFF)
714 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
715 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
716 #define MPI2_IOCSTATUS_BUSY (0x0002)
717 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
718 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
719 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
720 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
721 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
722 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
723 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
724 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */
730 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
731 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
732 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
733 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
734 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
735 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
741 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
742 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
743 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
744 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
745 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
746 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
747 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
748 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
749 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
750 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
751 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
752 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
755 * For use by SCSI Initiator and SCSI Target end-to-end data protection
758 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
759 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
760 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
766 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
767 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
768 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
769 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
770 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
771 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
772 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
773 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
774 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
775 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
781 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
782 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
788 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
794 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
800 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
806 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
808 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
809 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
810 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
811 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
812 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
813 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
827 U16 FunctionDependent1; /* 0x00 */
828 U8 ChainOffset; /* 0x02 */
829 U8 Function; /* 0x03 */
830 U16 FunctionDependent2; /* 0x04 */
831 U8 FunctionDependent3; /* 0x06 */
832 U8 MsgFlags; /* 0x07 */
833 U8 VP_ID; /* 0x08 */
834 U8 VF_ID; /* 0x09 */
835 U16 Reserved1; /* 0x0A */
845 U16 FunctionDependent1; /* 0x00 */
846 U8 MsgLength; /* 0x02 */
847 U8 Function; /* 0x03 */
848 U16 FunctionDependent2; /* 0x04 */
849 U8 FunctionDependent3; /* 0x06 */
850 U8 MsgFlags; /* 0x07 */
851 U8 VP_ID; /* 0x08 */
852 U8 VF_ID; /* 0x09 */
853 U16 Reserved1; /* 0x0A */
854 U16 FunctionDependent5; /* 0x0C */
855 U16 IOCStatus; /* 0x0E */
856 U32 IOCLogInfo; /* 0x10 */
864 U8 Dev; /* 0x00 */
865 U8 Unit; /* 0x01 */
866 U8 Minor; /* 0x02 */
867 U8 Major; /* 0x03 */
877 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
878 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
879 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
880 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
881 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
882 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
886 * Fusion-MPT MPI Scatter Gather Elements
920 * MPI Chain Element structures - for MPI v2.0 products only
955 * MPI Transaction Context Element structures - for MPI v2.0 products only
1020 * MPI SGE union for IO SGL's - for MPI v2.0 products only
1034 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1068 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1069 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1070 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1071 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1072 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1073 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1074 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1078 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1079 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1083 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */
1084 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1085 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */
1086 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1090 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1094 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1095 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1102 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1103 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1107 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1108 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1109 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1110 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1112 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1127 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1128 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1129 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
1131 /* CAUTION - The following are READ-MODIFY-WRITE! */
1132 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1133 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1139 * Fusion-MPT IEEE Scatter Gather Elements
1147 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1176 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1179 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1204 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1232 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1233 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1237 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1241 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1242 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1246 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1247 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1248 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1249 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1253 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1254 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element …
1255 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1256 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1257 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element …
1258 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1261 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */
1274 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1275 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1276 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_…
1278 /* CAUTION - The following are READ-MODIFY-WRITE! */
1279 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1280 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1284 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1311 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1312 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1313 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1314 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */
1315 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */
1316 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */
1318 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1319 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1320 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1321 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)