Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2016 Solarflare Communications Inc.
60 if (req.emr_rc != 0) { in siena_nic_get_partn_mask()
72 return (0); in siena_nic_get_partn_mask()
88 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_board_cfg()
97 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; in siena_board_cfg()
99 /* External port identifier using one-based port numbering */ in siena_board_cfg()
100 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port; in siena_board_cfg()
104 &capabilities, mac_addr)) != 0) in siena_board_cfg()
107 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); in siena_board_cfg()
109 encp->enc_board_type = board_type; in siena_board_cfg()
116 encp->enc_hw_pf_count = 1; in siena_board_cfg()
119 encp->enc_clk_mult = 1; in siena_board_cfg()
121 enp->en_features |= EFX_FEATURE_TURBO; in siena_board_cfg()
125 encp->enc_clk_mult = 2; in siena_board_cfg()
129 encp->enc_evq_timer_quantum_ns = in siena_board_cfg()
130 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult; in siena_board_cfg()
131 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in siena_board_cfg()
135 encp->enc_rx_prefix_size = 16; in siena_board_cfg()
138 encp->enc_rx_buf_align_start = 1; in siena_board_cfg()
139 encp->enc_rx_buf_align_end = 1; in siena_board_cfg()
142 encp->enc_rx_push_align = 1; in siena_board_cfg()
146 encp->enc_rx_scale_max_exclusive_contexts = 1; in siena_board_cfg()
148 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR); in siena_board_cfg()
149 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ); in siena_board_cfg()
155 encp->enc_rx_scale_l4_hash_supported = B_TRUE; in siena_board_cfg()
158 encp->enc_rx_scale_additional_modes_supported = B_FALSE; in siena_board_cfg()
161 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); in siena_board_cfg()
163 encp->enc_tx_dma_desc_boundary = 4096; in siena_board_cfg()
167 if (rc != 0) { in siena_board_cfg()
175 encp->enc_evq_limit = nevq; in siena_board_cfg()
176 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq); in siena_board_cfg()
177 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq); in siena_board_cfg()
179 encp->enc_txq_max_ndescs = 4096; in siena_board_cfg()
181 encp->enc_buftbl_limit = SIENA_SRAM_ROWS - in siena_board_cfg()
182 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) - in siena_board_cfg()
183 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); in siena_board_cfg()
185 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; in siena_board_cfg()
186 encp->enc_fw_assisted_tso_enabled = B_FALSE; in siena_board_cfg()
187 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE; in siena_board_cfg()
188 encp->enc_fw_assisted_tso_v2_n_contexts = 0; in siena_board_cfg()
189 encp->enc_allow_set_mac_with_installed_filters = B_TRUE; in siena_board_cfg()
190 encp->enc_rx_packed_stream_supported = B_FALSE; in siena_board_cfg()
191 encp->enc_rx_var_packed_stream_supported = B_FALSE; in siena_board_cfg()
192 encp->enc_rx_es_super_buffer_supported = B_FALSE; in siena_board_cfg()
193 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE; in siena_board_cfg()
196 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000; in siena_board_cfg()
197 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2; in siena_board_cfg()
199 encp->enc_nvram_update_verify_result_supported = B_FALSE; in siena_board_cfg()
201 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS; in siena_board_cfg()
203 encp->enc_filter_action_flag_supported = B_FALSE; in siena_board_cfg()
204 encp->enc_filter_action_mark_supported = B_FALSE; in siena_board_cfg()
205 encp->enc_filter_action_mark_max = 0; in siena_board_cfg()
207 return (0); in siena_board_cfg()
222 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_phy_cfg()
226 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ in siena_phy_cfg()
227 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) in siena_phy_cfg()
232 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask, in siena_phy_cfg()
233 NULL, &encp->enc_phy_stat_mask, NULL); in siena_phy_cfg()
236 return (0); in siena_phy_cfg()
244 #define SIENA_BIU_MAGIC0 0x01234567
245 #define SIENA_BIU_MAGIC1 0xfedcba98
255 * Write magic values to scratch registers 0 and 1, then in siena_nic_biu_test()
261 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); in siena_nic_biu_test()
266 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); in siena_nic_biu_test()
284 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); in siena_nic_biu_test()
289 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); in siena_nic_biu_test()
301 return (0); in siena_nic_biu_test()
319 efx_port_t *epp = &(enp->en_port); in siena_nic_probe()
320 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_nic_probe()
326 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); in siena_nic_probe()
329 if ((rc = siena_nic_biu_test(enp)) != 0) in siena_nic_probe()
334 FRF_AZ_ADR_REGION0, 0, in siena_nic_probe()
341 if ((rc = efx_mcdi_read_assertion(enp)) != 0) in siena_nic_probe()
345 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) in siena_nic_probe()
349 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0) in siena_nic_probe()
352 if ((rc = siena_board_cfg(enp)) != 0) in siena_nic_probe()
355 if ((rc = siena_phy_cfg(enp)) != 0) in siena_nic_probe()
359 if ((rc = siena_nic_reset(enp)) != 0) in siena_nic_probe()
361 if ((rc = siena_phy_get_link(enp, &sls)) != 0) in siena_nic_probe()
363 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask; in siena_nic_probe()
364 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; in siena_nic_probe()
367 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0) in siena_nic_probe()
369 enp->en_u.siena.enu_partn_mask = mask; in siena_nic_probe()
374 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0) in siena_nic_probe()
379 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0) in siena_nic_probe()
384 if ((rc = mcdi_mon_cfg_build(enp)) != 0) in siena_nic_probe()
388 encp->enc_features = enp->en_features; in siena_nic_probe()
390 return (0); in siena_nic_probe()
435 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); in siena_nic_reset()
438 if ((rc = efx_mcdi_read_assertion(enp)) != 0) in siena_nic_reset()
440 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) in siena_nic_reset()
447 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0); in siena_nic_reset()
451 req.emr_in_length = 0; in siena_nic_reset()
453 req.emr_out_length = 0; in siena_nic_reset()
457 if (req.emr_rc != 0) { in siena_nic_reset()
462 return (0); in siena_nic_reset()
471 return (0); in siena_nic_reset()
490 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0); in siena_nic_rx_cfg()
510 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); in siena_nic_init()
513 if ((rc = efx_mcdi_log_ctrl(enp)) != 0) in siena_nic_init()
525 if ((rc = siena_phy_reconfigure(enp)) != 0) in siena_nic_init()
528 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1; in siena_nic_init()
530 return (0); in siena_nic_init()
560 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
561 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
562 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
563 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
564 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
565 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
566 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
567 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
568 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
569 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
570 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
571 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
572 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
576 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
577 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
578 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
579 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
580 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
581 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
582 0x00000003, 0x00000000, 0x00000000, 0x00000000,
583 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
584 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
585 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
586 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
587 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
588 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
608 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
609 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
610 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
611 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
612 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
613 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
614 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
629 while (count > 0) { in siena_nic_test_registers()
631 EFSYS_ASSERT(rsp->rows == 1); in siena_nic_test_registers()
634 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original, in siena_nic_test_registers()
636 for (bit = 0; bit < 128; bit++) { in siena_nic_test_registers()
638 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit)) in siena_nic_test_registers()
643 EFX_AND_OWORD(reg, rsp->mask); in siena_nic_test_registers()
646 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, in siena_nic_test_registers()
648 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, in siena_nic_test_registers()
651 EFX_AND_OWORD(buf, rsp->mask); in siena_nic_test_registers()
658 EFX_OR_OWORD(reg, rsp->mask); in siena_nic_test_registers()
661 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, in siena_nic_test_registers()
663 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, in siena_nic_test_registers()
666 EFX_AND_OWORD(buf, rsp->mask); in siena_nic_test_registers()
674 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, in siena_nic_test_registers()
677 --count; in siena_nic_test_registers()
681 return (0); in siena_nic_test_registers()
689 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); in siena_nic_test_registers()
711 while (count > 0) { in siena_nic_test_tables()
713 address = rsp->address; in siena_nic_test_tables()
714 for (index = 0; index < rsp->rows; ++index) { in siena_nic_test_tables()
715 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); in siena_nic_test_tables()
717 EFX_AND_OWORD(reg, rsp->mask); in siena_nic_test_tables()
718 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE); in siena_nic_test_tables()
720 address += rsp->step; in siena_nic_test_tables()
724 address = rsp->address; in siena_nic_test_tables()
725 for (index = 0; index < rsp->rows; ++index) { in siena_nic_test_tables()
726 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); in siena_nic_test_tables()
728 EFX_AND_OWORD(reg, rsp->mask); in siena_nic_test_tables()
729 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE); in siena_nic_test_tables()
735 address += rsp->step; in siena_nic_test_tables()
739 --count; in siena_nic_test_tables()
742 return (0); in siena_nic_test_tables()
766 for (count = 0; count < nitems; ++count) { in siena_nic_register_test()
768 rsp->mask.eo_u32[0] = *dwordp++; in siena_nic_register_test()
769 rsp->mask.eo_u32[1] = *dwordp++; in siena_nic_register_test()
770 rsp->mask.eo_u32[2] = *dwordp++; in siena_nic_register_test()
771 rsp->mask.eo_u32[3] = *dwordp++; in siena_nic_register_test()
780 for (count = 0; count < nitems; ++count) { in siena_nic_register_test()
782 rsp->mask.eo_u32[0] = *dwordp++; in siena_nic_register_test()
783 rsp->mask.eo_u32[1] = *dwordp++; in siena_nic_register_test()
784 rsp->mask.eo_u32[2] = *dwordp++; in siena_nic_register_test()
785 rsp->mask.eo_u32[3] = *dwordp++; in siena_nic_register_test()
789 EFX_ARRAY_SIZE(__siena_registers))) != 0) in siena_nic_register_test()
794 EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
799 EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
803 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0) in siena_nic_register_test()
806 return (0); in siena_nic_register_test()