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/linux/drivers/gpu/drm/xe/
H A Dxe_gt.c1 // SPDX-License-Identifier: MIT
70 struct xe_gt *gt = arg; in gt_fini() local
72 destroy_workqueue(gt->ordered_wq); in gt_fini()
77 struct xe_gt *gt; in xe_gt_alloc() local
80 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); in xe_gt_alloc()
81 if (!gt) in xe_gt_alloc()
82 return ERR_PTR(-ENOMEM); in xe_gt_alloc()
84 gt->tile = tile; in xe_gt_alloc()
85 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", in xe_gt_alloc()
88 err = drmm_add_action_or_reset(&gt_to_xe(gt)->drm, gt_fini, gt); in xe_gt_alloc()
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H A Dxe_gt_sriov_pf_control.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
53 ret = xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_vf_control_cmd()
54 return ret > 0 ? -EPROTO : ret; in guc_action_vf_control_cmd()
57 static int pf_send_vf_control_cmd(struct xe_gt *gt, unsigned int vfid, u32 cmd) in pf_send_vf_control_cmd() argument
61 xe_gt_assert(gt, vfid != PFID); in pf_send_vf_control_cmd()
62 xe_gt_sriov_dbg_verbose(gt, "sending VF%u control command %s\n", in pf_send_vf_control_cmd()
65 err = guc_action_vf_control_cmd(&gt->uc.guc, vfid, cmd); in pf_send_vf_control_cmd()
67 xe_gt_sriov_err(gt, "VF%u control command %s failed (%pe)\n", in pf_send_vf_control_cmd()
72 static int pf_send_vf_pause(struct xe_gt *gt, unsigned int vfid) in pf_send_vf_pause() argument
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H A Dxe_gt_sriov_pf_config.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
56 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_update_vf_cfg()
62 static int pf_send_vf_cfg_reset(struct xe_gt *gt, u32 vfid) in pf_send_vf_cfg_reset() argument
64 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_cfg_reset()
69 return ret <= 0 ? ret : -EPROTO; in pf_send_vf_cfg_reset()
76 static int pf_send_vf_buf_klvs(struct xe_gt *gt, u32 vfid, struct xe_guc_buf buf, u32 num_dwords) in pf_send_vf_buf_klvs() argument
78 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_buf_klvs()
84 * Return: 0 on success, -ENOKEY if some KLVs were not updated, -EPROTO if reply was malformed,
87 static int pf_push_vf_buf_klvs(struct xe_gt *gt, unsigned int vfid, u32 num_klvs, in pf_push_vf_buf_klvs() argument
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H A Dxe_gt.h1 /* SPDX-License-Identifier: MIT */
9 #include <linux/fault-inject.h>
18 for ((id__) = 0; (id__) < ARRAY_SIZE((gt__)->hw_engines); (id__)++) \
19 for_each_if(((hwe__) = (gt__)->hw_engines + (id__)) && \
22 #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0) argument
31 int xe_gt_init_early(struct xe_gt *gt);
32 int xe_gt_init(struct xe_gt *gt);
33 void xe_gt_mmio_init(struct xe_gt *gt);
34 void xe_gt_declare_wedged(struct xe_gt *gt);
35 int xe_gt_record_default_lrcs(struct xe_gt *gt);
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H A Dxe_gt_idle.c1 // SPDX-License-Identifier: MIT
21 * DOC: Xe GT Idle
23 * Contains functions that init GT idle features like C6
25 * device/gt#/gtidle/name - name of the state
26 * device/gt#/gtidle/idle_residency_ms - Provides residency of the idle state in ms
27 * device/gt#/gtidle/idle_status - Provides current idle state
32 struct kobject *kobj = &dev->kobj; in dev_to_gtidle()
34 return &kobj_to_gt(kobj->parent)->gtidle; in dev_to_gtidle()
44 return &gtidle_to_gt(gtidle)->uc.guc.pc; in gtidle_to_pc()
51 struct xe_gt *gt = container_of(guc, struct xe_gt, uc.guc); in pc_to_xe() local
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H A Dxe_gt_ccs_mode.c1 // SPDX-License-Identifier: MIT
17 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) in __xe_gt_apply_ccs_mode() argument
20 int num_slices = hweight32(CCS_MASK(gt)); in __xe_gt_apply_ccs_mode()
21 struct xe_device *xe = gt_to_xe(gt); in __xe_gt_apply_ccs_mode()
25 xe_assert(xe, xe_gt_ccs_mode_enabled(gt)); in __xe_gt_apply_ccs_mode()
48 for (width = num_slices / num_engines; width; width--) { in __xe_gt_apply_ccs_mode()
52 for_each_hw_engine(hwe, gt, id) { in __xe_gt_apply_ccs_mode()
53 if (hwe->class != XE_ENGINE_CLASS_COMPUTE) in __xe_gt_apply_ccs_mode()
56 if (hwe->logical_instance >= num_engines) in __xe_gt_apply_ccs_mode()
59 config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0; in __xe_gt_apply_ccs_mode()
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H A Dxe_gt_sriov_pf_service.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
125 regs = ERR_PTR(-ENOPKG); in pick_runtime_regs()
132 static int pf_alloc_runtime_info(struct xe_gt *gt) in pf_alloc_runtime_info() argument
134 struct xe_device *xe = gt_to_xe(gt); in pf_alloc_runtime_info()
139 xe_gt_assert(gt, IS_SRIOV_PF(xe)); in pf_alloc_runtime_info()
140 xe_gt_assert(gt, !gt->sriov.pf.service.runtime.size); in pf_alloc_runtime_info()
141 xe_gt_assert(gt, !gt->sriov.pf.service.runtime.regs); in pf_alloc_runtime_info()
142 xe_gt_assert(gt, !gt->sriov.pf.service.runtime.values); in pf_alloc_runtime_info()
151 values = drmm_kcalloc(&xe->drm, size, sizeof(u32), GFP_KERNEL); in pf_alloc_runtime_info()
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H A Dxe_gt_sriov_pf_monitor.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
17 * xe_gt_sriov_pf_monitor_flr - Cleanup VF data after VF FLR.
18 * @gt: the &xe_gt
24 void xe_gt_sriov_pf_monitor_flr(struct xe_gt *gt, u32 vfid) in xe_gt_sriov_pf_monitor_flr() argument
28 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in xe_gt_sriov_pf_monitor_flr()
29 xe_gt_sriov_pf_assert_vfid(gt, vfid); in xe_gt_sriov_pf_monitor_flr()
32 gt->sriov.pf.vfs[vfid].monitor.guc.events[e] = 0; in xe_gt_sriov_pf_monitor_flr()
35 static void pf_update_event_counter(struct xe_gt *gt, u32 vfid, in pf_update_event_counter() argument
38 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in pf_update_event_counter()
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H A Dxe_force_wake.c1 // SPDX-License-Identifier: MIT
27 fw->initialized_domains |= BIT(id); in mark_domain_initialized()
34 struct xe_force_wake_domain *domain = &fw->domains[id]; in init_domain()
36 domain->id = id; in init_domain()
37 domain->reg_ctl = reg; in init_domain()
38 domain->reg_ack = ack; in init_domain()
39 domain->val = FORCEWAKE_MT(FORCEWAKE_KERNEL); in init_domain()
40 domain->mask = FORCEWAKE_MT_MASK(FORCEWAKE_KERNEL); in init_domain()
45 void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw) in xe_force_wake_init_gt() argument
47 struct xe_device *xe = gt_to_xe(gt); in xe_force_wake_init_gt()
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H A Dxe_gt_sriov_pf_debugfs.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
29 * ├── gt0 # d_inode->i_private = gt
30 * │   ├── pf # d_inode->i_private = gt
31 * │   ├── vf1 # d_inode->i_private = VFID(1)
33 * │   ├── vfN # d_inode->i_private = VFID(N)
38 return d->d_inode->i_private; in extract_priv()
43 return extract_priv(d->d_parent); in extract_gt()
137 struct xe_gt *gt = extract_gt(data); \
138 struct xe_device *xe = gt_to_xe(gt); \
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H A Dxe_guc.c1 // SPDX-License-Identifier: MIT
59 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); in guc_bo_ggtt_addr()
64 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); in guc_bo_ggtt_addr()
71 u32 level = xe_guc_log_get_level(&guc->log); in guc_ctl_debug_flags()
87 if (!xe->info.skip_guc_pc) in guc_ctl_feature_flags()
90 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) in guc_ctl_feature_flags()
98 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; in guc_ctl_log_params_flags()
128 FIELD_PREP(GUC_LOG_CRASH, CRASH_BUFFER_SIZE / LOG_UNIT - 1) | in guc_ctl_log_params_flags()
129 FIELD_PREP(GUC_LOG_DEBUG, DEBUG_BUFFER_SIZE / LOG_UNIT - 1) | in guc_ctl_log_params_flags()
130 FIELD_PREP(GUC_LOG_CAPTURE, CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) | in guc_ctl_log_params_flags()
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H A Dxe_gsc_proxy.c1 // SPDX-License-Identifier: MIT
32 * is integrated in GT, the graphics driver needs to transfer the messages from
38 * 1 - Xe submits a request to GSC asking for the message to CSME
39 * 2 - GSC replies with the proxy header + payload for CSME
40 * 3 - Xe sends the reply from GSC as-is to CSME via the mei proxy component
41 * 4 - CSME replies with the proxy header + payload for GSC
42 * 5 - Xe submits a request to GSC with the reply from CSME
43 * 6 - GSC replies either with a new header + payload (same as step 2, so we
68 struct xe_gt *gt = gsc_to_gt(gsc); in xe_gsc_proxy_init_done() local
69 u32 fwsts1 = xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)); in xe_gsc_proxy_init_done()
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/linux/drivers/gpu/drm/i915/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
9 # Enable -Werror in CI and development
10 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
14 subdir-ccflags-y += -DI915
16 subdir-ccflags-y += -I$(src)
21 i915-y += \
52 i915-y += \
58 i915-y += \
66 i915-$(CONFIG_COMPAT) += \
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt.h1 /* SPDX-License-Identifier: MIT */
17 * Check that the GT is a graphics GT and has an IP version within the
20 #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ argument
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
28 * Check that the GT is a media GT and has an IP version within the
34 #define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \ argument
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
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H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
18 __igt_reset_stolen(struct intel_gt *gt, in __igt_reset_stolen() argument
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
34 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
43 return -ENOMEM; in __igt_reset_stolen()
47 err = -ENOMEM; in __igt_reset_stolen()
51 igt_global_reset_lock(gt); in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
54 err = igt_spinner_init(&spin, gt); in __igt_reset_stolen()
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H A Dintel_gt_pm_irq.c1 // SPDX-License-Identifier: MIT
13 static void write_pm_imr(struct intel_gt *gt) in write_pm_imr() argument
15 struct drm_i915_private *i915 = gt->i915; in write_pm_imr()
16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr()
17 u32 mask = gt->pm_imr; in write_pm_imr()
32 static void gen6_gt_pm_update_irq(struct intel_gt *gt, in gen6_gt_pm_update_irq() argument
40 lockdep_assert_held(gt->irq_lock); in gen6_gt_pm_update_irq()
42 new_val = gt->pm_imr; in gen6_gt_pm_update_irq()
46 if (new_val != gt->pm_imr) { in gen6_gt_pm_update_irq()
47 gt->pm_imr = new_val; in gen6_gt_pm_update_irq()
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H A Dintel_gt_sysfs.c1 // SPDX-License-Identifier: MIT
23 return !strncmp(kobj->name, "gt", 2); in is_object_gt()
31 * has been called, whether it's called from gt/ or from in intel_gt_sysfs_get_drvdata()
35 * If the interface is called from gt/ then private data is in intel_gt_sysfs_get_drvdata()
49 static struct kobject *gt_get_parent_obj(struct intel_gt *gt) in gt_get_parent_obj() argument
51 return &gt->i915->drm.primary->kdev->kobj; in gt_get_parent_obj()
58 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name); in id_show() local
60 return sysfs_emit(buf, "%u\n", gt->info.id); in id_show()
81 void intel_gt_sysfs_register(struct intel_gt *gt) in intel_gt_sysfs_register() argument
88 * We generate the files only for gt 0 in intel_gt_sysfs_register()
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H A Dintel_gt_clock_utils.c1 // SPDX-License-Identifier: MIT
81 freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); in gen11_read_clock_frequency()
95 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
102 freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg); in gen9_read_clock_frequency()
135 * -> 63:32 increments every 1024 ns in g4x_read_clock_frequency()
151 return DIV_ROUND_CLOSEST(intel_fsb_freq(uncore->i915), 4) * 1000; in gen4_read_clock_frequency()
156 if (GRAPHICS_VER(uncore->i915) >= 11) in read_clock_frequency()
158 else if (GRAPHICS_VER(uncore->i915) >= 9) in read_clock_frequency()
160 else if (GRAPHICS_VER(uncore->i915) >= 6) in read_clock_frequency()
162 else if (GRAPHICS_VER(uncore->i915) == 5) in read_clock_frequency()
[all …]
H A Dselftest_gt_pm.c1 // SPDX-License-Identifier: MIT
20 return -1; in cmp_u64()
32 return -1; in cmp_u32()
41 struct drm_i915_private *i915 = engine->i915; in read_timestamp()
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
81 struct intel_gt *gt = arg; in live_gt_clocks() local
87 if (!gt->clock_frequency) { /* unknown */ in live_gt_clocks()
92 if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */ in live_gt_clocks()
95 wakeref = intel_gt_pm_get(gt); in live_gt_clocks()
96 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in live_gt_clocks()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dpci.c80 { 0x106b, 0x0605, "GeForce GT 130" },
86 { 0x1043, 0x202d, "GeForce GT 220M" },
92 { 0x152d, 0x0850, "GeForce GT 240M LE" },
98 { 0x1043, 0x14a2, "GeForce GT 320M" },
99 { 0x1043, 0x14d2, "GeForce GT 320M" },
105 { 0x106b, 0x0633, "GeForce GT 120" },
111 { 0x106b, 0x0693, "GeForce GT 120" },
232 { 0x1025, 0x0692, "GeForce GT 620M" },
233 { 0x1025, 0x0725, "GeForce GT 620M" },
234 { 0x1025, 0x0728, "GeForce GT 620M" },
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_mocs.c1 // SPDX-License-Identifier: GPL-2.0 AND MIT
23 static int live_mocs_init(struct live_mocs *arg, struct xe_gt *gt) in live_mocs_init() argument
30 flags = get_mocs_settings(gt_to_xe(gt), &arg->table); in live_mocs_init()
32 kunit_info(test, "gt %d", gt->info.id); in live_mocs_init()
33 kunit_info(test, "gt type %d", gt->info.type); in live_mocs_init()
34 kunit_info(test, "table size %d", arg->table.table_size); in live_mocs_init()
35 kunit_info(test, "table uc_index %d", arg->table.uc_index); in live_mocs_init()
36 kunit_info(test, "table num_mocs_regs %d", arg->table.num_mocs_regs); in live_mocs_init()
41 static void read_l3cc_table(struct xe_gt *gt, in read_l3cc_table() argument
49 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); in read_l3cc_table()
[all …]
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_irq.c1 // SPDX-License-Identifier: MIT
7 #include "gt/intel_gt_irq.h"
8 #include "gt/intel_gt_regs.h"
9 #include "gt/intel_gt_types.h"
21 * intel_pxp_irq_handler - Handles PXP interrupts.
27 struct intel_gt *gt; in intel_pxp_irq_handler() local
32 gt = pxp->ctrl_gt; in intel_pxp_irq_handler()
34 lockdep_assert_held(gt->irq_lock); in intel_pxp_irq_handler()
43 pxp->session_events |= PXP_TERMINATION_REQUEST | PXP_INVAL_REQUIRED | in intel_pxp_irq_handler()
48 pxp->session_events |= PXP_TERMINATION_COMPLETE | PXP_EVENT_TYPE_IRQ; in intel_pxp_irq_handler()
[all …]
/linux/drivers/gpu/drm/i915/selftests/
H A Digt_reset.c2 * SPDX-License-Identifier: MIT
9 #include "gt/intel_engine.h"
10 #include "gt/intel_gt.h"
14 void igt_global_reset_lock(struct intel_gt *gt) in igt_global_reset_lock() argument
19 pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags); in igt_global_reset_lock()
21 while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) in igt_global_reset_lock()
22 wait_event(gt->reset.queue, in igt_global_reset_lock()
23 !test_bit(I915_RESET_BACKOFF, &gt->reset.flags)); in igt_global_reset_lock()
25 for_each_engine(engine, gt, id) { in igt_global_reset_lock()
27 &gt->reset.flags)) in igt_global_reset_lock()
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/linux/drivers/gpu/drm/i915/gt/uc/
H A Dselftest_guc.c1 // SPDX-License-Identifier: MIT
6 #include "gt/intel_gt_print.h"
18 err = -ETIMEDOUT; in request_add_spin()
34 ret = i915_sw_fence_await_dma_fence(&rq->submit, in nop_user_request()
35 &from->fence, 0, in nop_user_request()
51 struct intel_gt *gt = arg; in intel_guc_scrub_ctbs() local
59 if (!intel_has_gpu_reset(gt)) in intel_guc_scrub_ctbs()
62 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_guc_scrub_ctbs()
63 engine = intel_selftest_find_any_engine(gt); in intel_guc_scrub_ctbs()
70 gt_err(gt, "Failed to create context %d: %pe\n", i, ce); in intel_guc_scrub_ctbs()
[all …]
H A Dintel_gsc_uc.c1 // SPDX-License-Identifier: MIT
8 #include "gt/intel_gt.h"
9 #include "gt/intel_gt_print.h"
19 struct intel_gt *gt = gsc_uc_to_gt(gsc); in gsc_work() local
24 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in gsc_work()
26 spin_lock_irq(gt->irq_lock); in gsc_work()
27 actions = gsc->gsc_work_actions; in gsc_work()
28 gsc->gsc_work_actions = 0; in gsc_work()
29 spin_unlock_irq(gt->irq_lock); in gsc_work()
36 else if (ret != -EEXIST) in gsc_work()
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