1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_EYEQ 70 bool "Mobileye EyeQ reset controller" 71 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 72 select AUXILIARY_BUS 73 default MACH_EYEQ5 || MACH_EYEQ6H 74 help 75 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 76 and EyeQ6H SoCs. 77 78 It has one or more domains, with a varying number of resets in each. 79 Registers are located in a shared register region called OLB. EyeQ6H 80 has multiple reset instances. 81 82config RESET_GPIO 83 tristate "GPIO reset controller" 84 depends on GPIOLIB 85 help 86 This enables a generic reset controller for resets attached via 87 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 88 property. 89 90 If compiled as module, it will be called reset-gpio. 91 92config RESET_HSDK 93 bool "Synopsys HSDK Reset Driver" 94 depends on HAS_IOMEM 95 depends on ARC_SOC_HSDK || COMPILE_TEST 96 help 97 This enables the reset controller driver for HSDK board. 98 99config RESET_IMX7 100 tristate "i.MX7/8 Reset Driver" 101 depends on HAS_IOMEM 102 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 103 default y if SOC_IMX7D 104 select MFD_SYSCON 105 help 106 This enables the reset controller driver for i.MX7 SoCs. 107 108config RESET_IMX8MP_AUDIOMIX 109 tristate "i.MX8MP AudioMix Reset Driver" 110 depends on ARCH_MXC || COMPILE_TEST 111 select AUXILIARY_BUS 112 default CLK_IMX8MP 113 help 114 This enables the reset controller driver for i.MX8MP AudioMix 115 116config RESET_INTEL_GW 117 bool "Intel Reset Controller Driver" 118 depends on X86 || COMPILE_TEST 119 depends on OF && HAS_IOMEM 120 select REGMAP_MMIO 121 help 122 This enables the reset controller driver for Intel Gateway SoCs. 123 Say Y to control the reset signals provided by reset controller. 124 Otherwise, say N. 125 126config RESET_K210 127 bool "Reset controller driver for Canaan Kendryte K210 SoC" 128 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 129 select MFD_SYSCON 130 default SOC_CANAAN_K210 131 help 132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 133 Say Y if you want to control reset signals provided by this 134 controller. 135 136config RESET_LANTIQ 137 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 138 default SOC_TYPE_XWAY 139 help 140 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 141 142config RESET_LPC18XX 143 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 144 default ARCH_LPC18XX 145 help 146 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 147 148config RESET_MCHP_SPARX5 149 tristate "Microchip Sparx5 reset driver" 150 depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 151 default y if SPARX5_SWITCH 152 select MFD_SYSCON 153 help 154 This driver supports switch core reset for the Microchip Sparx5 SoC. 155 156config RESET_NPCM 157 bool "NPCM BMC Reset Driver" if COMPILE_TEST 158 default ARCH_NPCM 159 select AUXILIARY_BUS 160 help 161 This enables the reset controller driver for Nuvoton NPCM 162 BMC SoCs. 163 164config RESET_NUVOTON_MA35D1 165 bool "Nuvoton MA35D1 Reset Driver" 166 depends on ARCH_MA35 || COMPILE_TEST 167 default ARCH_MA35 168 help 169 This enables the reset controller driver for Nuvoton MA35D1 SoC. 170 171config RESET_PISTACHIO 172 bool "Pistachio Reset Driver" 173 depends on MIPS || COMPILE_TEST 174 help 175 This enables the reset driver for ImgTec Pistachio SoCs. 176 177config RESET_POLARFIRE_SOC 178 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 179 depends on MCHP_CLK_MPFS 180 select AUXILIARY_BUS 181 default MCHP_CLK_MPFS 182 help 183 This driver supports peripheral reset for the Microchip PolarFire SoC 184 185config RESET_QCOM_AOSS 186 tristate "Qcom AOSS Reset Driver" 187 depends on ARCH_QCOM || COMPILE_TEST 188 help 189 This enables the AOSS (always on subsystem) reset driver 190 for Qualcomm SDM845 SoCs. Say Y if you want to control 191 reset signals provided by AOSS for Modem, Venus, ADSP, 192 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 193 194config RESET_QCOM_PDC 195 tristate "Qualcomm PDC Reset Driver" 196 depends on ARCH_QCOM || COMPILE_TEST 197 help 198 This enables the PDC (Power Domain Controller) reset driver 199 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 200 to control reset signals provided by PDC for Modem, Compute, 201 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 202 203config RESET_RASPBERRYPI 204 tristate "Raspberry Pi 4 Firmware Reset Driver" 205 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 206 default USB_XHCI_PCI 207 help 208 Raspberry Pi 4's co-processor controls some of the board's HW 209 initialization process, but it's up to Linux to trigger it when 210 relevant. This driver provides a reset controller capable of 211 interfacing with RPi4's co-processor and model these firmware 212 initialization routines as reset lines. 213 214config RESET_RZG2L_USBPHY_CTRL 215 tristate "Renesas RZ/G2L USBPHY control driver" 216 depends on ARCH_RZG2L || COMPILE_TEST 217 help 218 Support for USBPHY Control found on RZ/G2L family. It mainly 219 controls reset and power down of the USB/PHY. 220 221config RESET_SCMI 222 tristate "Reset driver controlled via ARM SCMI interface" 223 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 224 default ARM_SCMI_PROTOCOL 225 help 226 This driver provides support for reset signal/domains that are 227 controlled by firmware that implements the SCMI interface. 228 229 This driver uses SCMI Message Protocol to interact with the 230 firmware controlling all the reset signals. 231 232config RESET_SIMPLE 233 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 234 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 235 depends on HAS_IOMEM 236 help 237 This enables a simple reset controller driver for reset lines that 238 that can be asserted and deasserted by toggling bits in a contiguous, 239 exclusive register space. 240 241 Currently this driver supports: 242 - Altera SoCFPGAs 243 - ASPEED BMC SoCs 244 - Bitmain BM1880 SoC 245 - Realtek SoCs 246 - RCC reset controller in STM32 MCUs 247 - Allwinner SoCs 248 - SiFive FU740 SoCs 249 - Sophgo SoCs 250 251config RESET_SOCFPGA 252 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 253 default ARM && ARCH_INTEL_SOCFPGA 254 select RESET_SIMPLE 255 help 256 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 257 driver gets initialized early during platform init calls. 258 259config RESET_SUNPLUS 260 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 261 default ARCH_SUNPLUS 262 help 263 This enables the reset driver support for Sunplus SoCs. 264 The reset lines that can be asserted and deasserted by toggling bits 265 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 266 which means each register holds 16 reset lines. 267 268config RESET_SUNXI 269 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 270 default ARCH_SUNXI 271 select RESET_SIMPLE 272 help 273 This enables the reset driver for Allwinner SoCs. 274 275config RESET_TI_SCI 276 tristate "TI System Control Interface (TI-SCI) reset driver" 277 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 278 help 279 This enables the reset driver support over TI System Control Interface 280 available on some new TI's SoCs. If you wish to use reset resources 281 managed by the TI System Controller, say Y here. Otherwise, say N. 282 283config RESET_TI_SYSCON 284 tristate "TI SYSCON Reset Driver" 285 depends on HAS_IOMEM 286 select MFD_SYSCON 287 help 288 This enables the reset driver support for TI devices with 289 memory-mapped reset registers as part of a syscon device node. If 290 you wish to use the reset framework for such memory-mapped devices, 291 say Y here. Otherwise, say N. 292 293config RESET_TI_TPS380X 294 tristate "TI TPS380x Reset Driver" 295 select GPIOLIB 296 help 297 This enables the reset driver support for TI TPS380x devices. If 298 you wish to use the reset framework for such devices, say Y here. 299 Otherwise, say N. 300 301config RESET_TN48M_CPLD 302 tristate "Delta Networks TN48M switch CPLD reset controller" 303 depends on MFD_TN48M_CPLD || COMPILE_TEST 304 default MFD_TN48M_CPLD 305 help 306 This enables the reset controller driver for the Delta TN48M CPLD. 307 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 308 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 309 Microchip PD69200 PoE PSE controller. 310 311 This driver can also be built as a module. If so, the module will be 312 called reset-tn48m. 313 314config RESET_UNIPHIER 315 tristate "Reset controller driver for UniPhier SoCs" 316 depends on ARCH_UNIPHIER || COMPILE_TEST 317 depends on OF && MFD_SYSCON 318 default ARCH_UNIPHIER 319 help 320 Support for reset controllers on UniPhier SoCs. 321 Say Y if you want to control reset signals provided by System Control 322 block, Media I/O block, Peripheral Block. 323 324config RESET_UNIPHIER_GLUE 325 tristate "Reset driver in glue layer for UniPhier SoCs" 326 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 327 default ARCH_UNIPHIER 328 select RESET_SIMPLE 329 help 330 Support for peripheral core reset included in its own glue layer 331 on UniPhier SoCs. Say Y if you want to control reset signals 332 provided by the glue layer. 333 334config RESET_ZYNQ 335 bool "ZYNQ Reset Driver" if COMPILE_TEST 336 default ARCH_ZYNQ 337 help 338 This enables the reset controller driver for Xilinx Zynq SoCs. 339 340config RESET_ZYNQMP 341 bool "ZYNQMP Reset Driver" if COMPILE_TEST 342 default ARCH_ZYNQMP 343 help 344 This enables the reset controller driver for Xilinx ZynqMP SoCs. 345 346source "drivers/reset/amlogic/Kconfig" 347source "drivers/reset/starfive/Kconfig" 348source "drivers/reset/sti/Kconfig" 349source "drivers/reset/hisilicon/Kconfig" 350source "drivers/reset/tegra/Kconfig" 351 352endif 353