21 #define RTC_CTRL		(0x0 << 2)		/* Control RTC */
22 #define RTC_ALRM0_EN		BIT(0)
26 #define RTC_COUNTER_REG		(0x1 << 2)		/* Program RTC counter initial value */
28 #define RTC_ALARM0_REG		(0x2 << 2)		/* Program RTC alarm0 value */
30 #define RTC_SEC_ADJUST_REG	(0x6 << 2)		/* Control second-based timing adjustment */
31 #define RTC_MATCH_COUNTER	GENMASK(18, 0)
35 #define RTC_INT_MASK		(0x8 << 2)		/* RTC interrupt mask */
36 #define RTC_ALRM0_IRQ_MSK	BIT(0)
38 #define RTC_INT_CLR		(0x9 << 2)		/* Clear RTC interrupt */
39 #define RTC_ALRM0_IRQ_CLR	BIT(0)
41 #define RTC_OSCIN_CTRL0		(0xa << 2)		/* Control RTC clk from 24M */
42 #define RTC_OSCIN_CTRL1		(0xb << 2)		/* Control RTC clk from 24M */
45 #define RTC_OSCIN_OUT_N0M0	GENMASK(11, 0)
48 #define RTC_INT_STATUS		(0xc << 2)		/* RTC interrupt status */
49 #define RTC_ALRM0_IRQ_STATUS	BIT(0)
51 #define RTC_REAL_TIME		(0xd << 2)		/* RTC time value */
53 #define RTC_OSCIN_OUT_32K_N0	0x2dc
54 #define RTC_OSCIN_OUT_32K_N1	0x2db
55 #define RTC_OSCIN_OUT_32K_M0	0x1
56 #define RTC_OSCIN_OUT_32K_M1	0x2
58 #define RTC_SWALLOW_SECOND	0x2
59 #define RTC_INSERT_SECOND	0x3
88 	for (i = 0; (1 << i) < size; i++)  in gray_to_binary()
114 	return 0;  in aml_rtc_read_time()
137 	return 0;  in aml_rtc_set_time()
152 			   RTC_ALRM0_IRQ_MSK, 0);  in aml_rtc_set_alarm()
162 	return 0;  in aml_rtc_set_alarm()
183 	alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0;  in aml_rtc_read_alarm()
187 	return 0;  in aml_rtc_read_alarm()
204 		val = 0;  in aml_rtc_read_offset()
214 	return 0;  in aml_rtc_read_offset()
220 	int sign = 0;  in aml_rtc_set_offset()
221 	int match_counter = 0;  in aml_rtc_set_offset()
222 	int enable = 0;  in aml_rtc_set_offset()
231 		sign = offset < 0 ? RTC_SWALLOW_SECOND : RTC_INSERT_SECOND;  in aml_rtc_set_offset()
233 		if (match_counter < 0 || match_counter > RTC_MATCH_COUNTER)  in aml_rtc_set_offset()
242 	return 0;  in aml_rtc_set_offset()
253 				   RTC_ALRM0_IRQ_MSK, 0);  in aml_rtc_alarm_enable()
258 				   RTC_ALRM0_EN, 0);  in aml_rtc_alarm_enable()
261 	return 0;  in aml_rtc_alarm_enable()
278 	regmap_write(rtc->map, RTC_ALARM0_REG, 0);  in aml_rtc_handler()
288 	u32 reg_val = 0;  in aml_rtc_init()
316 			regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0);  in aml_rtc_init()
321 	regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0);  in aml_rtc_init()
329 	int ret = 0;  in aml_rtc_probe()
339 	base = devm_platform_ioremap_resource(pdev, 0);  in aml_rtc_probe()
347 	rtc->irq = platform_get_irq(pdev, 0);  in aml_rtc_probe()
348 	if (rtc->irq < 0)  in aml_rtc_probe()
382 	rtc->rtc_dev->range_min = 0;  in aml_rtc_probe()
391 	return 0;  in aml_rtc_probe()
407 	return 0;  in aml_rtc_suspend()
417 	return 0;  in aml_rtc_resume()