Lines Matching +full:msi +full:- +full:available +full:- +full:ranges
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
26 - $ref: /schemas/pci/pci-host-bridge.yaml#
27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
28 - if:
31 - msi-map
34 interrupt-names:
36 const: msi
41 At least DBI reg-space and peripheral devices CFG-space outbound window
43 also required if the space is unrolled (IP-core version >= 4.80a).
47 reg-names:
52 - description:
53 Basic DWC PCIe controller configuration-space accessible over
60 - description:
61 Shadow DWC PCIe config-space registers. This space is selected
63 the PCI-SIG PCIe CFG-space with the shadow registers for some
65 mainly relevant for the end-point controller configuration,
66 but still there are some shadow registers available for the
69 - description:
70 External Local Bus registers. It's an application-dependent
73 be accessed over some platform-specific means (for instance
76 - description:
80 and CS2 = 1. For IP-core releases prior v4.80a, these registers
84 is available at 0x80000 base address.
86 - description:
87 Platform-specific eDMA registers. Some platforms may have eDMA
88 CSRs mapped in a non-standard base address. The registers offset
89 can be changed or the MS/LS-bits of the address can be attached
90 in an additional RTL block before the MEM-IO transactions reach
93 - description:
98 platform-specific method.
100 - description:
101 Outbound iATU-capable memory-region which will be used to access
104 - description:
105 Vendor-specific CSR names. Consider using the generic names above
108 - description: See native 'dbi' CSR region for details.
110 - description: See native 'elbi/app' CSR region for details.
112 - description: See native 'atu' CSR region for details.
114 - description: Syscon-related CSR regions.
116 - description: Tegra234 aperture
118 - description: AMD MDB PCIe SLCR region
121 - contains:
123 - contains:
128 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
133 interrupt-names:
138 - description:
142 - description:
147 - description:
153 pattern: '^dma([0-9]|1[0-5])?$'
154 - description:
159 - description:
163 - description:
164 Application-specific IRQ raised depending on the vendor-specific
167 - description:
168 DSP AXI MSI Interrupt detected. It gets de-asserted when there is
169 no more MSI interrupt pending. The interrupt is relevant to the
170 iMSI-RX - Integrated MSI Receiver (AXI bridge).
171 const: msi
172 - description:
177 - description:
183 - description:
188 - description:
189 Hot-plug event is detected. That is a bit has been set in the
193 - description:
198 - description:
203 - description:
207 - description:
208 Vendor-specific IRQ names. Consider using the generic names above
211 - description: See native "app" IRQ for details
217 - compatible
218 - reg
219 - reg-names
222 - |
224 compatible = "snps,dw-pcie";
228 reg-names = "dbi", "config";
229 #address-cells = <3>;
230 #size-cells = <2>;
231 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
233 bus-range = <0x0 0xff>;
236 interrupt-names = "msi", "hp";
238 reset-gpios = <&port0 0 1>;
241 phy-names = "pcie";
243 num-lanes = <1>;
244 max-link-speed = <3>;