| e4442636 | 19-Jun-2025 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
mips: dts: realtek: Add gpio block
The RTL9300 has a block of GPIOs included in the SoC. Add these to the devicetree.
This is taken from openwrt[1] the differences are removing the unnecessary seco
mips: dts: realtek: Add gpio block
The RTL9300 has a block of GPIOs included in the SoC. Add these to the devicetree.
This is taken from openwrt[1] the differences are removing the unnecessary second cell from the interrupt and removing the -controller from the node name to conform to the dtschema.
[1] - https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/dts/rtl930x.dtsi
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 787981d1 | 19-Jun-2025 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
mips: dts: realtek: Add watchdog
The RTL9300 has an integrated watchdog. Add this to the devicetree.
This is taken from openwrt[1] the only difference is removing the unnecessary second cell from t
mips: dts: realtek: Add watchdog
The RTL9300 has an integrated watchdog. Add this to the devicetree.
This is taken from openwrt[1] the only difference is removing the unnecessary second cell from the interrupts.
[1] - https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/dts/rtl930x.dtsi
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 1931e4cc | 19-Jun-2025 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
mips: dts: realtek: Add switch interrupts
Add interrupts for the rtl9301-switch.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.
mips: dts: realtek: Add switch interrupts
Add interrupts for the rtl9301-switch.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 5ae16e22 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Add restart to Cisco SG220-26P
Define a gpio-restart node to the Cisco SG220-26P so the device can be rebooted using the SoC's hard reset pin. Set the priority to 192 so the gpio
mips: dts: realtek: Add restart to Cisco SG220-26P
Define a gpio-restart node to the Cisco SG220-26P so the device can be rebooted using the SoC's hard reset pin. Set the priority to 192 so the gpio-restart method takes priority over the watchdog restart.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| b3992b82 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Add RTL838x SoC peripherals
Add some of the SoC's CPU peripherals currently supported: - GPIO controller with support for 24 GPIO lines, although not all lines are brought
mips: dts: realtek: Add RTL838x SoC peripherals
Add some of the SoC's CPU peripherals currently supported: - GPIO controller with support for 24 GPIO lines, although not all lines are brought out to pads on the SoC package. These lines can generate interrupts from external sources. - Watchdog which can be used to restart the SoC if no external restart logic is present. - SPI controller, primarily used to access NOR flash
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 4b7785dd | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Replace uart clock property
Add a fixed clock to define the clock frequency of the Lexra bus and use this for the two uart nodes instead of a separate clock-frequency property.
mips: dts: realtek: Replace uart clock property
Add a fixed clock to define the clock frequency of the Lexra bus and use this for the two uart nodes instead of a separate clock-frequency property.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 31e96a0a | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Correct uart interrupt-parent
The uart interrupts on RTL838x chips do not lead to the CPU's interrupt controller directly, but passes via the SoC interrupt controller. Update the
mips: dts: realtek: Correct uart interrupt-parent
The uart interrupts on RTL838x chips do not lead to the CPU's interrupt controller directly, but passes via the SoC interrupt controller. Update the interrupt-parent property to fix this.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 8e644816 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Add SoC IRQ node for RTL838x
Add the SoC interrupt controller so other components can link to it.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bog
mips: dts: realtek: Add SoC IRQ node for RTL838x
Add the SoC interrupt controller so other components can link to it.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 045cbcc4 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Fold rtl83xx into rtl838x
rtl83xx.dtsi was once (presumably) created as a base for both RTL838x and RTL839x SoCs. Both SoCs have a different CPU and the peripherals require diffe
mips: dts: realtek: Fold rtl83xx into rtl838x
rtl83xx.dtsi was once (presumably) created as a base for both RTL838x and RTL839x SoCs. Both SoCs have a different CPU and the peripherals require different compatibles. Fold rtl83xx.dtsi into rtl838x.dtsi, currently only supporting RTL838x SoCs, and create the RTL839x base include later when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 652d5000 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Add address to SoC node name
Although not strictly required by the simple-bus binding, add the bus offset to the node name to be consistent with other nodes. Also drop the node l
mips: dts: realtek: Add address to SoC node name
Although not strictly required by the simple-bus binding, add the bus offset to the node name to be consistent with other nodes. Also drop the node label as it is not referenced anywhere.
Signed-off-by: Sander Vanheule <sander@svanheule.net> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| e5723ab6 | 19-Jan-2025 |
Sander Vanheule <sander@svanheule.net> |
mips: dts: realtek: Clean up CPU clocks
The referenced CPU clock does not require any additional #clock-cells, so drop the extraneous '0' in the referenced CPU clock.
The binding for MIPS cpus also
mips: dts: realtek: Clean up CPU clocks
The referenced CPU clock does not require any additional #clock-cells, so drop the extraneous '0' in the referenced CPU clock.
The binding for MIPS cpus also does not allow for the clock-names property, so just drop it.
This resolves some error message from 'dtbs_check': cpu@0: clocks: [[4], [0]] is too long 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Sander Vanheule <sander@svanheule.net> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # For RTL9302C Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 75eb0cbe | 10-Jul-2024 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
mips: dts: realtek: add device_type property to cpu node
Add device_type = "cpu" to the cpu node for the rtl838x SoC. This resolves the following dtbs_check complaint:
cpus: cpu@0: 'cache-level' i
mips: dts: realtek: add device_type property to cpu node
Add device_type = "cpu" to the cpu node for the rtl838x SoC. This resolves the following dtbs_check complaint:
cpus: cpu@0: 'cache-level' is a required property
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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