| cf141287 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for register xfer
- Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a synchronization method. By d
misc: amd-sbi: Add support for register xfer
- Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a synchronization method. By defining, a register access path, we use APML modules and library for all APML transactions. Without having to use external tools such as i2c-tools, which may cause race conditions.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-10-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 69b1ba83 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for read MCA register protocol
- AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The information is accessed for range of
misc: amd-sbi: Add support for read MCA register protocol
- AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The information is accessed for range of MCA registers by passing register address and thread ID to the protocol. MCA register read command using the register address to access Core::X86::Msr::MCG_CAP which determines the number of MCA banks. Access is read-only
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-9-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| bb13a84e | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for CPUID protocol
- AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed b
misc: amd-sbi: Add support for CPUID protocol
- AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed by providing CPUID Function, extended function and thread ID to the protocol. Undefined function returns 0.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-8-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| ad76f3e8 | 13-Mar-2024 |
Thomas Weißschuh <linux@weissschuh.net> |
misc/pvpanic: add shutdown event definition
Shutdown requests are normally hardware dependent. By extending pvpanic to also handle shutdown requests, guests can submit such requests with an easily i
misc/pvpanic: add shutdown event definition
Shutdown requests are normally hardware dependent. By extending pvpanic to also handle shutdown requests, guests can submit such requests with an easily implementable and cross-platform mechanism.
The event was added to the specification in qemu commit 73279cecca03 ("docs/specs/pvpanic: document shutdown event").
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240313-pvpanic-shutdown-header-v1-2-7f1970d66366@weissschuh.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| c2239a25 | 16-Nov-2022 |
farah kassabri <fkassabri@habana.ai> |
habanalabs: pass-through request from user to f/w
Add a uAPI, as part of the INFO IOCTL, to allow users to send requests directly to f/w, according to a pre-defined set of opcodes that the f/w expos
habanalabs: pass-through request from user to f/w
Add a uAPI, as part of the INFO IOCTL, to allow users to send requests directly to f/w, according to a pre-defined set of opcodes that the f/w exposes.
The f/w will put the result in a kernel-allocated buffer, which the driver will then copy to the user-supplied buffer.
This will allow f/w tools to communicate directly with the f/w without the need to add a new uAPI to the driver for each new type of request.
Signed-off-by: farah kassabri <fkassabri@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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| aff6354a | 31-Oct-2022 |
Dani Liberman <dliberman@habana.ai> |
habanalabs/gaudi: add page fault notify event
Each time page fault happens, besides capturing its data, also notify the user about it.
Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by
habanalabs/gaudi: add page fault notify event
Each time page fault happens, besides capturing its data, also notify the user about it.
Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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| cb5fb665 | 30-Oct-2022 |
Dani Liberman <dliberman@habana.ai> |
habanalabs/gaudi: add razwi notify event
Each time razwi (read-only zero, write ignore) happens, besides capturing its data, also notify the user about it.
Signed-off-by: Dani Liberman <dliberman@h
habanalabs/gaudi: add razwi notify event
Each time razwi (read-only zero, write ignore) happens, besides capturing its data, also notify the user about it.
Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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| 15ac503c | 28-Sep-2022 |
Dani Liberman <dliberman@habana.ai> |
habanalabs/gaudi2: capture RAZWI information
Added function to calculate possible engines which caused RAZWI (read-only zero, write ignored), from a given router id or module index.
When getting RA
habanalabs/gaudi2: capture RAZWI information
Added function to calculate possible engines which caused RAZWI (read-only zero, write ignored), from a given router id or module index.
When getting RAZWI via PSOC IP, first the router id is calculated and then the possible engines that caused the RAZWI are calculated.
There is a possibility that the RAZWI initiator is not an engine. In that case, it will not be included in possible engines as it doesn't have an engine id.
RAZWI information is captured when receiving event from engine or via PSOC IP.
Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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