| c0a0a7ae | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: lan969x-serdes: add support for lan969x serdes driver
Add support for lan969x SERDES driver. Lan969x has ten 10G SERDES'es which share the same features and data rates as the Sparx5 SERDES'es.
phy: lan969x-serdes: add support for lan969x serdes driver
Add support for lan969x SERDES driver. Lan969x has ten 10G SERDES'es which share the same features and data rates as the Sparx5 SERDES'es.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-9-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 6158a32b | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add support for branching on chip type
In preparation for lan969x, add a way to branch out on code that is to be executed on either Sparx5 or lan969x. Initially, this is require
phy: sparx5-serdes: add support for branching on chip type
In preparation for lan969x, add a way to branch out on code that is to be executed on either Sparx5 or lan969x. Initially, this is required to branch out when checking the SERDES types and SERDES speeds, since the handling of these differ on the two platforms. This will also be used by the lan969x driver introduced in a subsequent patch.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-7-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| c8e4c8b7 | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add indirection layer to register macros
The register macros are used to read and write to the SERDES registers. The registers are largely the same on Sparx5 and lan969x, however
phy: sparx5-serdes: add indirection layer to register macros
The register macros are used to read and write to the SERDES registers. The registers are largely the same on Sparx5 and lan969x, however some register target sizes differ. Therefore we introduce a new indirection to the register macros. The target sizes are looked up, using a mapping table (sparx5_serdes_tsize) that maps the register target to the register target size.
With this addition, we can reuse all the existing macros for lan969x.
Also the autogenerated macros are now formatted slightly different, to adhere to a 80 character limit.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-6-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| f16df057 | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add function for getting the CMU index
The SERDES to CMU mapping is different on Sparx5 and lan969x. Therefore create a function for getting the CMU index on Sparx5.
Signed-off-
phy: sparx5-serdes: add function for getting the CMU index
The SERDES to CMU mapping is different on Sparx5 and lan969x. Therefore create a function for getting the CMU index on Sparx5.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-5-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| d61d42a9 | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add ops to match data
We need to handle code differently in a few places. Add a struct: sparx5_serdes_ops for this purpose, and populate it a with function to set the SERDES type
phy: sparx5-serdes: add ops to match data
We need to handle code differently in a few places. Add a struct: sparx5_serdes_ops for this purpose, and populate it a with function to set the SERDES type.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-4-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 5206ba96 | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add constant for the number of CMU's
The number of CMU's differ for Sparx5 and lan969x, so add a new field: cmu_max and use it throughout.
Signed-off-by: Daniel Machon <daniel.m
phy: sparx5-serdes: add constant for the number of CMU's
The number of CMU's differ for Sparx5 and lan969x, so add a new field: cmu_max and use it throughout.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-3-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 8e65baf8 | 09-Sep-2024 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add constants to match data
We need to handle a few different constants that differ for Sparx5 and lan969x. Add a new struct: sparx5_serdes_consts for this purpose. We populate i
phy: sparx5-serdes: add constants to match data
We need to handle a few different constants that differ for Sparx5 and lan969x. Add a new struct: sparx5_serdes_consts for this purpose. We populate it with an initial field for the number of SERDES'es: sd_max.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-2-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 7a503071 | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanes
Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resettin
phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanes
Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resetting the serdes involves reconfiguring it with preset values. The serdesmode is required to determine the clock-providing CMU, therefore make sure the serdes is not reconfigured if the serdesmode is not set.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 2db7289f | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: remove power up of all CMUs
CMUs should not be powered up by default anymore, so remove responsible code.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https:
phy: sparx5-serdes: remove power up of all CMUs
CMUs should not be powered up by default anymore, so remove responsible code.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 96bb1664 | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: power on CMUs individually
Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a pr
phy: sparx5-serdes: power on CMUs individually
Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a preset map of serdes mode and index to CMU index.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-6-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 044f3a1a | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: power down all CMUs by default
All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring
phy: sparx5-serdes: power down all CMUs by default
All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU.
Individual CMUs are later powered up, when the serdes lanes are configured.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-5-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 238a583f | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: reorder CMU functions
Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes.
Signed-off-by: Daniel Machon <daniel.machon@microch
phy: sparx5-serdes: reorder CMU functions
Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 3d61a1f8 | 17-Apr-2023 |
Daniel Machon <daniel.machon@microchip.com> |
phy: sparx5-serdes: configure optimal quiet mode for serdes lanes
All the serdes lanes of the sparx5 will transition between normal mode and quiet mode, depending on activity. Make sure that the qui
phy: sparx5-serdes: configure optimal quiet mode for serdes lanes
All the serdes lanes of the sparx5 will transition between normal mode and quiet mode, depending on activity. Make sure that the quiet mode is configured optimally for all lanes initially. Although not much, this will save a small amount of power.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-3-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 17dcc120 | 30-Nov-2021 |
Horatiu Vultur <horatiu.vultur@microchip.com> |
phy: lan966x: Extend lan966x to support multiple phy interfaces.
Currently the driver is supporting only the interfaces QSGMII, SGMII, RGMII and GMII. This patch extend the supported interfaces with
phy: lan966x: Extend lan966x to support multiple phy interfaces.
Currently the driver is supporting only the interfaces QSGMII, SGMII, RGMII and GMII. This patch extend the supported interfaces with 1000BASE-X and 2500BASE-X.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20211130101015.164916-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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