1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ 8 9 /* Only for QMP V5 5NM PHY - TX registers */ 10 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80 15 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00 16 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04 17 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08 18 #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c 19 #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10 20 #define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14 21 #define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18 22 #define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c 23 #define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20 24 #define QSERDES_V5_5NM_TX_LPB_EN 0x24 25 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX 0x28 26 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX 0x2c 27 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30 28 #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34 29 #define QSERDES_V5_5NM_TX_PERL_LENGTH1 0x38 30 #define QSERDES_V5_5NM_TX_PERL_LENGTH2 0x3c 31 #define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT 0x40 32 #define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL 0x44 33 #define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN 0x48 34 #define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN 0x4c 35 #define QSERDES_V5_5NM_TX_TX_POL_INV 0x50 36 #define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN 0x54 37 #define QSERDES_V5_5NM_TX_BIST_PATTERN1 0x58 38 #define QSERDES_V5_5NM_TX_BIST_PATTERN2 0x5c 39 #define QSERDES_V5_5NM_TX_BIST_PATTERN3 0x60 40 #define QSERDES_V5_5NM_TX_BIST_PATTERN4 0x64 41 #define QSERDES_V5_5NM_TX_BIST_PATTERN5 0x68 42 #define QSERDES_V5_5NM_TX_BIST_PATTERN6 0x6c 43 #define QSERDES_V5_5NM_TX_BIST_PATTERN7 0x70 44 #define QSERDES_V5_5NM_TX_BIST_PATTERN8 0x74 45 #define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78 46 #define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c 47 #define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80 48 #define QSERDES_V5_5NM_TX_ATB_SEL1 0x84 49 #define QSERDES_V5_5NM_TX_ATB_SEL2 0x88 50 #define QSERDES_V5_5NM_TX_RCV_DETECT_LVL 0x8c 51 #define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2 0x90 52 #define QSERDES_V5_5NM_TX_PRBS_SEED1 0x94 53 #define QSERDES_V5_5NM_TX_PRBS_SEED2 0x98 54 #define QSERDES_V5_5NM_TX_PRBS_SEED3 0x9c 55 #define QSERDES_V5_5NM_TX_PRBS_SEED4 0xa0 56 #define QSERDES_V5_5NM_TX_RESET_GEN 0xa4 57 #define QSERDES_V5_5NM_TX_RESET_GEN_MUXES 0xa8 58 #define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN 0xac 59 #define QSERDES_V5_5NM_TX_VMODE_CTRL1 0xb0 60 #define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1 0xb4 61 #define QSERDES_V5_5NM_TX_BIST_STATUS 0xb8 62 #define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1 0xbc 63 #define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2 0xc0 64 #define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1 0xc4 65 #define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG 0xc8 66 #define QSERDES_V5_5NM_TX_PI_QEC_CTRL 0xcc 67 #define QSERDES_V5_5NM_TX_PRE_EMPH 0xd0 68 #define QSERDES_V5_5NM_TX_SW_RESET 0xd4 69 #define QSERDES_V5_5NM_TX_TX_BAND 0xd8 70 #define QSERDES_V5_5NM_TX_SLEW_CNTL0 0xdc 71 #define QSERDES_V5_5NM_TX_SLEW_CNTL1 0xe0 72 #define QSERDES_V5_5NM_TX_INTERFACE_SELECT 0xe4 73 #define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL 0xe8 74 #define QSERDES_V5_5NM_TX_DEBUG_BUS0 0xec 75 #define QSERDES_V5_5NM_TX_DEBUG_BUS1 0xf0 76 #define QSERDES_V5_5NM_TX_DEBUG_BUS2 0xf4 77 #define QSERDES_V5_5NM_TX_DEBUG_BUS3 0xf8 78 #define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS 0xfc 79 80 /* Only for QMP V5 5NM PHY - RX registers */ 81 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0 0x000 82 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x004 83 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x008 84 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c 85 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0 0x010 86 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x014 87 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x018 88 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c 89 #define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION 0x020 90 #define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY 0x024 91 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x028 92 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c 93 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x030 94 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x034 95 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x038 96 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c 97 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x040 98 #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x044 99 #define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1 0x048 100 #define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2 0x04c 101 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE0 0x050 102 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE1 0x054 103 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE2 0x058 104 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE3 0x05c 105 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE0 0x060 106 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE1 0x064 107 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE2 0x068 108 #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE3 0x06c 109 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE0 0x070 110 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE1 0x074 111 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE2 0x078 112 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE3 0x07c 113 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE0 0x080 114 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE1 0x084 115 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2 0x088 116 #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE3 0x08c 117 #define QSERDES_V5_5NM_RX_RXCLK_DIV2_CTRL 0x090 118 #define QSERDES_V5_5NM_RX_RX_BAND 0x094 119 #define QSERDES_V5_5NM_RX_RX_TERM_BW 0x098 120 #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE0 0x09c 121 #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE1 0x0a0 122 #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2 0x0a4 123 #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE3 0x0a8 124 #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE0 0x0ac 125 #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE1 0x0b0 126 #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2 0x0b4 127 #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE3 0x0b8 128 #define QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS 0x0bc 129 #define QSERDES_V5_5NM_RX_UCDR_PD_DATA_FILTER_ENABLES 0x0c0 130 #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4 131 #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8 132 #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc 133 #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0 134 #define QSERDES_V5_5NM_RX_AUX_CONTROL 0x0d4 135 #define QSERDES_V5_5NM_RX_AUXDATA_TB 0x0d8 136 #define QSERDES_V5_5NM_RX_RCLK_AUXDATA_SEL 0x0dc 137 #define QSERDES_V5_5NM_RX_EOM_CTRL 0x0e0 138 #define QSERDES_V5_5NM_RX_AC_JTAG_ENABLE 0x0e4 139 #define QSERDES_V5_5NM_RX_AC_JTAG_INITP 0x0e8 140 #define QSERDES_V5_5NM_RX_AC_JTAG_INITN 0x0ec 141 #define QSERDES_V5_5NM_RX_AC_JTAG_LVL 0x0f0 142 #define QSERDES_V5_5NM_RX_AC_JTAG_MODE 0x0f4 143 #define QSERDES_V5_5NM_RX_AC_JTAG_RESET 0x0f8 144 #define QSERDES_V5_5NM_RX_RX_RCVR_IQ_EN 0x0fc 145 #define QSERDES_V5_5NM_RX_RX_Q_EN_RATES 0x100 146 #define QSERDES_V5_5NM_RX_RX_IDAC_I0_DC_OFFSETS 0x104 147 #define QSERDES_V5_5NM_RX_RX_IDAC_I0BAR_DC_OFFSETS 0x108 148 #define QSERDES_V5_5NM_RX_RX_IDAC_I1_DC_OFFSETS 0x10c 149 #define QSERDES_V5_5NM_RX_RX_IDAC_I1BAR_DC_OFFSETS 0x110 150 #define QSERDES_V5_5NM_RX_RX_IDAC_Q_DC_OFFSETS 0x114 151 #define QSERDES_V5_5NM_RX_RX_IDAC_QBAR_DC_OFFSETS 0x118 152 #define QSERDES_V5_5NM_RX_RX_IDAC_A_DC_OFFSETS 0x11c 153 #define QSERDES_V5_5NM_RX_RX_IDAC_ABAR_DC_OFFSETS 0x120 154 #define QSERDES_V5_5NM_RX_RX_IDAC_EN 0x124 155 #define QSERDES_V5_5NM_RX_RX_IDAC_ENABLES 0x128 156 #define QSERDES_V5_5NM_RX_RX_IDAC_SIGN 0x12c 157 #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE 0x130 158 #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL1 0x134 159 #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2 0x138 160 #define QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET 0x13c 161 #define QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE 0x140 162 #define QSERDES_V5_5NM_RX_RX_HIGHZ_PARRATE 0x144 163 #define QSERDES_V5_5NM_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148 164 #define QSERDES_V5_5NM_RX_DFE_1 0x14c 165 #define QSERDES_V5_5NM_RX_DFE_2 0x150 166 #define QSERDES_V5_5NM_RX_DFE_3 0x154 167 #define QSERDES_V5_5NM_RX_DFE_4 0x158 168 #define QSERDES_V5_5NM_RX_DFE_TAP3_CTRL 0x15c 169 #define QSERDES_V5_5NM_RX_DFE_TAP3_MANVAL_KTAP 0x160 170 #define QSERDES_V5_5NM_RX_DFE_TAP4_CTRL 0x164 171 #define QSERDES_V5_5NM_RX_DFE_TAP4_MANVAL_KTAP 0x168 172 #define QSERDES_V5_5NM_RX_DFE_TAP5_CTRL 0x16c 173 #define QSERDES_V5_5NM_RX_DFE_TAP5_MANVAL_KTAP 0x170 174 #define QSERDES_V5_5NM_RX_TX_ADPT_CTRL 0x174 175 #define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1 0x178 176 #define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE2 0x17c 177 #define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH1 0x180 178 #define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH2 0x184 179 #define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH1 0x188 180 #define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH2 0x18c 181 #define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH1 0x190 182 #define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH2 0x194 183 #define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1 0x198 184 #define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL2 0x19c 185 #define QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL 0x1a0 186 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL1 0x1a4 187 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL2 0x1a8 188 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac 189 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0 190 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4 191 #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8 192 #define QSERDES_V5_5NM_RX_GM_CAL 0x1bc 193 #define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK1 0x1c0 194 #define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK2 0x1c4 195 #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL2 0x1c8 196 #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL3 0x1cc 197 #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL4 0x1d0 198 #define QSERDES_V5_5NM_RX_RX_IDAC_TSETTLE_LOW 0x1d4 199 #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_LSB 0x1d8 200 #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_MSB 0x1dc 201 #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0 202 #define QSERDES_V5_5NM_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4 203 #define QSERDES_V5_5NM_RX_SIGDET_ENABLES 0x1e8 204 #define QSERDES_V5_5NM_RX_SIGDET_CNTRL 0x1ec 205 #define QSERDES_V5_5NM_RX_SIGDET_LVL 0x1f0 206 #define QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL 0x1f4 207 #define QSERDES_V5_5NM_RX_CDR_FREEZE_UP_DN 0x1f8 208 #define QSERDES_V5_5NM_RX_CDR_RESET_OVERRIDE 0x1fc 209 #define QSERDES_V5_5NM_RX_RX_INTERFACE_MODE 0x200 210 #define QSERDES_V5_5NM_RX_JITTER_GEN_MODE 0x204 211 #define QSERDES_V5_5NM_RX_SJ_AMP1 0x208 212 #define QSERDES_V5_5NM_RX_SJ_AMP2 0x20c 213 #define QSERDES_V5_5NM_RX_SJ_PER1 0x210 214 #define QSERDES_V5_5NM_RX_SJ_PER2 0x214 215 #define QSERDES_V5_5NM_RX_PPM_OFFSET1 0x218 216 #define QSERDES_V5_5NM_RX_PPM_OFFSET2 0x21c 217 #define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD1 0x220 218 #define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD2 0x224 219 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0 0x228 220 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1 0x22c 221 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2 0x230 222 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3 0x234 223 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4 0x238 224 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5 0x23c 225 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6 0x240 226 #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7 0x244 227 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0 0x248 228 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1 0x24c 229 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2 0x250 230 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3 0x254 231 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4 0x258 232 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5 0x25c 233 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6 0x260 234 #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7 0x264 235 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B0 0x268 236 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B1 0x26c 237 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B2 0x270 238 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B3 0x274 239 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B4 0x278 240 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B5 0x27c 241 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B6 0x280 242 #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B7 0x284 243 #define QSERDES_V5_5NM_RX_PHPRE_CTRL 0x288 244 #define QSERDES_V5_5NM_RX_PHPRE_INITVAL 0x28c 245 #define QSERDES_V5_5NM_RX_DFE_EN_TIMER 0x290 246 #define QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET 0x294 247 #define QSERDES_V5_5NM_RX_DCC_CTRL1 0x298 248 #define QSERDES_V5_5NM_RX_DCC_CTRL2 0x29c 249 #define QSERDES_V5_5NM_RX_DCC_OFFSET 0x2a0 250 #define QSERDES_V5_5NM_RX_DCC_CMUX_POSTCAL_OFFSET 0x2a4 251 #define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL1 0x2a8 252 #define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL2 0x2ac 253 #define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_CTRL_1 0x2b0 254 #define QSERDES_V5_5NM_RX_RX_MARG_CTRL1 0x2b4 255 #define QSERDES_V5_5NM_RX_RX_MARG_CTRL2 0x2b8 256 #define QSERDES_V5_5NM_RX_RX_MARG_CTRL3 0x2bc 257 #define QSERDES_V5_5NM_RX_RX_MARG_CTRL_4 0x2c0 258 #define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_0_1 0x2c4 259 #define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_2_3 0x2c8 260 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL1 0x2cc 261 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL2 0x2d0 262 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE210 0x2d4 263 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE3 0x2d8 264 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE210 0x2dc 265 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE3 0x2e0 266 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE210 0x2e4 267 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE3 0x2e8 268 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE210 0x2ec 269 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE3 0x2f0 270 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE210 0x2f4 271 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE3 0x2f8 272 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE210 0x2fc 273 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE3 0x300 274 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE210 0x304 275 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE3 0x308 276 #define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE10 0x30c 277 #define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x310 278 #define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CTRL 0x314 279 #define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CODE 0x318 280 #define QSERDES_V5_5NM_RX_RES_CODE_THRESH_HIGH_AND_BYP 0x31c 281 #define QSERDES_V5_5NM_RX_RES_CODE_THRESH_LOW 0x320 282 #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL1 0x324 283 #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL2 0x328 284 #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL3 0x32c 285 #define QSERDES_V5_5NM_RX_PI_CTRL1 0x330 286 #define QSERDES_V5_5NM_RX_PI_CTRL2 0x334 287 #define QSERDES_V5_5NM_RX_PI_QUAD 0x338 288 #define QSERDES_V5_5NM_RX_QPI_CTRL1 0x33c 289 #define QSERDES_V5_5NM_RX_QPI_CTRL2 0x340 290 #define QSERDES_V5_5NM_RX_QPI_QUAD 0x344 291 #define QSERDES_V5_5NM_RX_IDATA1 0x348 292 #define QSERDES_V5_5NM_RX_IDATA2 0x34c 293 #define QSERDES_V5_5NM_RX_IDATA3 0x350 294 #define QSERDES_V5_5NM_RX_AC_JTAG_OUTP 0x354 295 #define QSERDES_V5_5NM_RX_AC_JTAG_OUTN 0x358 296 #define QSERDES_V5_5NM_RX_RX_SIGDET 0x35c 297 #define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_STATUS_1 0x360 298 #define QSERDES_V5_5NM_RX_READ_EQCODE 0x364 299 #define QSERDES_V5_5NM_RX_READ_OFFSETCODE 0x368 300 #define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_LOW 0x36c 301 #define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_HIGH 0x370 302 #define QSERDES_V5_5NM_RX_VGA_READ_CODE 0x374 303 #define QSERDES_V5_5NM_RX_VTHRESH_READ_CODE 0x378 304 #define QSERDES_V5_5NM_RX_DFE_TAP1_READ_CODE 0x37c 305 #define QSERDES_V5_5NM_RX_DFE_TAP2_READ_CODE 0x380 306 #define QSERDES_V5_5NM_RX_DFE_TAP3_READ_CODE 0x384 307 #define QSERDES_V5_5NM_RX_DFE_TAP4_READ_CODE 0x388 308 #define QSERDES_V5_5NM_RX_DFE_TAP5_READ_CODE 0x38c 309 #define QSERDES_V5_5NM_RX_IDAC_STATUS_I0 0x390 310 #define QSERDES_V5_5NM_RX_IDAC_STATUS_I0BAR 0x394 311 #define QSERDES_V5_5NM_RX_IDAC_STATUS_I1 0x398 312 #define QSERDES_V5_5NM_RX_IDAC_STATUS_I1BAR 0x39c 313 #define QSERDES_V5_5NM_RX_IDAC_STATUS_Q 0x3a0 314 #define QSERDES_V5_5NM_RX_IDAC_STATUS_QBAR 0x3a4 315 #define QSERDES_V5_5NM_RX_IDAC_STATUS_A 0x3a8 316 #define QSERDES_V5_5NM_RX_IDAC_STATUS_ABAR 0x3ac 317 #define QSERDES_V5_5NM_RX_IDAC_STATUS_SM_ON 0x3b0 318 #define QSERDES_V5_5NM_RX_IDAC_STATUS_SIGNERROR 0x3b4 319 #define QSERDES_V5_5NM_RX_IVCM_CAL_STATUS 0x3b8 320 #define QSERDES_V5_5NM_RX_IVCM_CAL_DEBUG_STATUS 0x3bc 321 #define QSERDES_V5_5NM_RX_DCC_CAL_STATUS 0x3c0 322 #define QSERDES_V5_5NM_RX_DCC_READ_CODE_STATUS 0x3c4 323 #define QSERDES_V5_5NM_RX_RX_MARG_DEBUG1_STATUS 0x3c8 324 #define QSERDES_V5_5NM_RX_RX_MARG_DEBUG2_STATUS 0x3cc 325 #define QSERDES_V5_5NM_RX_RX_MARG_READ_CODE_STATUS 0x3d0 326 #define QSERDES_V5_5NM_RX_EOM_ERR_CNT_LSB_STATUS 0x3d4 327 #define QSERDES_V5_5NM_RX_EOM_ERR_CNT_MSB_STATUS 0x3d8 328 #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_TUNE_STATUS 0x3dc 329 #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS1_STATUS 0x3e0 330 #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS2_STATUS 0x3e4 331 #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS3_STATUS 0x3e8 332 333 #endif 334