| 8dd256ba | 09-Jan-2023 |
Andre Przywara <andre.przywara@arm.com> |
phy: sun4i-usb: Replace types with explicit quirk flags
So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. Thi
phy: sun4i-usb: Replace types with explicit quirk flags
So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. This does not only look weird, but gets more or more cumbersome to maintain.
Remove the bogus type names altogether, instead introduce flags for each quirk, and explicitly check for them. This improves readability, and simplifies future extensions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230109012223.4079299-4-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 4d0c2165 | 14-Nov-2022 |
Samuel Holland <samuel@sholland.org> |
phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant
A100 features an updated DPHY, which moves PLL control inside the DPHY register space (previously the PLL was controlled from the CCU).
phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant
A100 features an updated DPHY, which moves PLL control inside the DPHY register space (previously the PLL was controlled from the CCU). It also requires a modified analog power-on sequence. This "combo PHY" can also be used as an LVDS PHY, but that is not yet supported by the driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221114022113.31694-9-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 3fd490a7 | 14-Nov-2022 |
Samuel Holland <samuel@sholland.org> |
phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
The A100 variant uses the same values for the timing registers, and it uses the same final power-on sequence, but it needs a differen
phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
The A100 variant uses the same values for the timing registers, and it uses the same final power-on sequence, but it needs a different analog register configuration in the middle. Support this by moving the variant-specific parts to a hook provided by the variant.
Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221114022113.31694-8-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| cb7f49a3 | 14-Nov-2022 |
Samuel Holland <samuel@sholland.org> |
phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
The A100 variant of the DPHY requires configuring the analog registers before setting the global enable bit. Since this order also works
phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
The A100 variant of the DPHY requires configuring the analog registers before setting the global enable bit. Since this order also works on the other variants, always use it, to minimize the differences between them.
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221114022113.31694-7-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 0f607406 | 31-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its various predecessors: it has four full PHYs like the H3, needs some extra bi
phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its various predecessors: it has four full PHYs like the H3, needs some extra bits to be set like the H6, and puts SIDDQ on a different bit like the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new compatible name to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221031111358.3387297-5-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 204642e7 | 03-Feb-2022 |
Samuel Holland <samuel@sholland.org> |
phy: sun4i-usb: Add D1 variant
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances.
Signed-off-by: Samuel Holl
phy: sun4i-usb: Add D1 variant
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances.
Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-4-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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| 1743dea7 | 03-Feb-2022 |
Andre Przywara <andre.przywara@arm.com> |
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY inte
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-3-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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