1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <dt-bindings/phy/phy-qcom-qusb2.h> 23 24 #define QUSB2PHY_PLL 0x0 25 #define QUSB2PHY_PLL_TEST 0x04 26 #define CLK_REF_SEL BIT(7) 27 28 #define QUSB2PHY_PLL_TUNE 0x08 29 #define QUSB2PHY_PLL_USER_CTL1 0x0c 30 #define QUSB2PHY_PLL_USER_CTL2 0x10 31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 32 #define QUSB2PHY_PLL_PWR_CTRL 0x18 33 34 /* QUSB2PHY_PLL_STATUS register bits */ 35 #define PLL_LOCKED BIT(5) 36 37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 38 #define CORE_READY_STATUS BIT(0) 39 40 /* QUSB2PHY_PORT_POWERDOWN register bits */ 41 #define CLAMP_N_EN BIT(5) 42 #define FREEZIO_N BIT(1) 43 #define POWER_DOWN BIT(0) 44 45 /* QUSB2PHY_PWR_CTRL1 register bits */ 46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 47 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 48 49 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 50 51 #define PHY_CLK_SCHEME_SEL BIT(0) 52 53 /* QUSB2PHY_INTR_CTRL register bits */ 54 #define DMSE_INTR_HIGH_SEL BIT(4) 55 #define DPSE_INTR_HIGH_SEL BIT(3) 56 #define CHG_DET_INTR_EN BIT(2) 57 #define DMSE_INTR_EN BIT(1) 58 #define DPSE_INTR_EN BIT(0) 59 60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 61 #define CORE_PLL_EN_FROM_RESET BIT(4) 62 #define CORE_RESET BIT(5) 63 #define CORE_RESET_MUX BIT(6) 64 65 /* QUSB2PHY_IMP_CTRL1 register bits */ 66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 67 #define IMP_RES_OFFSET_SHIFT 0x0 68 69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ 70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) 71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 72 73 /* QUSB2PHY_CHG_CONTROL_2 register bits */ 74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) 75 #define CHG_CTRL2_OFFSET_SHIFT 0x4 76 77 /* QUSB2PHY_PORT_TUNE1 register bits */ 78 #define HSTX_TRIM_MASK GENMASK(7, 4) 79 #define HSTX_TRIM_SHIFT 0x4 80 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 82 #define PREEMPHASIS_EN_SHIFT 0x0 83 84 /* QUSB2PHY_PORT_TUNE2 register bits */ 85 #define HSDISC_TRIM_MASK GENMASK(1, 0) 86 #define HSDISC_TRIM_SHIFT 0x0 87 88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 90 #define QUSB2PHY_PLL_CMODE 0x2c 91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 95 #define QUSB2PHY_PWR_CTRL2 0x214 96 #define QUSB2PHY_IMP_CTRL1 0x220 97 #define QUSB2PHY_IMP_CTRL2 0x224 98 #define QUSB2PHY_CHG_CTRL2 0x23c 99 100 struct qusb2_phy_init_tbl { 101 unsigned int offset; 102 unsigned int val; 103 /* 104 * register part of layout ? 105 * if yes, then offset gives index in the reg-layout 106 */ 107 int in_layout; 108 }; 109 110 #define QUSB2_PHY_INIT_CFG(o, v) \ 111 { \ 112 .offset = o, \ 113 .val = v, \ 114 } 115 116 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 117 { \ 118 .offset = o, \ 119 .val = v, \ 120 .in_layout = 1, \ 121 } 122 123 /* set of registers with offsets different per-PHY */ 124 enum qusb2phy_reg_layout { 125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 126 QUSB2PHY_PLL_STATUS, 127 QUSB2PHY_PORT_TUNE1, 128 QUSB2PHY_PORT_TUNE2, 129 QUSB2PHY_PORT_TUNE3, 130 QUSB2PHY_PORT_TUNE4, 131 QUSB2PHY_PORT_TUNE5, 132 QUSB2PHY_PORT_TEST1, 133 QUSB2PHY_PORT_TEST2, 134 QUSB2PHY_PORT_POWERDOWN, 135 QUSB2PHY_INTR_CTRL, 136 }; 137 138 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { 139 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 140 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8), 141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3), 142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0), 144 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 147 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 148 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 149 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 150 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), 152 }; 153 154 static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] = { 155 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 156 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00), 157 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), 158 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc3), 159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 160 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 161 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 162 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 164 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 165 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 166 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 167 }; 168 169 static const unsigned int ipq6018_regs_layout[] = { 170 [QUSB2PHY_PLL_STATUS] = 0x38, 171 [QUSB2PHY_PORT_TUNE1] = 0x80, 172 [QUSB2PHY_PORT_TUNE2] = 0x84, 173 [QUSB2PHY_PORT_TUNE3] = 0x88, 174 [QUSB2PHY_PORT_TUNE4] = 0x8C, 175 [QUSB2PHY_PORT_TUNE5] = 0x90, 176 [QUSB2PHY_PORT_TEST1] = 0x98, 177 [QUSB2PHY_PORT_TEST2] = 0x9C, 178 [QUSB2PHY_PORT_POWERDOWN] = 0xB4, 179 [QUSB2PHY_INTR_CTRL] = 0xBC, 180 }; 181 182 static const unsigned int msm8996_regs_layout[] = { 183 [QUSB2PHY_PLL_STATUS] = 0x38, 184 [QUSB2PHY_PORT_TUNE1] = 0x80, 185 [QUSB2PHY_PORT_TUNE2] = 0x84, 186 [QUSB2PHY_PORT_TUNE3] = 0x88, 187 [QUSB2PHY_PORT_TUNE4] = 0x8c, 188 [QUSB2PHY_PORT_TUNE5] = 0x90, 189 [QUSB2PHY_PORT_TEST1] = 0xb8, 190 [QUSB2PHY_PORT_TEST2] = 0x9c, 191 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 192 [QUSB2PHY_INTR_CTRL] = 0xbc, 193 }; 194 195 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 196 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 197 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 198 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 199 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 200 201 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 202 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 203 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 204 205 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 206 207 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 208 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 209 }; 210 211 static const unsigned int msm8998_regs_layout[] = { 212 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 213 [QUSB2PHY_PLL_STATUS] = 0x1a0, 214 [QUSB2PHY_PORT_TUNE1] = 0x23c, 215 [QUSB2PHY_PORT_TUNE2] = 0x240, 216 [QUSB2PHY_PORT_TUNE3] = 0x244, 217 [QUSB2PHY_PORT_TUNE4] = 0x248, 218 [QUSB2PHY_PORT_TEST1] = 0x24c, 219 [QUSB2PHY_PORT_TEST2] = 0x250, 220 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 221 [QUSB2PHY_INTR_CTRL] = 0x22c, 222 }; 223 224 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { 225 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13), 226 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 227 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 228 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 229 230 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5), 231 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09), 232 233 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 234 }; 235 236 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { 237 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 238 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), 239 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), 240 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), 241 242 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 243 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 244 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 245 246 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 247 248 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 249 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 250 }; 251 252 static const unsigned int qusb2_v2_regs_layout[] = { 253 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 254 [QUSB2PHY_PLL_STATUS] = 0x1a0, 255 [QUSB2PHY_PORT_TUNE1] = 0x240, 256 [QUSB2PHY_PORT_TUNE2] = 0x244, 257 [QUSB2PHY_PORT_TUNE3] = 0x248, 258 [QUSB2PHY_PORT_TUNE4] = 0x24c, 259 [QUSB2PHY_PORT_TUNE5] = 0x250, 260 [QUSB2PHY_PORT_TEST1] = 0x254, 261 [QUSB2PHY_PORT_TEST2] = 0x258, 262 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 263 [QUSB2PHY_INTR_CTRL] = 0x230, 264 }; 265 266 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { 267 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 268 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 269 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 270 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 271 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 272 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 273 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 274 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 275 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 276 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 277 278 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 279 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 280 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 281 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 282 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 283 284 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 285 }; 286 287 struct qusb2_phy_cfg { 288 const struct qusb2_phy_init_tbl *tbl; 289 /* number of entries in the table */ 290 unsigned int tbl_num; 291 /* offset to PHY_CLK_SCHEME register in TCSR map */ 292 unsigned int clk_scheme_offset; 293 294 /* array of registers with different offsets */ 295 const unsigned int *regs; 296 unsigned int mask_core_ready; 297 unsigned int disable_ctrl; 298 unsigned int autoresume_en; 299 300 /* true if PHY has PLL_TEST register to select clk_scheme */ 301 bool has_pll_test; 302 303 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 304 bool update_tune1_with_efuse; 305 306 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 307 bool has_pll_override; 308 309 /* true if PHY default clk scheme is single-ended */ 310 bool se_clk_scheme_default; 311 }; 312 313 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 314 .tbl = msm8996_init_tbl, 315 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 316 .regs = msm8996_regs_layout, 317 318 .has_pll_test = true, 319 .se_clk_scheme_default = true, 320 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 321 .mask_core_ready = PLL_LOCKED, 322 .autoresume_en = BIT(3), 323 }; 324 325 static const struct qusb2_phy_cfg msm8998_phy_cfg = { 326 .tbl = msm8998_init_tbl, 327 .tbl_num = ARRAY_SIZE(msm8998_init_tbl), 328 .regs = msm8998_regs_layout, 329 330 .disable_ctrl = POWER_DOWN, 331 .mask_core_ready = CORE_READY_STATUS, 332 .has_pll_override = true, 333 .se_clk_scheme_default = true, 334 .autoresume_en = BIT(0), 335 .update_tune1_with_efuse = true, 336 }; 337 338 static const struct qusb2_phy_cfg ipq6018_phy_cfg = { 339 .tbl = ipq6018_init_tbl, 340 .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), 341 .regs = ipq6018_regs_layout, 342 343 .disable_ctrl = POWER_DOWN, 344 .mask_core_ready = PLL_LOCKED, 345 /* autoresume not used */ 346 .autoresume_en = BIT(0), 347 }; 348 349 static const struct qusb2_phy_cfg ipq5424_phy_cfg = { 350 .tbl = ipq5424_init_tbl, 351 .tbl_num = ARRAY_SIZE(ipq5424_init_tbl), 352 .regs = ipq6018_regs_layout, 353 354 .disable_ctrl = POWER_DOWN, 355 .mask_core_ready = PLL_LOCKED, 356 .autoresume_en = BIT(0), 357 }; 358 359 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { 360 .tbl = qusb2_v2_init_tbl, 361 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), 362 .regs = qusb2_v2_regs_layout, 363 364 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 365 POWER_DOWN), 366 .mask_core_ready = CORE_READY_STATUS, 367 .has_pll_override = true, 368 .se_clk_scheme_default = true, 369 .autoresume_en = BIT(0), 370 .update_tune1_with_efuse = true, 371 }; 372 373 static const struct qusb2_phy_cfg sdm660_phy_cfg = { 374 .tbl = msm8996_init_tbl, 375 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 376 .regs = msm8996_regs_layout, 377 378 .has_pll_test = true, 379 .se_clk_scheme_default = false, 380 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 381 .mask_core_ready = PLL_LOCKED, 382 .autoresume_en = BIT(3), 383 }; 384 385 static const struct qusb2_phy_cfg sm6115_phy_cfg = { 386 .tbl = sm6115_init_tbl, 387 .tbl_num = ARRAY_SIZE(sm6115_init_tbl), 388 .regs = msm8996_regs_layout, 389 390 .has_pll_test = true, 391 .se_clk_scheme_default = true, 392 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 393 .mask_core_ready = PLL_LOCKED, 394 .autoresume_en = BIT(3), 395 }; 396 397 static const char * const qusb2_phy_vreg_names[] = { 398 "vdd", "vdda-pll", "vdda-phy-dpdm", 399 }; 400 401 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 402 403 /* struct override_param - structure holding qusb2 v2 phy overriding param 404 * set override true if the device tree property exists and read and assign 405 * to value 406 */ 407 struct override_param { 408 bool override; 409 u8 value; 410 }; 411 412 /*struct override_params - structure holding qusb2 v2 phy overriding params 413 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register 414 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register 415 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register 416 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 417 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register 418 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register 419 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register 420 */ 421 struct override_params { 422 struct override_param imp_res_offset; 423 struct override_param hstx_trim; 424 struct override_param preemphasis; 425 struct override_param preemphasis_width; 426 struct override_param bias_ctrl; 427 struct override_param charge_ctrl; 428 struct override_param hsdisc_trim; 429 }; 430 431 /** 432 * struct qusb2_phy - structure holding qusb2 phy attributes 433 * 434 * @phy: generic phy 435 * @base: iomapped memory space for qubs2 phy 436 * 437 * @cfg_ahb_clk: AHB2PHY interface clock 438 * @ref_clk: phy reference clock 439 * @iface_clk: phy interface clock 440 * @phy_reset: phy reset control 441 * @vregs: regulator supplies bulk data 442 * 443 * @tcsr: TCSR syscon register map 444 * @cell: nvmem cell containing phy tuning value 445 * 446 * @overrides: pointer to structure for all overriding tuning params 447 * 448 * @cfg: phy config data 449 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 450 * @phy_initialized: indicate if PHY has been initialized 451 * @mode: current PHY mode 452 */ 453 struct qusb2_phy { 454 struct phy *phy; 455 void __iomem *base; 456 457 struct clk *cfg_ahb_clk; 458 struct clk *ref_clk; 459 struct clk *iface_clk; 460 struct reset_control *phy_reset; 461 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 462 463 struct regmap *tcsr; 464 struct nvmem_cell *cell; 465 466 struct override_params overrides; 467 468 const struct qusb2_phy_cfg *cfg; 469 bool has_se_clk_scheme; 470 bool phy_initialized; 471 enum phy_mode mode; 472 }; 473 474 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 475 u32 val, u32 mask) 476 { 477 u32 reg; 478 479 reg = readl(base + offset); 480 reg &= ~mask; 481 reg |= val & mask; 482 writel(reg, base + offset); 483 484 /* Ensure above write is completed */ 485 readl(base + offset); 486 } 487 488 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 489 { 490 u32 reg; 491 492 reg = readl(base + offset); 493 reg |= val; 494 writel(reg, base + offset); 495 496 /* Ensure above write is completed */ 497 readl(base + offset); 498 } 499 500 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 501 { 502 u32 reg; 503 504 reg = readl(base + offset); 505 reg &= ~val; 506 writel(reg, base + offset); 507 508 /* Ensure above write is completed */ 509 readl(base + offset); 510 } 511 512 static inline 513 void qcom_qusb2_phy_configure(void __iomem *base, 514 const unsigned int *regs, 515 const struct qusb2_phy_init_tbl tbl[], int num) 516 { 517 int i; 518 519 for (i = 0; i < num; i++) { 520 if (tbl[i].in_layout) 521 writel(tbl[i].val, base + regs[tbl[i].offset]); 522 else 523 writel(tbl[i].val, base + tbl[i].offset); 524 } 525 } 526 527 /* 528 * Update board specific PHY tuning override values if specified from 529 * device tree. 530 */ 531 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 532 { 533 const struct qusb2_phy_cfg *cfg = qphy->cfg; 534 struct override_params *or = &qphy->overrides; 535 536 if (or->imp_res_offset.override) 537 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 538 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, 539 IMP_RES_OFFSET_MASK); 540 541 if (or->bias_ctrl.override) 542 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, 543 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, 544 BIAS_CTRL2_RES_OFFSET_MASK); 545 546 if (or->charge_ctrl.override) 547 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, 548 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, 549 CHG_CTRL2_OFFSET_MASK); 550 551 if (or->hstx_trim.override) 552 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 553 or->hstx_trim.value << HSTX_TRIM_SHIFT, 554 HSTX_TRIM_MASK); 555 556 if (or->preemphasis.override) 557 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 558 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, 559 PREEMPHASIS_EN_MASK); 560 561 if (or->preemphasis_width.override) { 562 if (or->preemphasis_width.value == 563 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 564 qusb2_setbits(qphy->base, 565 cfg->regs[QUSB2PHY_PORT_TUNE1], 566 PREEMPH_WIDTH_HALF_BIT); 567 else 568 qusb2_clrbits(qphy->base, 569 cfg->regs[QUSB2PHY_PORT_TUNE1], 570 PREEMPH_WIDTH_HALF_BIT); 571 } 572 573 if (or->hsdisc_trim.override) 574 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 575 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, 576 HSDISC_TRIM_MASK); 577 } 578 579 /* 580 * Fetches HS Tx tuning value from nvmem and sets the 581 * QUSB2PHY_PORT_TUNE1/2 register. 582 * For error case, skip setting the value and use the default value. 583 */ 584 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 585 { 586 struct device *dev = &qphy->phy->dev; 587 const struct qusb2_phy_cfg *cfg = qphy->cfg; 588 u8 *val, hstx_trim; 589 590 /* efuse register is optional */ 591 if (!qphy->cell) 592 return; 593 594 /* 595 * Read efuse register having TUNE2/1 parameter's high nibble. 596 * If efuse register shows value as 0x0 (indicating value is not 597 * fused), or if we fail to find a valid efuse register setting, 598 * then use default value for high nibble that we have already 599 * set while configuring the phy. 600 */ 601 val = nvmem_cell_read(qphy->cell, NULL); 602 if (IS_ERR(val)) { 603 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 604 return; 605 } 606 hstx_trim = val[0]; 607 kfree(val); 608 if (!hstx_trim) { 609 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 610 return; 611 } 612 613 /* Fused TUNE1/2 value is the higher nibble only */ 614 if (cfg->update_tune1_with_efuse) 615 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 616 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 617 else 618 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 619 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 620 } 621 622 static int qusb2_phy_set_mode(struct phy *phy, 623 enum phy_mode mode, int submode) 624 { 625 struct qusb2_phy *qphy = phy_get_drvdata(phy); 626 627 qphy->mode = mode; 628 629 return 0; 630 } 631 632 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 633 { 634 struct qusb2_phy *qphy = dev_get_drvdata(dev); 635 const struct qusb2_phy_cfg *cfg = qphy->cfg; 636 u32 intr_mask; 637 638 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 639 640 if (!qphy->phy_initialized) { 641 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 642 return 0; 643 } 644 645 /* 646 * Enable DP/DM interrupts to detect line state changes based on current 647 * speed. In other words, enable the triggers _opposite_ of what the 648 * current D+/D- levels are e.g. if currently D+ high, D- low 649 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 650 */ 651 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 652 switch (qphy->mode) { 653 case PHY_MODE_USB_HOST_HS: 654 case PHY_MODE_USB_HOST_FS: 655 case PHY_MODE_USB_DEVICE_HS: 656 case PHY_MODE_USB_DEVICE_FS: 657 intr_mask |= DMSE_INTR_HIGH_SEL; 658 break; 659 case PHY_MODE_USB_HOST_LS: 660 case PHY_MODE_USB_DEVICE_LS: 661 intr_mask |= DPSE_INTR_HIGH_SEL; 662 break; 663 default: 664 /* No device connected, enable both DP/DM high interrupt */ 665 intr_mask |= DMSE_INTR_HIGH_SEL; 666 intr_mask |= DPSE_INTR_HIGH_SEL; 667 break; 668 } 669 670 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 671 672 /* hold core PLL into reset */ 673 if (cfg->has_pll_override) { 674 qusb2_setbits(qphy->base, 675 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 676 CORE_PLL_EN_FROM_RESET | CORE_RESET | 677 CORE_RESET_MUX); 678 } 679 680 /* enable phy auto-resume only if device is connected on bus */ 681 if (qphy->mode != PHY_MODE_INVALID) { 682 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 683 cfg->autoresume_en); 684 /* Autoresume bit has to be toggled in order to enable it */ 685 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 686 cfg->autoresume_en); 687 } 688 689 if (!qphy->has_se_clk_scheme) 690 clk_disable_unprepare(qphy->ref_clk); 691 692 clk_disable_unprepare(qphy->cfg_ahb_clk); 693 clk_disable_unprepare(qphy->iface_clk); 694 695 return 0; 696 } 697 698 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 699 { 700 struct qusb2_phy *qphy = dev_get_drvdata(dev); 701 const struct qusb2_phy_cfg *cfg = qphy->cfg; 702 int ret; 703 704 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 705 706 if (!qphy->phy_initialized) { 707 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 708 return 0; 709 } 710 711 ret = clk_prepare_enable(qphy->iface_clk); 712 if (ret) { 713 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 714 return ret; 715 } 716 717 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 718 if (ret) { 719 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 720 goto disable_iface_clk; 721 } 722 723 if (!qphy->has_se_clk_scheme) { 724 ret = clk_prepare_enable(qphy->ref_clk); 725 if (ret) { 726 dev_err(dev, "failed to enable ref clk, %d\n", ret); 727 goto disable_ahb_clk; 728 } 729 } 730 731 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 732 733 /* bring core PLL out of reset */ 734 if (cfg->has_pll_override) { 735 qusb2_clrbits(qphy->base, 736 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 737 CORE_RESET | CORE_RESET_MUX); 738 } 739 740 return 0; 741 742 disable_ahb_clk: 743 clk_disable_unprepare(qphy->cfg_ahb_clk); 744 disable_iface_clk: 745 clk_disable_unprepare(qphy->iface_clk); 746 747 return ret; 748 } 749 750 static int qusb2_phy_init(struct phy *phy) 751 { 752 struct qusb2_phy *qphy = phy_get_drvdata(phy); 753 const struct qusb2_phy_cfg *cfg = qphy->cfg; 754 unsigned int val = 0; 755 unsigned int clk_scheme; 756 int ret; 757 758 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 759 760 /* turn on regulator supplies */ 761 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 762 if (ret) 763 return ret; 764 765 ret = clk_prepare_enable(qphy->iface_clk); 766 if (ret) { 767 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 768 goto poweroff_phy; 769 } 770 771 /* enable ahb interface clock to program phy */ 772 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 773 if (ret) { 774 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 775 goto disable_iface_clk; 776 } 777 778 /* Perform phy reset */ 779 ret = reset_control_assert(qphy->phy_reset); 780 if (ret) { 781 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 782 goto disable_ahb_clk; 783 } 784 785 /* 100 us delay to keep PHY in reset mode */ 786 usleep_range(100, 150); 787 788 ret = reset_control_deassert(qphy->phy_reset); 789 if (ret) { 790 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 791 goto disable_ahb_clk; 792 } 793 794 /* Disable the PHY */ 795 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 796 qphy->cfg->disable_ctrl); 797 798 if (cfg->has_pll_test) { 799 /* save reset value to override reference clock scheme later */ 800 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 801 } 802 803 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 804 cfg->tbl_num); 805 806 /* Override board specific PHY tuning values */ 807 qusb2_phy_override_phy_params(qphy); 808 809 /* Set efuse value for tuning the PHY */ 810 qusb2_phy_set_tune2_param(qphy); 811 812 /* Enable the PHY */ 813 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 814 POWER_DOWN); 815 816 /* Required to get phy pll lock successfully */ 817 usleep_range(150, 160); 818 819 /* 820 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME 821 * register in the TCSR so, if there's none, use the default 822 * value hardcoded in the configuration. 823 */ 824 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; 825 826 /* 827 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 828 * clock scheme is selected. If yes, then disable differential 829 * ref_clk and use single-ended clock, otherwise use differential 830 * ref_clk only. 831 */ 832 if (qphy->tcsr) { 833 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 834 &clk_scheme); 835 if (ret) { 836 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 837 goto assert_phy_reset; 838 } 839 840 /* is it a differential clock scheme ? */ 841 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 842 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 843 __func__); 844 qphy->has_se_clk_scheme = false; 845 } else { 846 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 847 __func__); 848 } 849 } 850 851 if (!qphy->has_se_clk_scheme) { 852 ret = clk_prepare_enable(qphy->ref_clk); 853 if (ret) { 854 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 855 ret); 856 goto assert_phy_reset; 857 } 858 } 859 860 if (cfg->has_pll_test) { 861 if (!qphy->has_se_clk_scheme) 862 val &= ~CLK_REF_SEL; 863 else 864 val |= CLK_REF_SEL; 865 866 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 867 868 /* ensure above write is through */ 869 readl(qphy->base + QUSB2PHY_PLL_TEST); 870 } 871 872 /* Required to get phy pll lock successfully */ 873 usleep_range(100, 110); 874 875 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 876 if (!(val & cfg->mask_core_ready)) { 877 dev_err(&phy->dev, 878 "QUSB2PHY pll lock failed: status reg = %x\n", val); 879 ret = -EBUSY; 880 goto disable_ref_clk; 881 } 882 qphy->phy_initialized = true; 883 884 return 0; 885 886 disable_ref_clk: 887 if (!qphy->has_se_clk_scheme) 888 clk_disable_unprepare(qphy->ref_clk); 889 assert_phy_reset: 890 reset_control_assert(qphy->phy_reset); 891 disable_ahb_clk: 892 clk_disable_unprepare(qphy->cfg_ahb_clk); 893 disable_iface_clk: 894 clk_disable_unprepare(qphy->iface_clk); 895 poweroff_phy: 896 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 897 898 return ret; 899 } 900 901 static int qusb2_phy_exit(struct phy *phy) 902 { 903 struct qusb2_phy *qphy = phy_get_drvdata(phy); 904 905 /* Disable the PHY */ 906 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 907 qphy->cfg->disable_ctrl); 908 909 if (!qphy->has_se_clk_scheme) 910 clk_disable_unprepare(qphy->ref_clk); 911 912 reset_control_assert(qphy->phy_reset); 913 914 clk_disable_unprepare(qphy->cfg_ahb_clk); 915 clk_disable_unprepare(qphy->iface_clk); 916 917 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 918 919 qphy->phy_initialized = false; 920 921 return 0; 922 } 923 924 static const struct phy_ops qusb2_phy_gen_ops = { 925 .init = qusb2_phy_init, 926 .exit = qusb2_phy_exit, 927 .set_mode = qusb2_phy_set_mode, 928 .owner = THIS_MODULE, 929 }; 930 931 static const struct of_device_id qusb2_phy_of_match_table[] = { 932 { 933 .compatible = "qcom,ipq5424-qusb2-phy", 934 .data = &ipq5424_phy_cfg, 935 }, { 936 .compatible = "qcom,ipq6018-qusb2-phy", 937 .data = &ipq6018_phy_cfg, 938 }, { 939 .compatible = "qcom,ipq8074-qusb2-phy", 940 .data = &msm8996_phy_cfg, 941 }, { 942 .compatible = "qcom,ipq9574-qusb2-phy", 943 .data = &ipq6018_phy_cfg, 944 }, { 945 .compatible = "qcom,msm8953-qusb2-phy", 946 .data = &msm8996_phy_cfg, 947 }, { 948 .compatible = "qcom,msm8996-qusb2-phy", 949 .data = &msm8996_phy_cfg, 950 }, { 951 .compatible = "qcom,msm8998-qusb2-phy", 952 .data = &msm8998_phy_cfg, 953 }, { 954 .compatible = "qcom,qcm2290-qusb2-phy", 955 .data = &sm6115_phy_cfg, 956 }, { 957 .compatible = "qcom,sdm660-qusb2-phy", 958 .data = &sdm660_phy_cfg, 959 }, { 960 .compatible = "qcom,sm4250-qusb2-phy", 961 .data = &sm6115_phy_cfg, 962 }, { 963 .compatible = "qcom,sm6115-qusb2-phy", 964 .data = &sm6115_phy_cfg, 965 }, { 966 /* 967 * Deprecated. Only here to support legacy device 968 * trees that didn't include "qcom,qusb2-v2-phy" 969 */ 970 .compatible = "qcom,sdm845-qusb2-phy", 971 .data = &qusb2_v2_phy_cfg, 972 }, { 973 .compatible = "qcom,qusb2-v2-phy", 974 .data = &qusb2_v2_phy_cfg, 975 }, 976 { }, 977 }; 978 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 979 980 static const struct dev_pm_ops qusb2_phy_pm_ops = { 981 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 982 qusb2_phy_runtime_resume, NULL) 983 }; 984 985 static int qusb2_phy_probe(struct platform_device *pdev) 986 { 987 struct device *dev = &pdev->dev; 988 struct qusb2_phy *qphy; 989 struct phy_provider *phy_provider; 990 struct phy *generic_phy; 991 int ret, i; 992 int num; 993 u32 value; 994 struct override_params *or; 995 996 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 997 if (!qphy) 998 return -ENOMEM; 999 or = &qphy->overrides; 1000 1001 qphy->base = devm_platform_ioremap_resource(pdev, 0); 1002 if (IS_ERR(qphy->base)) 1003 return PTR_ERR(qphy->base); 1004 1005 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 1006 if (IS_ERR(qphy->cfg_ahb_clk)) 1007 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), 1008 "failed to get cfg ahb clk\n"); 1009 1010 qphy->ref_clk = devm_clk_get(dev, "ref"); 1011 if (IS_ERR(qphy->ref_clk)) 1012 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), 1013 "failed to get ref clk\n"); 1014 1015 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); 1016 if (IS_ERR(qphy->iface_clk)) 1017 return PTR_ERR(qphy->iface_clk); 1018 1019 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 1020 if (IS_ERR(qphy->phy_reset)) { 1021 dev_err(dev, "failed to get phy core reset\n"); 1022 return PTR_ERR(qphy->phy_reset); 1023 } 1024 1025 num = ARRAY_SIZE(qphy->vregs); 1026 for (i = 0; i < num; i++) 1027 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 1028 1029 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 1030 if (ret) 1031 return dev_err_probe(dev, ret, 1032 "failed to get regulator supplies\n"); 1033 1034 /* Get the specific init parameters of QMP phy */ 1035 qphy->cfg = of_device_get_match_data(dev); 1036 1037 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 1038 "qcom,tcsr-syscon"); 1039 if (IS_ERR(qphy->tcsr)) { 1040 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 1041 qphy->tcsr = NULL; 1042 } 1043 1044 qphy->cell = devm_nvmem_cell_get(dev, NULL); 1045 if (IS_ERR(qphy->cell)) { 1046 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 1047 return -EPROBE_DEFER; 1048 qphy->cell = NULL; 1049 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 1050 } 1051 1052 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 1053 &value)) { 1054 or->imp_res_offset.value = (u8)value; 1055 or->imp_res_offset.override = true; 1056 } 1057 1058 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", 1059 &value)) { 1060 or->bias_ctrl.value = (u8)value; 1061 or->bias_ctrl.override = true; 1062 } 1063 1064 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", 1065 &value)) { 1066 or->charge_ctrl.value = (u8)value; 1067 or->charge_ctrl.override = true; 1068 } 1069 1070 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 1071 &value)) { 1072 or->hstx_trim.value = (u8)value; 1073 or->hstx_trim.override = true; 1074 } 1075 1076 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 1077 &value)) { 1078 or->preemphasis.value = (u8)value; 1079 or->preemphasis.override = true; 1080 } 1081 1082 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 1083 &value)) { 1084 or->preemphasis_width.value = (u8)value; 1085 or->preemphasis_width.override = true; 1086 } 1087 1088 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", 1089 &value)) { 1090 or->hsdisc_trim.value = (u8)value; 1091 or->hsdisc_trim.override = true; 1092 } 1093 1094 pm_runtime_set_active(dev); 1095 pm_runtime_enable(dev); 1096 /* 1097 * Prevent runtime pm from being ON by default. Users can enable 1098 * it using power/control in sysfs. 1099 */ 1100 pm_runtime_forbid(dev); 1101 1102 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 1103 if (IS_ERR(generic_phy)) { 1104 ret = PTR_ERR(generic_phy); 1105 dev_err(dev, "failed to create phy, %d\n", ret); 1106 pm_runtime_disable(dev); 1107 return ret; 1108 } 1109 qphy->phy = generic_phy; 1110 1111 dev_set_drvdata(dev, qphy); 1112 phy_set_drvdata(generic_phy, qphy); 1113 1114 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1115 if (!IS_ERR(phy_provider)) 1116 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); 1117 else 1118 pm_runtime_disable(dev); 1119 1120 return PTR_ERR_OR_ZERO(phy_provider); 1121 } 1122 1123 static struct platform_driver qusb2_phy_driver = { 1124 .probe = qusb2_phy_probe, 1125 .driver = { 1126 .name = "qcom-qusb2-phy", 1127 .pm = &qusb2_phy_pm_ops, 1128 .of_match_table = qusb2_phy_of_match_table, 1129 }, 1130 }; 1131 1132 module_platform_driver(qusb2_phy_driver); 1133 1134 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1135 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 1136 MODULE_LICENSE("GPL v2"); 1137