| 8871389d | 19-Jan-2026 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"
Prefer the new "rx-polarity" and "tx-polarity" properties, which in this case have the advantage that polarity inversion can be specified per dir
net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"
Prefer the new "rx-polarity" and "tx-polarity" properties, which in this case have the advantage that polarity inversion can be specified per direction (and per protocol, although this isn't useful here).
We use the vendor specific ones as fallback if the standard description doesn't exist.
Daniel, referring to the Mediatek SDK, clarifies that the combined SGMII_PN_SWAP_TX_RX register field should be split like this: bit 0 is TX and bit 1 is RX: https://lore.kernel.org/linux-phy/aSW--slbJWpXK0nv@makrotopia.org/
Suggested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20260119091220.1493761-6-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| 3f29dd34 | 21-Nov-2025 |
Alexander Duyck <alexanderduyck@fb.com> |
net: pcs: xpcs: Add support for FBNIC 25G, 50G, 100G PMD
The fbnic driver is planning to make use of the XPCS driver to enable support for PCS and better integration with phylink. To do this though
net: pcs: xpcs: Add support for FBNIC 25G, 50G, 100G PMD
The fbnic driver is planning to make use of the XPCS driver to enable support for PCS and better integration with phylink. To do this though we will need to enable several workarounds since the PMD interface for fbnic is likely to be unique since it is a mix of two different vendor products with a unique wrapper around the IP.
I have generated a PHY identifier based on IEEE 802.3-2022 22.2.4.3.1 using an OUI belonging to Meta Platforms and used with our NICs. Using this we will provide it as the PMD ID via the SW based MDIO interface so that the fbnic device can be identified and necessary workarounds enabled in the XPCS driver.
As an initial workaround this change adds an exception so that soft_reset is not set when the driver is initially bound to the PCS.
In addition I have added logic to integrate the PMD Rx signal detect state into the link state for the PCS. With this we can avoid the link coming up too soon on the FBNIC PMD and as a result of it being in the training state so we can avoid link flaps.
Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Link: https://patch.msgid.link/176374321695.959489.6648161125012056619.stgit@ahduyck-xeon-server.home.arpa Signed-off-by: Paolo Abeni <pabeni@redhat.com>
show more ...
|
| 39e13817 | 21-Nov-2025 |
Alexander Duyck <alexanderduyck@fb.com> |
net: pcs: xpcs: Fix PMA identifier handling in XPCS
The XPCS driver was mangling the PMA identifier as the original code appears to have been focused on just capturing the OUI. Rather than store a m
net: pcs: xpcs: Fix PMA identifier handling in XPCS
The XPCS driver was mangling the PMA identifier as the original code appears to have been focused on just capturing the OUI. Rather than store a mangled ID it is better to work with the actual PMA ID and instead just mask out the values that don't apply rather than shifting them and reordering them as you still don't get the original OUI for the NIC without having to bitswap the values as per the definition of the layout in IEEE 802.3-2022 22.2.4.3.1.
By laying it out as it was in the hardware it is also less likely for us to have an unintentional collision as the enum values will occupy the revision number area while the OUI occupies the upper 22 bits.
Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Link: https://patch.msgid.link/176374320920.959489.17267159479370601070.stgit@ahduyck-xeon-server.home.arpa Signed-off-by: Paolo Abeni <pabeni@redhat.com>
show more ...
|
| 08f89e42 | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Add RZ/T2H MIIC support
Add support for the Renesas RZ/T2H MIIC by defining SoC-specific modctrl match tables, register map, and string representations for converters and ports.
net: pcs: rzn1-miic: Add RZ/T2H MIIC support
Add support for the Renesas RZ/T2H MIIC by defining SoC-specific modctrl match tables, register map, and string representations for converters and ports.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| 41974731 | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock
Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to stru
net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock
Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so the driver can either perform the traditional global unlock sequence (as used on RZ/N1) or use a different policy for other SoCs (for example RZ/T2H, which does not require leaving registers unlocked).
miic_reg_writel() now calls the per-SoC miic_write callback to perform register writes. Provide miic_reg_writel_unlocked() as the default writer and set it for the RZ/N1 OF data so existing platforms keep the same behaviour. Add a miic_unlock_regs() helper that implements the accessory register unlock sequence so the unlock/lock sequence can be reused where needed (for example when a SoC requires explicit unlock/lock around individual accesses).
This change is preparatory work for supporting RZ/T2H.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| 882a8bb0 | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Add support to handle resets
Add reset-line handling to the RZN1 MIIC driver and move reset configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (= 2), add storage fo
net: pcs: rzn1-miic: Add support to handle resets
Add reset-line handling to the RZN1 MIIC driver and move reset configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (= 2), add storage for reset_control_bulk_data in struct miic and add reset_ids and reset_count fields to miic_of_data.
When reset_ids are present in the OF data, the driver obtains the reset lines with devm_reset_control_bulk_get_exclusive(), deasserts them during probe and registers a devres action to assert them on remove or on error.
This change is preparatory work to support the RZ/T2H SoC, which exposes two reset lines for the ETHSS IP. The driver remains backward compatible for platforms that do not provide reset lines.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| 6245237a | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Make switch mode mask SoC-specific
Move the hardcoded switch mode mask definition into the SoC-specific miic_of_data structure. This allows each SoC to define its own mask value
net: pcs: rzn1-miic: Make switch mode mask SoC-specific
Move the hardcoded switch mode mask definition into the SoC-specific miic_of_data structure. This allows each SoC to define its own mask value rather than relying on a single fixed constant. For RZ/N1 the mask remains GENMASK(4, 0).
This is in preparation for adding support for RZ/T2H, where the switch mode mask is GENMASK(2, 0).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| c112520d | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: move port range handling into SoC data
Define per-SoC miic_port_start and miic_port_max fields in struct miic_of_data and use them to validate the device-tree "reg" port number
net: pcs: rzn1-miic: move port range handling into SoC data
Define per-SoC miic_port_start and miic_port_max fields in struct miic_of_data and use them to validate the device-tree "reg" port number and to compute the driver's internal zero-based port index as (port - miic_port_start). Replace uses of the hard-coded MIIC_MAX_NR_PORTS with the SoC-provided miic_port_max when iterating over ports.
On RZ/N1 the MIIC ports are numbered 1..5, whereas RZ/T2H numbers its MIIC ports 0..3. By making the port base and range part of the OF data the driver no longer assumes a fixed numbering scheme and can support SoCs that enumerate ports from either zero or one and that expose different numbers of ports.
This change is preparatory work for adding RZ/T2H support.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| f39e968d | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Move configuration data to SoC-specific struct
Move configuration data such as the modctrl matching table, converter count, and string lookup tables into the SoC-specific miic_o
net: pcs: rzn1-miic: Move configuration data to SoC-specific struct
Move configuration data such as the modctrl matching table, converter count, and string lookup tables into the SoC-specific miic_of_data structure. Update the helper functions to use the per-SoC configuration instead of relying on fixed-size arrays or global tables, and allocate DT configuration memory dynamically.
This refactoring keeps the existing RZ/N1 support intact while preparing the driver to handle the different configuration requirements of the RZ/T2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|
| 861d10f0 | 10-Sep-2025 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
net: pcs: rzn1-miic: Add missing include files
The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK() macros but does not explicitly include the headers where they are defined. Add
net: pcs: rzn1-miic: Add missing include files
The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK() macros but does not explicitly include the headers where they are defined. Add the missing <linux/array_size.h> and <linux/bits.h> includes.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20250910204132.319975-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
show more ...
|