drm/amd/display: Fix warnings[Why & How]Fix various warnings related to unsigned/signed mismatches- Consistently use the same signedness for a given value- Explcitly cast between types when ne
drm/amd/display: Fix warnings[Why & How]Fix various warnings related to unsigned/signed mismatches- Consistently use the same signedness for a given value- Explcitly cast between types when neededReviewed-by: Dillon Varone <dillon.varone@amd.com>Signed-off-by: Clay King <clayking@amd.com>Signed-off-by: James Lin <pinglei.lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drm/amd/display: Rework YCbCr422 DSC policy- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSCenabled based on DSC caps and stream signal typeReviewed-by: Wenjing Liu <wenjing.li
drm/amd/display: Rework YCbCr422 DSC policy- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSCenabled based on DSC caps and stream signal typeReviewed-by: Wenjing Liu <wenjing.liu@amd.com>Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>Signed-off-by: Roman Li <roman.li@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Revert "drm/amd/display: Rework YCbCr422 DSC policy"Revert commit 19b79e4f2182 ("drm/amd/display: Rework YCbCr422 DSC policy")Reason for Revert:This commit is causing compliance failuresReview
Revert "drm/amd/display: Rework YCbCr422 DSC policy"Revert commit 19b79e4f2182 ("drm/amd/display: Rework YCbCr422 DSC policy")Reason for Revert:This commit is causing compliance failuresReviewed-by: Wenjing Liu <wenjing.liu@amd.com>Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Rework YCbCr422 DSC policy- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSCenabled based on DSC caps and stream signal typeReviewed-by: Wenjing Liu <wenjing.liu@amd.com>Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: refactor DSC cap calculation for dcn35why:dcn35 currently uses a hardcoded DSC display clock value which is incorrectfor some asic types. Newer DCN versions retrieve dsc display
drm/amd/display: refactor DSC cap calculation for dcn35why:dcn35 currently uses a hardcoded DSC display clock value which is incorrectfor some asic types. Newer DCN versions retrieve dsc display clock fromclk_mgr. The same can be done for dcn35.how:Refactor the DSC cap calculation using pre-existing logic.Handle ODM combine requirements in dc_dsc.c.Replace hardcoded display clock with actual value retrieved from clk_mgr.Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Reviewed-by: Charlene Liu <charlene.liu@amd.com>Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>Signed-off-by: Mohit Bawa <Mohit.Bawa@amd.com>Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add more DC HW state info to underflow logging[Why]Debugging underflow issues frequently requires knowing theHW state at the time of underflow. To enable capturing thisHW state
drm/amd/display: Add more DC HW state info to underflow logging[Why]Debugging underflow issues frequently requires knowing theHW state at the time of underflow. To enable capturing thisHW state information, interface functions are needed for thevarious DC HW blocks.[How]This change adds the interface functions to read HW state forthe following DC HW blocks:- HUBBUB- HUBP- DPP- MPC- OPP- DSC- OPTC- DCCGReviewed-by: George Shen <george.shen@amd.com>Signed-off-by: Karen Chen <Karen.Chen@amd.com>Signed-off-by: Wayne Lin <wayne.lin@amd.com>Tested-by: Dan Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Reset DSC memory status[WHY]When system exits idle state followed by enabling the display,DSC memory may still be forced in a deep sleep or shutdown state.Intermittent DSC corr
drm/amd/display: Reset DSC memory status[WHY]When system exits idle state followed by enabling the display,DSC memory may still be forced in a deep sleep or shutdown state.Intermittent DSC corruption is seen when display is visible.[HOW]When DSC is enabled, reset dsc memory to force and disable status.Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgSigned-off-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Duncan Ma <duncan.ma@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Refactor DSC into component folder[why]To refactor DSC and make DSC files unit testable.[how]moved the dcnxx_dsc.c and .h filesinto corresponding dcn folders insidethe dsc
drm/amd/display: Refactor DSC into component folder[why]To refactor DSC and make DSC files unit testable.[how]moved the dcnxx_dsc.c and .h filesinto corresponding dcn folders insidethe dsc and cleared the linkage errors.Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Bhuvana Chandra Pinninti <bhuvanachandra.pinninti@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>