| e1311954 | 21-May-2026 |
Joey Lu <a0987203069@gmail.com> |
clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic
ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest() unconditionally before the switch statement, and then every case branch
clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic
ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest() unconditionally before the switch statement, and then every case branch overwrote pll_freq by reading the current hardware registers. For CAPLL and DDRPLL this means find_closest() ran unnecessarily (and incorrectly, since those PLLs are read-only) and its result was silently discarded.
Fix by moving the find_closest() call inside the APLL/EPLL/VPLL branch where it belongs. Group CAPLL and DDRPLL together as read-only PLLs that simply report their current rate; handle them with an explicit if/else to keep the CAPLL (SMIC design) and DDRPLL (standard design) paths distinct.
Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu <a0987203069@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
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| 26de5aed | 21-May-2026 |
Joey Lu <a0987203069@gmail.com> |
clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc
PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits. The hardware fractional field occupies bits [31:8] (24
clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc
PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits. The hardware fractional field occupies bits [31:8] (24 bits), so the mask must be GENMASK(31, 8).
The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC) as the denominator to obtain 2 decimal places. With the corrected 24-bit mask the old divisor is wrong; replace the arithmetic with a proper 24-bit fixed-point rounding to 3 decimal places using the kernel's DIV_ROUND_CLOSEST_ULL helper:
n_frac = n * 1000 + DIV_ROUND_CLOSEST_ULL(x * 1000, 1 << 24)
Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu <a0987203069@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
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| cd9e9bbf | 11-Aug-2025 |
Brian Masney <bmasney@redhat.com> |
clk: nuvoton: ma35d1-pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle sema
clk: nuvoton: ma35d1-pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
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| f50a000b | 22-Jun-2023 |
Jacky Huang <ychuang3@nuvoton.com> |
clk: nuvoton: Use clk_parent_data instead of string for parent clock
For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments,
clk: nuvoton: Use clk_parent_data instead of string for parent clock
For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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| ebd617b6 | 22-Jun-2023 |
Jacky Huang <ychuang3@nuvoton.com> |
clk: nuvoton: Update all constant hex values to lowercase
The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be low
clk: nuvoton: Update all constant hex values to lowercase
The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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