| 48c7771b | 05-May-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix pic64gx gpio interrupt-cells
As the pic64gx devicetree files got added in parallel to the
GPIO interrupt-cells being fixed for PolarFire SoC, they didn't get
changed to th
riscv: dts: microchip: fix pic64gx gpio interrupt-cells
As the pic64gx devicetree files got added in parallel to the
GPIO interrupt-cells being fixed for PolarFire SoC, they didn't get
changed to the correct values. Fix them now.
Fixes: 7219d20f9f421 ("riscv: dts: microchip: add pic64gx and its curiosity kit")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| bba74984 | 05-Mar-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add gpio line names on beaglev-fire
GPIO controller 2 has the gpio-line-names property, but the two other
controllers do not. Add the property for these controllers too.
Sign
riscv: dts: microchip: add gpio line names on beaglev-fire
GPIO controller 2 has the gpio-line-names property, but the two other
controllers do not. Add the property for these controllers too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 11cec5d0 | 05-Mar-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add adc interrupt on beaglev-fire
The mcp3464r on the beaglev-fire has its interrupt wired up, but not
present in the devicetree. Add it.
Signed-off-by: Conor Dooley <conor.d
riscv: dts: microchip: add adc interrupt on beaglev-fire
The mcp3464r on the beaglev-fire has its interrupt wired up, but not
present in the devicetree. Add it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 044427ff | 05-Mar-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: clean up beaglev-fire regulator node names
Recently the binding for regulator-fixed introduced preferred naming, in
the regulator-XvY format. Change the existing regulators to
riscv: dts: microchip: clean up beaglev-fire regulator node names
Recently the binding for regulator-fixed introduced preferred naming, in
the regulator-XvY format. Change the existing regulators to match this
pattern.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 7ab03283 | 05-Mar-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: remove gpio hogs from beaglev-fire
sd-det-hog should be cd-gpios, but when the mmc-spi-slot was added, the
"cd-" prefix was omitted and the collision with the hog was not noti
riscv: dts: microchip: remove gpio hogs from beaglev-fire
sd-det-hog should be cd-gpios, but when the mmc-spi-slot was added, the
"cd-" prefix was omitted and the collision with the hog was not noticed.
vio-enable-hog is just a regulator that can be modelled as such.
Fixes: 1088d49b62648 ("riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 79b731da | 19-Mar-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: gpio controllers on mpfs need 2 interrupt cells
The platform has variable interrupt types for GPIO interrupts, in
addition to having multiple lines per GPIO controller. Two in
riscv: dts: microchip: gpio controllers on mpfs need 2 interrupt cells
The platform has variable interrupt types for GPIO interrupts, in
addition to having multiple lines per GPIO controller. Two interrupt
cells are required.
Fixes: 528a5b1f2556d ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4ce4a46c | 07-Apr-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
Just like PolarFire SoC, the same issues with GPIO interrupts exist in
the pic64gx, due to their similarity. Yoinking fr
riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
Just like PolarFire SoC, the same issues with GPIO interrupts exist in
the pic64gx, due to their similarity. Yoinking from the commit message
for the same change for PolarFire SoC:
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| b0258f69 | 10-Feb-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPI
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so
ngpios needs to be set to match the number of lines/interrupts.
The m100pfsevp has conflicting interrupt mappings for controllers 0 and
2, as they cannot both be using an interrupt in "direct mode" at the
same time, so the default replaces this impossible configuration.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4a1739c3 | 20-Nov-2025 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add tsu clock to macb on mpfs
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
a
riscv: dts: microchip: add tsu clock to macb on mpfs
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is required for
correct rate selection.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 0aa19240 | 17-Nov-2025 |
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> |
riscv: dts: microchip: remove POLARFIRE mention in Makefile
Substitute user hidden CONFIG_ARCH_MICROCHIP_POLARFIRE by user visible
CONFIG_ARCH_MICROCHIP.
Signed-off-by: Pierre-Henry Moussay <pierre
riscv: dts: microchip: remove POLARFIRE mention in Makefile
Substitute user hidden CONFIG_ARCH_MICROCHIP_POLARFIRE by user visible
CONFIG_ARCH_MICROCHIP.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 7219d20f | 17-Nov-2025 |
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> |
riscv: dts: microchip: add pic64gx and its curiosity kit
The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000.
Features
riscv: dts: microchip: add pic64gx and its curiosity kit
The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000.
Features include:
- 1 GB DDR4 SDRAM
- Gigabit Ethernet
- microSD-card slot
note: due to issue on some board, the SDHCI is limited to HS (High
speed mode, with a clock of 50MHz and 3.3V signals).
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 26535e84 | 10-Nov-2025 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: convert clock and reset to use syscon
The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt cont
riscv: dts: microchip: convert clock and reset to use syscon
The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt control
functionality. Re-write the devicetree to describe the sys explicitly,
as its own node, rather than as a region of the clock node.
Correspondingly, the phandles to the reset controller must be updated to
the new provider. The drivers will continue to support the old way of
doing things.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| acc21153 | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: add a device tree for Discovery Kit
Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit.
The Discovery Kit is a cost-optimized board based on PolarFire SoC
riscv: dts: microchip: add a device tree for Discovery Kit
Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit.
The Discovery Kit is a cost-optimized board based on PolarFire SoC
MPFS095T and features:
- 1 GB DDR4x16
- 1x Gigabit Ethernet
- 3x UARTs
- Raspberry Pi connector
- mikroBus connector
- microSD card connector
Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 02428682 | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match
the fixed clock bindings naming recommendation.
Update
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match
the fixed clock bindings naming recommendation.
Update the reserved memory regions in the Icicle Kit common dtsi to
use lowercase hex and drop the redundant status properties from the
memory regions, as they are not required.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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