1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 enum: 83 - apm,potenza 84 - apm,strega 85 - apple,avalanche 86 - apple,blizzard 87 - apple,cyclone 88 - apple,firestorm 89 - apple,hurricane-zephyr 90 - apple,icestorm 91 - apple,mistral 92 - apple,monsoon 93 - apple,twister 94 - apple,typhoon 95 - arm,arm710t 96 - arm,arm720t 97 - arm,arm740t 98 - arm,arm7ej-s 99 - arm,arm7tdmi 100 - arm,arm7tdmi-s 101 - arm,arm9es 102 - arm,arm9ej-s 103 - arm,arm920t 104 - arm,arm922t 105 - arm,arm925 106 - arm,arm926e-s 107 - arm,arm926ej-s 108 - arm,arm940t 109 - arm,arm946e-s 110 - arm,arm966e-s 111 - arm,arm968e-s 112 - arm,arm9tdmi 113 - arm,arm1020e 114 - arm,arm1020t 115 - arm,arm1022e 116 - arm,arm1026ej-s 117 - arm,arm1136j-s 118 - arm,arm1136jf-s 119 - arm,arm1156t2-s 120 - arm,arm1156t2f-s 121 - arm,arm1176jzf 122 - arm,arm1176jz-s 123 - arm,arm1176jzf-s 124 - arm,arm11mpcore 125 - arm,armv8 # Only for s/w models 126 - arm,c1-nano 127 - arm,c1-premium 128 - arm,c1-pro 129 - arm,c1-ultra 130 - arm,cortex-a5 131 - arm,cortex-a7 132 - arm,cortex-a8 133 - arm,cortex-a9 134 - arm,cortex-a12 135 - arm,cortex-a15 136 - arm,cortex-a17 137 - arm,cortex-a32 138 - arm,cortex-a34 139 - arm,cortex-a35 140 - arm,cortex-a53 141 - arm,cortex-a55 142 - arm,cortex-a57 143 - arm,cortex-a65 144 - arm,cortex-a72 145 - arm,cortex-a73 146 - arm,cortex-a75 147 - arm,cortex-a76 148 - arm,cortex-a77 149 - arm,cortex-a78 150 - arm,cortex-a78ae 151 - arm,cortex-a78c 152 - arm,cortex-a320 153 - arm,cortex-a510 154 - arm,cortex-a520 155 - arm,cortex-a520ae 156 - arm,cortex-a710 157 - arm,cortex-a715 158 - arm,cortex-a720 159 - arm,cortex-a720ae 160 - arm,cortex-a725 161 - arm,cortex-m0 162 - arm,cortex-m0+ 163 - arm,cortex-m1 164 - arm,cortex-m3 165 - arm,cortex-m4 166 - arm,cortex-r4 167 - arm,cortex-r5 168 - arm,cortex-r7 169 - arm,cortex-r52 170 - arm,cortex-x1 171 - arm,cortex-x1c 172 - arm,cortex-x2 173 - arm,cortex-x3 174 - arm,cortex-x4 175 - arm,cortex-x925 176 - arm,neoverse-e1 177 - arm,neoverse-n1 178 - arm,neoverse-n2 179 - arm,neoverse-n3 180 - arm,neoverse-v1 181 - arm,neoverse-v2 182 - arm,neoverse-v3 183 - arm,neoverse-v3ae 184 - arm,rainier 185 - brcm,brahma-b15 186 - brcm,brahma-b53 187 - brcm,vulcan 188 - cavium,thunder 189 - cavium,thunder2 190 - faraday,fa526 191 - intel,sa110 192 - intel,sa1100 193 - marvell,feroceon 194 - marvell,mohawk 195 - marvell,pj4a 196 - marvell,pj4b 197 - marvell,sheeva-v5 198 - marvell,sheeva-v7 199 - nvidia,tegra132-denver 200 - nvidia,tegra186-denver 201 - nvidia,tegra194-carmel 202 - qcom,krait 203 - qcom,kryo 204 - qcom,kryo240 205 - qcom,kryo250 206 - qcom,kryo260 207 - qcom,kryo280 208 - qcom,kryo360 209 - qcom,kryo385 210 - qcom,kryo465 211 - qcom,kryo468 212 - qcom,kryo470 213 - qcom,kryo485 214 - qcom,kryo560 215 - qcom,kryo570 216 - qcom,kryo660 217 - qcom,kryo670 218 - qcom,kryo685 219 - qcom,kryo780 220 - qcom,oryon 221 - qcom,oryon-1-1 222 - qcom,oryon-1-2 223 - qcom,oryon-1-3 224 - qcom,oryon-1-4 225 - qcom,oryon-2-1 226 - qcom,oryon-2-2 227 - qcom,oryon-2-3 228 - qcom,scorpion 229 - samsung,mongoose-m2 230 - samsung,mongoose-m3 231 - samsung,mongoose-m5 232 233 enable-method: 234 $ref: /schemas/types.yaml#/definitions/string 235 oneOf: 236 # On ARM v8 64-bit this property is required 237 - enum: 238 - psci 239 - spin-table 240 # On ARM 32-bit systems this property is optional 241 - enum: 242 - actions,s500-smp 243 - allwinner,sun6i-a31 244 - allwinner,sun8i-a23 245 - allwinner,sun9i-a80-smp 246 - allwinner,sun8i-a83t-smp 247 - amlogic,meson8-smp 248 - amlogic,meson8b-smp 249 - arm,realview-smp 250 - aspeed,ast2600-smp 251 - brcm,bcm11351-cpu-method 252 - brcm,bcm23550 253 - brcm,bcm2836-smp 254 - brcm,bcm63138 255 - brcm,bcm-nsp-smp 256 - brcm,brahma-b15 257 - marvell,armada-375-smp 258 - marvell,armada-380-smp 259 - marvell,armada-390-smp 260 - marvell,armada-xp-smp 261 - marvell,98dx3236-smp 262 - marvell,mmp3-smp 263 - mediatek,mt6589-smp 264 - mediatek,mt81xx-tz-smp 265 - qcom,gcc-msm8660 266 - qcom,kpss-acc-v1 267 - qcom,kpss-acc-v2 268 - qcom,msm8226-smp 269 - qcom,msm8909-smp 270 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 271 - qcom,msm8916-smp 272 - renesas,apmu 273 - renesas,r9a06g032-smp 274 - rockchip,rk3036-smp 275 - rockchip,rk3066-smp 276 - socionext,milbeaut-m10v-smp 277 - ste,dbx500-smp 278 - ti,am3352 279 - ti,am4372 280 281 cpu-release-addr: 282 oneOf: 283 - $ref: /schemas/types.yaml#/definitions/uint32 284 - $ref: /schemas/types.yaml#/definitions/uint64 285 description: 286 The DT specification defines this as 64-bit always, but some 32-bit Arm 287 systems have used a 32-bit value which must be supported. 288 289 cpu-idle-states: 290 $ref: /schemas/types.yaml#/definitions/phandle-array 291 items: 292 maxItems: 1 293 description: 294 List of phandles to idle state nodes supported by this cpu (see 295 ./idle-states.yaml). 296 297 capacity-dmips-mhz: 298 description: 299 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 300 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 301 302 cci-control-port: true 303 304 dynamic-power-coefficient: 305 $ref: /schemas/types.yaml#/definitions/uint32 306 description: > 307 A u32 value that represents the running time dynamic power coefficient in 308 units of uW/MHz/V^2. The coefficient can either be calculated from power 309 measurements or derived by analysis. 310 311 The dynamic power consumption of the CPU is proportional to the square of 312 the Voltage (V) and the clock frequency (f). The coefficient is used to 313 calculate the dynamic power as below - 314 315 Pdyn = dynamic-power-coefficient * V^2 * f 316 317 where voltage is in V, frequency is in MHz. 318 319 interconnects: 320 minItems: 1 321 maxItems: 3 322 323 nvmem-cells: 324 maxItems: 1 325 326 nvmem-cell-names: 327 const: speed_grade 328 329 performance-domains: 330 maxItems: 1 331 332 power-domains: 333 minItems: 1 334 maxItems: 2 335 336 power-domain-names: 337 description: 338 For PSCI based platforms, the name corresponding to the index of the PSCI 339 PM domain provider, must be "psci". For SCMI based platforms, the name 340 corresponding to the index of an SCMI performance domain provider, must be 341 "perf". 342 minItems: 1 343 maxItems: 2 344 items: 345 enum: [ psci, perf, cpr ] 346 347 resets: 348 maxItems: 1 349 350 arm-supply: 351 deprecated: true 352 description: Use 'cpu-supply' instead 353 354 cpu0-supply: 355 deprecated: true 356 description: Use 'cpu-supply' instead 357 358 mem-supply: true 359 360 proc-supply: 361 deprecated: true 362 description: Use 'cpu-supply' instead 363 364 pu-supply: 365 deprecated: true 366 description: Only for i.MX6Q/DL/SL SoCs. 367 368 soc-supply: 369 deprecated: true 370 description: Only for i.MX6/7 Soc. 371 372 sram-supply: 373 deprecated: true 374 description: Use 'mem-supply' instead 375 376 fsl,soc-operating-points: 377 $ref: /schemas/types.yaml#/definitions/uint32-matrix 378 description: FSL i.MX6 Soc operation-points when change cpu frequency 379 deprecated: true 380 items: 381 items: 382 - description: Frequency in kHz 383 - description: Voltage for OPP in uV 384 385 mediatek,cci: 386 $ref: /schemas/types.yaml#/definitions/phandle 387 description: Link to Mediatek Cache Coherent Interconnect 388 389 edac-enabled: 390 $ref: /schemas/types.yaml#/definitions/flag 391 description: 392 A72 CPUs support Error Detection And Correction (EDAC) on their L1 and 393 L2 caches. This flag marks this function as usable. 394 395 qcom,saw: 396 $ref: /schemas/types.yaml#/definitions/phandle 397 description: 398 Specifies the SAW node associated with this CPU. 399 400 qcom,acc: 401 $ref: /schemas/types.yaml#/definitions/phandle 402 description: 403 Specifies the ACC node associated with this CPU. 404 405 qcom,freq-domain: 406 description: Specifies the QCom CPUFREQ HW associated with the CPU. 407 $ref: /schemas/types.yaml#/definitions/phandle-array 408 maxItems: 1 409 410 rockchip,pmu: 411 $ref: /schemas/types.yaml#/definitions/phandle 412 description: > 413 Specifies the syscon node controlling the cpu core power domains. 414 415 Optional for systems that have an "enable-method" property value of 416 "rockchip,rk3066-smp". While optional, it is the preferred way to get 417 access to the cpu-core power-domains. 418 419 secondary-boot-reg: 420 $ref: /schemas/types.yaml#/definitions/uint32 421 description: > 422 Required for systems that have an "enable-method" property value of 423 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 424 425 This includes the following SoCs: 426 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 427 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 428 429 The secondary-boot-reg property is a u32 value that specifies the 430 physical address of the register used to request the ROM holding pen 431 code release a secondary CPU. The value written to the register is 432 formed by encoding the target CPU id into the low bits of the 433 physical start address it should jump to. 434 435 thermal-idle: 436 type: object 437 438allOf: 439 - $ref: /schemas/cpu.yaml# 440 - $ref: /schemas/opp/opp-v1.yaml# 441 - if: 442 not: 443 properties: 444 compatible: 445 contains: 446 const: arm,cortex-a72 447 then: 448 # Allow edac-enabled only for Cortex A72 449 properties: 450 edac-enabled: false 451 452 - if: 453 # If the enable-method property contains one of those values 454 properties: 455 enable-method: 456 contains: 457 enum: 458 - brcm,bcm11351-cpu-method 459 - brcm,bcm23550 460 - brcm,bcm-nsp-smp 461 # and if enable-method is present 462 required: 463 - enable-method 464 then: 465 required: 466 - secondary-boot-reg 467 - if: 468 properties: 469 enable-method: 470 enum: 471 - spin-table 472 - renesas,r9a06g032-smp 473 required: 474 - enable-method 475 then: 476 required: 477 - cpu-release-addr 478 - if: 479 properties: 480 enable-method: 481 enum: 482 - qcom,kpss-acc-v1 483 - qcom,kpss-acc-v2 484 - qcom,msm8226-smp 485 - qcom,msm8916-smp 486 required: 487 - enable-method 488 then: 489 required: 490 - qcom,acc 491 - qcom,saw 492 else: 493 if: 494 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 495 # "spin-table" or "psci" enable-methods. Disallowing the properties for 496 # all other CPUs is the best we can do as there's not any way to 497 # distinguish these Qualcomm platforms. 498 not: 499 properties: 500 compatible: 501 const: arm,cortex-a53 502 then: 503 properties: 504 qcom,acc: false 505 qcom,saw: false 506 507required: 508 - device_type 509 - reg 510 - compatible 511 512dependencies: 513 rockchip,pmu: [enable-method] 514 515unevaluatedProperties: false 516 517examples: 518 - | 519 cpus { 520 #size-cells = <0>; 521 #address-cells = <1>; 522 523 cpu@0 { 524 device_type = "cpu"; 525 compatible = "arm,cortex-a15"; 526 reg = <0x0>; 527 }; 528 529 cpu@1 { 530 device_type = "cpu"; 531 compatible = "arm,cortex-a15"; 532 reg = <0x1>; 533 }; 534 535 cpu@100 { 536 device_type = "cpu"; 537 compatible = "arm,cortex-a7"; 538 reg = <0x100>; 539 }; 540 541 cpu@101 { 542 device_type = "cpu"; 543 compatible = "arm,cortex-a7"; 544 reg = <0x101>; 545 }; 546 }; 547 548 - | 549 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 550 cpus { 551 #size-cells = <0>; 552 #address-cells = <1>; 553 554 cpu@0 { 555 device_type = "cpu"; 556 compatible = "arm,cortex-a8"; 557 reg = <0x0>; 558 }; 559 }; 560 561 - | 562 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 563 cpus { 564 #size-cells = <0>; 565 #address-cells = <1>; 566 567 cpu@0 { 568 device_type = "cpu"; 569 compatible = "arm,arm926ej-s"; 570 reg = <0x0>; 571 }; 572 }; 573 574 - | 575 // Example 4 (ARM Cortex-A57 64-bit system): 576 cpus { 577 #size-cells = <0>; 578 #address-cells = <2>; 579 580 cpu@0 { 581 device_type = "cpu"; 582 compatible = "arm,cortex-a57"; 583 reg = <0x0 0x0>; 584 enable-method = "spin-table"; 585 cpu-release-addr = <0 0x20000000>; 586 }; 587 588 cpu@1 { 589 device_type = "cpu"; 590 compatible = "arm,cortex-a57"; 591 reg = <0x0 0x1>; 592 enable-method = "spin-table"; 593 cpu-release-addr = <0 0x20000000>; 594 }; 595 596 cpu@100 { 597 device_type = "cpu"; 598 compatible = "arm,cortex-a57"; 599 reg = <0x0 0x100>; 600 enable-method = "spin-table"; 601 cpu-release-addr = <0 0x20000000>; 602 }; 603 604 cpu@101 { 605 device_type = "cpu"; 606 compatible = "arm,cortex-a57"; 607 reg = <0x0 0x101>; 608 enable-method = "spin-table"; 609 cpu-release-addr = <0 0x20000000>; 610 }; 611 612 cpu@10000 { 613 device_type = "cpu"; 614 compatible = "arm,cortex-a57"; 615 reg = <0x0 0x10000>; 616 enable-method = "spin-table"; 617 cpu-release-addr = <0 0x20000000>; 618 }; 619 620 cpu@10001 { 621 device_type = "cpu"; 622 compatible = "arm,cortex-a57"; 623 reg = <0x0 0x10001>; 624 enable-method = "spin-table"; 625 cpu-release-addr = <0 0x20000000>; 626 }; 627 628 cpu@10100 { 629 device_type = "cpu"; 630 compatible = "arm,cortex-a57"; 631 reg = <0x0 0x10100>; 632 enable-method = "spin-table"; 633 cpu-release-addr = <0 0x20000000>; 634 }; 635 636 cpu@10101 { 637 device_type = "cpu"; 638 compatible = "arm,cortex-a57"; 639 reg = <0x0 0x10101>; 640 enable-method = "spin-table"; 641 cpu-release-addr = <0 0x20000000>; 642 }; 643 644 cpu@100000000 { 645 device_type = "cpu"; 646 compatible = "arm,cortex-a57"; 647 reg = <0x1 0x0>; 648 enable-method = "spin-table"; 649 cpu-release-addr = <0 0x20000000>; 650 }; 651 652 cpu@100000001 { 653 device_type = "cpu"; 654 compatible = "arm,cortex-a57"; 655 reg = <0x1 0x1>; 656 enable-method = "spin-table"; 657 cpu-release-addr = <0 0x20000000>; 658 }; 659 660 cpu@100000100 { 661 device_type = "cpu"; 662 compatible = "arm,cortex-a57"; 663 reg = <0x1 0x100>; 664 enable-method = "spin-table"; 665 cpu-release-addr = <0 0x20000000>; 666 }; 667 668 cpu@100000101 { 669 device_type = "cpu"; 670 compatible = "arm,cortex-a57"; 671 reg = <0x1 0x101>; 672 enable-method = "spin-table"; 673 cpu-release-addr = <0 0x20000000>; 674 }; 675 676 cpu@100010000 { 677 device_type = "cpu"; 678 compatible = "arm,cortex-a57"; 679 reg = <0x1 0x10000>; 680 enable-method = "spin-table"; 681 cpu-release-addr = <0 0x20000000>; 682 }; 683 684 cpu@100010001 { 685 device_type = "cpu"; 686 compatible = "arm,cortex-a57"; 687 reg = <0x1 0x10001>; 688 enable-method = "spin-table"; 689 cpu-release-addr = <0 0x20000000>; 690 }; 691 692 cpu@100010100 { 693 device_type = "cpu"; 694 compatible = "arm,cortex-a57"; 695 reg = <0x1 0x10100>; 696 enable-method = "spin-table"; 697 cpu-release-addr = <0 0x20000000>; 698 }; 699 700 cpu@100010101 { 701 device_type = "cpu"; 702 compatible = "arm,cortex-a57"; 703 reg = <0x1 0x10101>; 704 enable-method = "spin-table"; 705 cpu-release-addr = <0 0x20000000>; 706 }; 707 }; 708... 709