| 3f5aeaf8 | 20-May-2026 |
Sascha Bischoff <sascha.bischoff@arm.com> |
Documentation: KVM: Clarify that PMU_V3_IRQ IntID requirements for GICv5
When running a GICv5-based guest, the PMU must use PPI 23. This, however, must be communicated via the KVM_ARM_VCPU_PMU_V3_CT
Documentation: KVM: Clarify that PMU_V3_IRQ IntID requirements for GICv5
When running a GICv5-based guest, the PMU must use PPI 23. This, however, must be communicated via the KVM_ARM_VCPU_PMU_V3_CTRL->KVM_ARM_VCPU_PMU_V3_IRQ ioctl as a full GICv5-style Interrupt ID. That is, 0x20000017. Optionally, the whole ioctl can be skipped for GICv5.
This was previously not clearly documented, so bump the documentation accordingly.
Fixes: 7c31c06e2d2d ("KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5") Link: https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff%40arm.com Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://lore.kernel.org/r/20260520091949.542365-17-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
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| d51c978b | 19-Mar-2026 |
Sascha Bischoff <Sascha.Bischoff@arm.com> |
KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI
GICv5 systems will likely not support the full set of PPIs. The presence of any virtual PPI is tied to the presence of the physica
KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI
GICv5 systems will likely not support the full set of PPIs. The presence of any virtual PPI is tied to the presence of the physical PPI. Therefore, the available PPIs will be limited by the physical host. Userspace cannot drive any PPIs that are not implemented.
Moreover, it is not desirable to expose all PPIs to the guest in the first place, even if they are supported in hardware. Some devices, such as the arch timer, are implemented in KVM, and hence those PPIs shouldn't be driven by userspace, either.
Provided a new UAPI: KVM_DEV_ARM_VGIC_GRP_CTRL => KVM_DEV_ARM_VGIC_USERPSPACE_PPIs
This allows userspace to query which PPIs it is able to drive via KVM_IRQ_LINE.
Additionally, introduce a check in kvm_vm_ioctl_irq_line() to reject any PPIs not in the userspace mask.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260319154937.3619520-40-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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| eb3c4d2c | 19-Mar-2026 |
Sascha Bischoff <Sascha.Bischoff@arm.com> |
Documentation: KVM: Introduce documentation for VGICv5
Now that it is possible to create a VGICv5 device, provide initial documentation for it. At this stage, there is little to document.
Signed-of
Documentation: KVM: Introduce documentation for VGICv5
Now that it is possible to create a VGICv5 device, provide initial documentation for it. At this stage, there is little to document.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260319154937.3619520-39-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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| 54478636 | 16-Jan-2025 |
Marc Zyngier <maz@kernel.org> |
KVM: arm64: nv: Fix doc header layout for timers
Stephen reports that 'make htmldocs' spits out a warning ("Documentation/virt/kvm/devices/vcpu.rst:147: WARNING: Definition list ends without a blank
KVM: arm64: nv: Fix doc header layout for timers
Stephen reports that 'make htmldocs' spits out a warning ("Documentation/virt/kvm/devices/vcpu.rst:147: WARNING: Definition list ends without a blank line; unexpected unindent.").
Fix it by keeping all the timer attributes on a single line.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Marc Zyngier <maz@kernel.org>
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