1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 #define PURE_EL2_SYSREG(el2) \ 86 case el2: { \ 87 *el1r = el2; \ 88 return true; \ 89 } 90 91 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 92 case el2: { \ 93 *xlate = fn; \ 94 *el1r = el1; \ 95 return true; \ 96 } 97 98 static bool get_el2_to_el1_mapping(unsigned int reg, 99 unsigned int *el1r, u64 (**xlate)(u64)) 100 { 101 switch (reg) { 102 PURE_EL2_SYSREG( VPIDR_EL2 ); 103 PURE_EL2_SYSREG( VMPIDR_EL2 ); 104 PURE_EL2_SYSREG( ACTLR_EL2 ); 105 PURE_EL2_SYSREG( HCR_EL2 ); 106 PURE_EL2_SYSREG( MDCR_EL2 ); 107 PURE_EL2_SYSREG( HSTR_EL2 ); 108 PURE_EL2_SYSREG( HACR_EL2 ); 109 PURE_EL2_SYSREG( VTTBR_EL2 ); 110 PURE_EL2_SYSREG( VTCR_EL2 ); 111 PURE_EL2_SYSREG( RVBAR_EL2 ); 112 PURE_EL2_SYSREG( TPIDR_EL2 ); 113 PURE_EL2_SYSREG( HPFAR_EL2 ); 114 PURE_EL2_SYSREG( HCRX_EL2 ); 115 PURE_EL2_SYSREG( HFGRTR_EL2 ); 116 PURE_EL2_SYSREG( HFGWTR_EL2 ); 117 PURE_EL2_SYSREG( HFGITR_EL2 ); 118 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 119 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 120 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 121 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 122 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 123 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 124 translate_sctlr_el2_to_sctlr_el1 ); 125 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 126 translate_cptr_el2_to_cpacr_el1 ); 127 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 128 translate_ttbr0_el2_to_ttbr0_el1 ); 129 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 130 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 131 translate_tcr_el2_to_tcr_el1 ); 132 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 134 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 135 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 138 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 140 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 141 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 146 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 147 default: 148 return false; 149 } 150 } 151 152 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 153 { 154 u64 val = 0x8badf00d8badf00d; 155 u64 (*xlate)(u64) = NULL; 156 unsigned int el1r; 157 158 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 159 goto memory_read; 160 161 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 162 if (!is_hyp_ctxt(vcpu)) 163 goto memory_read; 164 165 /* 166 * CNTHCTL_EL2 requires some special treatment to 167 * account for the bits that can be set via CNTKCTL_EL1. 168 */ 169 switch (reg) { 170 case CNTHCTL_EL2: 171 if (vcpu_el2_e2h_is_set(vcpu)) { 172 val = read_sysreg_el1(SYS_CNTKCTL); 173 val &= CNTKCTL_VALID_BITS; 174 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 175 return val; 176 } 177 break; 178 } 179 180 /* 181 * If this register does not have an EL1 counterpart, 182 * then read the stored EL2 version. 183 */ 184 if (reg == el1r) 185 goto memory_read; 186 187 /* 188 * If we have a non-VHE guest and that the sysreg 189 * requires translation to be used at EL1, use the 190 * in-memory copy instead. 191 */ 192 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 193 goto memory_read; 194 195 /* Get the current version of the EL1 counterpart. */ 196 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 197 if (reg >= __SANITISED_REG_START__) 198 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 199 200 return val; 201 } 202 203 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 204 if (unlikely(is_hyp_ctxt(vcpu))) 205 goto memory_read; 206 207 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 208 return val; 209 210 memory_read: 211 return __vcpu_sys_reg(vcpu, reg); 212 } 213 214 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 215 { 216 u64 (*xlate)(u64) = NULL; 217 unsigned int el1r; 218 219 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 220 goto memory_write; 221 222 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 223 if (!is_hyp_ctxt(vcpu)) 224 goto memory_write; 225 226 /* 227 * Always store a copy of the write to memory to avoid having 228 * to reverse-translate virtual EL2 system registers for a 229 * non-VHE guest hypervisor. 230 */ 231 __vcpu_sys_reg(vcpu, reg) = val; 232 233 switch (reg) { 234 case CNTHCTL_EL2: 235 /* 236 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 237 * Otherwise, some of the bits are backed by 238 * CNTKCTL_EL1, while the rest is kept in memory. 239 * Yes, this is fun stuff. 240 */ 241 if (vcpu_el2_e2h_is_set(vcpu)) 242 write_sysreg_el1(val, SYS_CNTKCTL); 243 return; 244 } 245 246 /* No EL1 counterpart? We're done here.? */ 247 if (reg == el1r) 248 return; 249 250 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 251 val = xlate(val); 252 253 /* Redirect this to the EL1 version of the register. */ 254 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 255 return; 256 } 257 258 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 259 if (unlikely(is_hyp_ctxt(vcpu))) 260 goto memory_write; 261 262 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 263 return; 264 265 memory_write: 266 __vcpu_sys_reg(vcpu, reg) = val; 267 } 268 269 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 270 #define CSSELR_MAX 14 271 272 /* 273 * Returns the minimum line size for the selected cache, expressed as 274 * Log2(bytes). 275 */ 276 static u8 get_min_cache_line_size(bool icache) 277 { 278 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 279 u8 field; 280 281 if (icache) 282 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 283 else 284 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 285 286 /* 287 * Cache line size is represented as Log2(words) in CTR_EL0. 288 * Log2(bytes) can be derived with the following: 289 * 290 * Log2(words) + 2 = Log2(bytes / 4) + 2 291 * = Log2(bytes) - 2 + 2 292 * = Log2(bytes) 293 */ 294 return field + 2; 295 } 296 297 /* Which cache CCSIDR represents depends on CSSELR value. */ 298 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 299 { 300 u8 line_size; 301 302 if (vcpu->arch.ccsidr) 303 return vcpu->arch.ccsidr[csselr]; 304 305 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 306 307 /* 308 * Fabricate a CCSIDR value as the overriding value does not exist. 309 * The real CCSIDR value will not be used as it can vary by the 310 * physical CPU which the vcpu currently resides in. 311 * 312 * The line size is determined with get_min_cache_line_size(), which 313 * should be valid for all CPUs even if they have different cache 314 * configuration. 315 * 316 * The associativity bits are cleared, meaning the geometry of all data 317 * and unified caches (which are guaranteed to be PIPT and thus 318 * non-aliasing) are 1 set and 1 way. 319 * Guests should not be doing cache operations by set/way at all, and 320 * for this reason, we trap them and attempt to infer the intent, so 321 * that we can flush the entire guest's address space at the appropriate 322 * time. The exposed geometry minimizes the number of the traps. 323 * [If guests should attempt to infer aliasing properties from the 324 * geometry (which is not permitted by the architecture), they would 325 * only do so for virtually indexed caches.] 326 * 327 * We don't check if the cache level exists as it is allowed to return 328 * an UNKNOWN value if not. 329 */ 330 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 331 } 332 333 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 334 { 335 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 336 u32 *ccsidr = vcpu->arch.ccsidr; 337 u32 i; 338 339 if ((val & CCSIDR_EL1_RES0) || 340 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 341 return -EINVAL; 342 343 if (!ccsidr) { 344 if (val == get_ccsidr(vcpu, csselr)) 345 return 0; 346 347 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 348 if (!ccsidr) 349 return -ENOMEM; 350 351 for (i = 0; i < CSSELR_MAX; i++) 352 ccsidr[i] = get_ccsidr(vcpu, i); 353 354 vcpu->arch.ccsidr = ccsidr; 355 } 356 357 ccsidr[csselr] = val; 358 359 return 0; 360 } 361 362 static bool access_rw(struct kvm_vcpu *vcpu, 363 struct sys_reg_params *p, 364 const struct sys_reg_desc *r) 365 { 366 if (p->is_write) 367 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 368 else 369 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 370 371 return true; 372 } 373 374 /* 375 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 376 */ 377 static bool access_dcsw(struct kvm_vcpu *vcpu, 378 struct sys_reg_params *p, 379 const struct sys_reg_desc *r) 380 { 381 if (!p->is_write) 382 return read_from_write_only(vcpu, p, r); 383 384 /* 385 * Only track S/W ops if we don't have FWB. It still indicates 386 * that the guest is a bit broken (S/W operations should only 387 * be done by firmware, knowing that there is only a single 388 * CPU left in the system, and certainly not from non-secure 389 * software). 390 */ 391 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 392 kvm_set_way_flush(vcpu); 393 394 return true; 395 } 396 397 static bool access_dcgsw(struct kvm_vcpu *vcpu, 398 struct sys_reg_params *p, 399 const struct sys_reg_desc *r) 400 { 401 if (!kvm_has_mte(vcpu->kvm)) 402 return undef_access(vcpu, p, r); 403 404 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 405 return access_dcsw(vcpu, p, r); 406 } 407 408 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 409 { 410 switch (r->aarch32_map) { 411 case AA32_LO: 412 *mask = GENMASK_ULL(31, 0); 413 *shift = 0; 414 break; 415 case AA32_HI: 416 *mask = GENMASK_ULL(63, 32); 417 *shift = 32; 418 break; 419 default: 420 *mask = GENMASK_ULL(63, 0); 421 *shift = 0; 422 break; 423 } 424 } 425 426 /* 427 * Generic accessor for VM registers. Only called as long as HCR_TVM 428 * is set. If the guest enables the MMU, we stop trapping the VM 429 * sys_regs and leave it in complete control of the caches. 430 */ 431 static bool access_vm_reg(struct kvm_vcpu *vcpu, 432 struct sys_reg_params *p, 433 const struct sys_reg_desc *r) 434 { 435 bool was_enabled = vcpu_has_cache_enabled(vcpu); 436 u64 val, mask, shift; 437 438 BUG_ON(!p->is_write); 439 440 get_access_mask(r, &mask, &shift); 441 442 if (~mask) { 443 val = vcpu_read_sys_reg(vcpu, r->reg); 444 val &= ~mask; 445 } else { 446 val = 0; 447 } 448 449 val |= (p->regval & (mask >> shift)) << shift; 450 vcpu_write_sys_reg(vcpu, val, r->reg); 451 452 kvm_toggle_cache(vcpu, was_enabled); 453 return true; 454 } 455 456 static bool access_actlr(struct kvm_vcpu *vcpu, 457 struct sys_reg_params *p, 458 const struct sys_reg_desc *r) 459 { 460 u64 mask, shift; 461 462 if (p->is_write) 463 return ignore_write(vcpu, p); 464 465 get_access_mask(r, &mask, &shift); 466 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 467 468 return true; 469 } 470 471 /* 472 * Trap handler for the GICv3 SGI generation system register. 473 * Forward the request to the VGIC emulation. 474 * The cp15_64 code makes sure this automatically works 475 * for both AArch64 and AArch32 accesses. 476 */ 477 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 478 struct sys_reg_params *p, 479 const struct sys_reg_desc *r) 480 { 481 bool g1; 482 483 if (!kvm_has_gicv3(vcpu->kvm)) 484 return undef_access(vcpu, p, r); 485 486 if (!p->is_write) 487 return read_from_write_only(vcpu, p, r); 488 489 /* 490 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 491 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 492 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 493 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 494 * group. 495 */ 496 if (p->Op0 == 0) { /* AArch32 */ 497 switch (p->Op1) { 498 default: /* Keep GCC quiet */ 499 case 0: /* ICC_SGI1R */ 500 g1 = true; 501 break; 502 case 1: /* ICC_ASGI1R */ 503 case 2: /* ICC_SGI0R */ 504 g1 = false; 505 break; 506 } 507 } else { /* AArch64 */ 508 switch (p->Op2) { 509 default: /* Keep GCC quiet */ 510 case 5: /* ICC_SGI1R_EL1 */ 511 g1 = true; 512 break; 513 case 6: /* ICC_ASGI1R_EL1 */ 514 case 7: /* ICC_SGI0R_EL1 */ 515 g1 = false; 516 break; 517 } 518 } 519 520 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 521 522 return true; 523 } 524 525 static bool access_gic_sre(struct kvm_vcpu *vcpu, 526 struct sys_reg_params *p, 527 const struct sys_reg_desc *r) 528 { 529 if (!kvm_has_gicv3(vcpu->kvm)) 530 return undef_access(vcpu, p, r); 531 532 if (p->is_write) 533 return ignore_write(vcpu, p); 534 535 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 536 p->regval = (ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE | 537 ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB); 538 } else { /* ICC_SRE_EL1 */ 539 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 540 } 541 542 return true; 543 } 544 545 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 546 struct sys_reg_params *p, 547 const struct sys_reg_desc *r) 548 { 549 if (p->is_write) 550 return ignore_write(vcpu, p); 551 else 552 return read_zero(vcpu, p); 553 } 554 555 /* 556 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 557 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 558 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 559 * treat it separately. 560 */ 561 static bool trap_loregion(struct kvm_vcpu *vcpu, 562 struct sys_reg_params *p, 563 const struct sys_reg_desc *r) 564 { 565 u32 sr = reg_to_encoding(r); 566 567 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 568 return undef_access(vcpu, p, r); 569 570 if (p->is_write && sr == SYS_LORID_EL1) 571 return write_to_read_only(vcpu, p, r); 572 573 return trap_raz_wi(vcpu, p, r); 574 } 575 576 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 577 struct sys_reg_params *p, 578 const struct sys_reg_desc *r) 579 { 580 if (!p->is_write) 581 return read_from_write_only(vcpu, p, r); 582 583 kvm_debug_handle_oslar(vcpu, p->regval); 584 return true; 585 } 586 587 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 588 struct sys_reg_params *p, 589 const struct sys_reg_desc *r) 590 { 591 if (p->is_write) 592 return write_to_read_only(vcpu, p, r); 593 594 p->regval = __vcpu_sys_reg(vcpu, r->reg); 595 return true; 596 } 597 598 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 599 u64 val) 600 { 601 /* 602 * The only modifiable bit is the OSLK bit. Refuse the write if 603 * userspace attempts to change any other bit in the register. 604 */ 605 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 606 return -EINVAL; 607 608 __vcpu_sys_reg(vcpu, rd->reg) = val; 609 return 0; 610 } 611 612 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 613 struct sys_reg_params *p, 614 const struct sys_reg_desc *r) 615 { 616 if (p->is_write) { 617 return ignore_write(vcpu, p); 618 } else { 619 p->regval = read_sysreg(dbgauthstatus_el1); 620 return true; 621 } 622 } 623 624 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 625 struct sys_reg_params *p, 626 const struct sys_reg_desc *r) 627 { 628 access_rw(vcpu, p, r); 629 630 kvm_debug_set_guest_ownership(vcpu); 631 return true; 632 } 633 634 /* 635 * reg_to_dbg/dbg_to_reg 636 * 637 * A 32 bit write to a debug register leave top bits alone 638 * A 32 bit read from a debug register only returns the bottom bits 639 */ 640 static void reg_to_dbg(struct kvm_vcpu *vcpu, 641 struct sys_reg_params *p, 642 const struct sys_reg_desc *rd, 643 u64 *dbg_reg) 644 { 645 u64 mask, shift, val; 646 647 get_access_mask(rd, &mask, &shift); 648 649 val = *dbg_reg; 650 val &= ~mask; 651 val |= (p->regval & (mask >> shift)) << shift; 652 *dbg_reg = val; 653 } 654 655 static void dbg_to_reg(struct kvm_vcpu *vcpu, 656 struct sys_reg_params *p, 657 const struct sys_reg_desc *rd, 658 u64 *dbg_reg) 659 { 660 u64 mask, shift; 661 662 get_access_mask(rd, &mask, &shift); 663 p->regval = (*dbg_reg & mask) >> shift; 664 } 665 666 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 667 { 668 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 669 670 switch (rd->Op2) { 671 case 0b100: 672 return &dbg->dbg_bvr[rd->CRm]; 673 case 0b101: 674 return &dbg->dbg_bcr[rd->CRm]; 675 case 0b110: 676 return &dbg->dbg_wvr[rd->CRm]; 677 case 0b111: 678 return &dbg->dbg_wcr[rd->CRm]; 679 default: 680 KVM_BUG_ON(1, vcpu->kvm); 681 return NULL; 682 } 683 } 684 685 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 686 const struct sys_reg_desc *rd) 687 { 688 u64 *reg = demux_wb_reg(vcpu, rd); 689 690 if (!reg) 691 return false; 692 693 if (p->is_write) 694 reg_to_dbg(vcpu, p, rd, reg); 695 else 696 dbg_to_reg(vcpu, p, rd, reg); 697 698 kvm_debug_set_guest_ownership(vcpu); 699 return true; 700 } 701 702 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 703 u64 val) 704 { 705 u64 *reg = demux_wb_reg(vcpu, rd); 706 707 if (!reg) 708 return -EINVAL; 709 710 *reg = val; 711 return 0; 712 } 713 714 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 715 u64 *val) 716 { 717 u64 *reg = demux_wb_reg(vcpu, rd); 718 719 if (!reg) 720 return -EINVAL; 721 722 *val = *reg; 723 return 0; 724 } 725 726 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 727 { 728 u64 *reg = demux_wb_reg(vcpu, rd); 729 730 /* 731 * Bail early if we couldn't find storage for the register, the 732 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 733 * being run. 734 */ 735 if (!reg) 736 return 0; 737 738 *reg = rd->val; 739 return rd->val; 740 } 741 742 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 743 { 744 u64 amair = read_sysreg(amair_el1); 745 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 746 return amair; 747 } 748 749 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 750 { 751 u64 actlr = read_sysreg(actlr_el1); 752 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 753 return actlr; 754 } 755 756 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 757 { 758 u64 mpidr; 759 760 /* 761 * Map the vcpu_id into the first three affinity level fields of 762 * the MPIDR. We limit the number of VCPUs in level 0 due to a 763 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 764 * of the GICv3 to be able to address each CPU directly when 765 * sending IPIs. 766 */ 767 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 768 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 769 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 770 mpidr |= (1ULL << 31); 771 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 772 773 return mpidr; 774 } 775 776 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 777 const struct sys_reg_desc *r) 778 { 779 if (kvm_vcpu_has_pmu(vcpu)) 780 return 0; 781 782 return REG_HIDDEN; 783 } 784 785 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 786 { 787 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 788 u8 n = vcpu->kvm->arch.pmcr_n; 789 790 if (n) 791 mask |= GENMASK(n - 1, 0); 792 793 reset_unknown(vcpu, r); 794 __vcpu_sys_reg(vcpu, r->reg) &= mask; 795 796 return __vcpu_sys_reg(vcpu, r->reg); 797 } 798 799 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 800 { 801 reset_unknown(vcpu, r); 802 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 803 804 return __vcpu_sys_reg(vcpu, r->reg); 805 } 806 807 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 808 { 809 /* This thing will UNDEF, who cares about the reset value? */ 810 if (!kvm_vcpu_has_pmu(vcpu)) 811 return 0; 812 813 reset_unknown(vcpu, r); 814 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 815 816 return __vcpu_sys_reg(vcpu, r->reg); 817 } 818 819 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 820 { 821 reset_unknown(vcpu, r); 822 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 823 824 return __vcpu_sys_reg(vcpu, r->reg); 825 } 826 827 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 828 { 829 u64 pmcr = 0; 830 831 if (!kvm_supports_32bit_el0()) 832 pmcr |= ARMV8_PMU_PMCR_LC; 833 834 /* 835 * The value of PMCR.N field is included when the 836 * vCPU register is read via kvm_vcpu_read_pmcr(). 837 */ 838 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 839 840 return __vcpu_sys_reg(vcpu, r->reg); 841 } 842 843 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 844 { 845 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 846 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 847 848 if (!enabled) 849 kvm_inject_undefined(vcpu); 850 851 return !enabled; 852 } 853 854 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 855 { 856 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 857 } 858 859 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 860 { 861 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 862 } 863 864 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 865 { 866 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 867 } 868 869 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 870 { 871 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 872 } 873 874 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 875 const struct sys_reg_desc *r) 876 { 877 u64 val; 878 879 if (pmu_access_el0_disabled(vcpu)) 880 return false; 881 882 if (p->is_write) { 883 /* 884 * Only update writeable bits of PMCR (continuing into 885 * kvm_pmu_handle_pmcr() as well) 886 */ 887 val = kvm_vcpu_read_pmcr(vcpu); 888 val &= ~ARMV8_PMU_PMCR_MASK; 889 val |= p->regval & ARMV8_PMU_PMCR_MASK; 890 if (!kvm_supports_32bit_el0()) 891 val |= ARMV8_PMU_PMCR_LC; 892 kvm_pmu_handle_pmcr(vcpu, val); 893 } else { 894 /* PMCR.P & PMCR.C are RAZ */ 895 val = kvm_vcpu_read_pmcr(vcpu) 896 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 897 p->regval = val; 898 } 899 900 return true; 901 } 902 903 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 904 const struct sys_reg_desc *r) 905 { 906 if (pmu_access_event_counter_el0_disabled(vcpu)) 907 return false; 908 909 if (p->is_write) 910 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 911 else 912 /* return PMSELR.SEL field */ 913 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 914 & PMSELR_EL0_SEL_MASK; 915 916 return true; 917 } 918 919 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 920 const struct sys_reg_desc *r) 921 { 922 u64 pmceid, mask, shift; 923 924 BUG_ON(p->is_write); 925 926 if (pmu_access_el0_disabled(vcpu)) 927 return false; 928 929 get_access_mask(r, &mask, &shift); 930 931 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 932 pmceid &= mask; 933 pmceid >>= shift; 934 935 p->regval = pmceid; 936 937 return true; 938 } 939 940 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 941 { 942 u64 pmcr, val; 943 944 pmcr = kvm_vcpu_read_pmcr(vcpu); 945 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 946 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 947 kvm_inject_undefined(vcpu); 948 return false; 949 } 950 951 return true; 952 } 953 954 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 955 u64 *val) 956 { 957 u64 idx; 958 959 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 960 /* PMCCNTR_EL0 */ 961 idx = ARMV8_PMU_CYCLE_IDX; 962 else 963 /* PMEVCNTRn_EL0 */ 964 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 965 966 *val = kvm_pmu_get_counter_value(vcpu, idx); 967 return 0; 968 } 969 970 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 971 struct sys_reg_params *p, 972 const struct sys_reg_desc *r) 973 { 974 u64 idx = ~0UL; 975 976 if (r->CRn == 9 && r->CRm == 13) { 977 if (r->Op2 == 2) { 978 /* PMXEVCNTR_EL0 */ 979 if (pmu_access_event_counter_el0_disabled(vcpu)) 980 return false; 981 982 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 983 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 984 } else if (r->Op2 == 0) { 985 /* PMCCNTR_EL0 */ 986 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 987 return false; 988 989 idx = ARMV8_PMU_CYCLE_IDX; 990 } 991 } else if (r->CRn == 0 && r->CRm == 9) { 992 /* PMCCNTR */ 993 if (pmu_access_event_counter_el0_disabled(vcpu)) 994 return false; 995 996 idx = ARMV8_PMU_CYCLE_IDX; 997 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 998 /* PMEVCNTRn_EL0 */ 999 if (pmu_access_event_counter_el0_disabled(vcpu)) 1000 return false; 1001 1002 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1003 } 1004 1005 /* Catch any decoding mistake */ 1006 WARN_ON(idx == ~0UL); 1007 1008 if (!pmu_counter_idx_valid(vcpu, idx)) 1009 return false; 1010 1011 if (p->is_write) { 1012 if (pmu_access_el0_disabled(vcpu)) 1013 return false; 1014 1015 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1016 } else { 1017 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1018 } 1019 1020 return true; 1021 } 1022 1023 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1024 const struct sys_reg_desc *r) 1025 { 1026 u64 idx, reg; 1027 1028 if (pmu_access_el0_disabled(vcpu)) 1029 return false; 1030 1031 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1032 /* PMXEVTYPER_EL0 */ 1033 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1034 reg = PMEVTYPER0_EL0 + idx; 1035 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1036 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1037 if (idx == ARMV8_PMU_CYCLE_IDX) 1038 reg = PMCCFILTR_EL0; 1039 else 1040 /* PMEVTYPERn_EL0 */ 1041 reg = PMEVTYPER0_EL0 + idx; 1042 } else { 1043 BUG(); 1044 } 1045 1046 if (!pmu_counter_idx_valid(vcpu, idx)) 1047 return false; 1048 1049 if (p->is_write) { 1050 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1051 kvm_vcpu_pmu_restore_guest(vcpu); 1052 } else { 1053 p->regval = __vcpu_sys_reg(vcpu, reg); 1054 } 1055 1056 return true; 1057 } 1058 1059 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1060 { 1061 bool set; 1062 1063 val &= kvm_pmu_accessible_counter_mask(vcpu); 1064 1065 switch (r->reg) { 1066 case PMOVSSET_EL0: 1067 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1068 set = r->CRm & 2; 1069 break; 1070 default: 1071 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1072 set = r->Op2 & 1; 1073 break; 1074 } 1075 1076 if (set) 1077 __vcpu_sys_reg(vcpu, r->reg) |= val; 1078 else 1079 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1080 1081 return 0; 1082 } 1083 1084 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1085 { 1086 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1087 1088 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1089 return 0; 1090 } 1091 1092 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1093 const struct sys_reg_desc *r) 1094 { 1095 u64 val, mask; 1096 1097 if (pmu_access_el0_disabled(vcpu)) 1098 return false; 1099 1100 mask = kvm_pmu_accessible_counter_mask(vcpu); 1101 if (p->is_write) { 1102 val = p->regval & mask; 1103 if (r->Op2 & 0x1) 1104 /* accessing PMCNTENSET_EL0 */ 1105 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1106 else 1107 /* accessing PMCNTENCLR_EL0 */ 1108 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1109 1110 kvm_pmu_reprogram_counter_mask(vcpu, val); 1111 } else { 1112 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1113 } 1114 1115 return true; 1116 } 1117 1118 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1119 const struct sys_reg_desc *r) 1120 { 1121 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1122 1123 if (check_pmu_access_disabled(vcpu, 0)) 1124 return false; 1125 1126 if (p->is_write) { 1127 u64 val = p->regval & mask; 1128 1129 if (r->Op2 & 0x1) 1130 /* accessing PMINTENSET_EL1 */ 1131 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1132 else 1133 /* accessing PMINTENCLR_EL1 */ 1134 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1135 } else { 1136 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1137 } 1138 1139 return true; 1140 } 1141 1142 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1143 const struct sys_reg_desc *r) 1144 { 1145 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1146 1147 if (pmu_access_el0_disabled(vcpu)) 1148 return false; 1149 1150 if (p->is_write) { 1151 if (r->CRm & 0x2) 1152 /* accessing PMOVSSET_EL0 */ 1153 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1154 else 1155 /* accessing PMOVSCLR_EL0 */ 1156 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1157 } else { 1158 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1159 } 1160 1161 return true; 1162 } 1163 1164 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1165 const struct sys_reg_desc *r) 1166 { 1167 u64 mask; 1168 1169 if (!p->is_write) 1170 return read_from_write_only(vcpu, p, r); 1171 1172 if (pmu_write_swinc_el0_disabled(vcpu)) 1173 return false; 1174 1175 mask = kvm_pmu_accessible_counter_mask(vcpu); 1176 kvm_pmu_software_increment(vcpu, p->regval & mask); 1177 return true; 1178 } 1179 1180 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1181 const struct sys_reg_desc *r) 1182 { 1183 if (p->is_write) { 1184 if (!vcpu_mode_priv(vcpu)) 1185 return undef_access(vcpu, p, r); 1186 1187 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1188 p->regval & ARMV8_PMU_USERENR_MASK; 1189 } else { 1190 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1191 & ARMV8_PMU_USERENR_MASK; 1192 } 1193 1194 return true; 1195 } 1196 1197 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1198 u64 *val) 1199 { 1200 *val = kvm_vcpu_read_pmcr(vcpu); 1201 return 0; 1202 } 1203 1204 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1205 u64 val) 1206 { 1207 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1208 struct kvm *kvm = vcpu->kvm; 1209 1210 mutex_lock(&kvm->arch.config_lock); 1211 1212 /* 1213 * The vCPU can't have more counters than the PMU hardware 1214 * implements. Ignore this error to maintain compatibility 1215 * with the existing KVM behavior. 1216 */ 1217 if (!kvm_vm_has_ran_once(kvm) && 1218 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1219 kvm->arch.pmcr_n = new_n; 1220 1221 mutex_unlock(&kvm->arch.config_lock); 1222 1223 /* 1224 * Ignore writes to RES0 bits, read only bits that are cleared on 1225 * vCPU reset, and writable bits that KVM doesn't support yet. 1226 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1227 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1228 * But, we leave the bit as it is here, as the vCPU's PMUver might 1229 * be changed later (NOTE: the bit will be cleared on first vCPU run 1230 * if necessary). 1231 */ 1232 val &= ARMV8_PMU_PMCR_MASK; 1233 1234 /* The LC bit is RES1 when AArch32 is not supported */ 1235 if (!kvm_supports_32bit_el0()) 1236 val |= ARMV8_PMU_PMCR_LC; 1237 1238 __vcpu_sys_reg(vcpu, r->reg) = val; 1239 return 0; 1240 } 1241 1242 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1243 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1244 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1245 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1246 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1247 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1248 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1249 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1250 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1251 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1252 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1253 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1254 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1255 get_dbg_wb_reg, set_dbg_wb_reg } 1256 1257 #define PMU_SYS_REG(name) \ 1258 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1259 .visibility = pmu_visibility 1260 1261 /* Macro to expand the PMEVCNTRn_EL0 register */ 1262 #define PMU_PMEVCNTR_EL0(n) \ 1263 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1264 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1265 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1266 1267 /* Macro to expand the PMEVTYPERn_EL0 register */ 1268 #define PMU_PMEVTYPER_EL0(n) \ 1269 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1270 .reset = reset_pmevtyper, \ 1271 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1272 1273 /* Macro to expand the AMU counter and type registers*/ 1274 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1275 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1276 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1277 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1278 1279 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1280 const struct sys_reg_desc *rd) 1281 { 1282 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1283 } 1284 1285 /* 1286 * If we land here on a PtrAuth access, that is because we didn't 1287 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1288 * way this happens is when the guest does not have PtrAuth support 1289 * enabled. 1290 */ 1291 #define __PTRAUTH_KEY(k) \ 1292 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1293 .visibility = ptrauth_visibility} 1294 1295 #define PTRAUTH_KEY(k) \ 1296 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1297 __PTRAUTH_KEY(k ## KEYHI_EL1) 1298 1299 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1300 struct sys_reg_params *p, 1301 const struct sys_reg_desc *r) 1302 { 1303 enum kvm_arch_timers tmr; 1304 enum kvm_arch_timer_regs treg; 1305 u64 reg = reg_to_encoding(r); 1306 1307 switch (reg) { 1308 case SYS_CNTP_TVAL_EL0: 1309 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1310 tmr = TIMER_HPTIMER; 1311 else 1312 tmr = TIMER_PTIMER; 1313 treg = TIMER_REG_TVAL; 1314 break; 1315 1316 case SYS_CNTV_TVAL_EL0: 1317 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1318 tmr = TIMER_HVTIMER; 1319 else 1320 tmr = TIMER_VTIMER; 1321 treg = TIMER_REG_TVAL; 1322 break; 1323 1324 case SYS_AARCH32_CNTP_TVAL: 1325 case SYS_CNTP_TVAL_EL02: 1326 tmr = TIMER_PTIMER; 1327 treg = TIMER_REG_TVAL; 1328 break; 1329 1330 case SYS_CNTV_TVAL_EL02: 1331 tmr = TIMER_VTIMER; 1332 treg = TIMER_REG_TVAL; 1333 break; 1334 1335 case SYS_CNTHP_TVAL_EL2: 1336 tmr = TIMER_HPTIMER; 1337 treg = TIMER_REG_TVAL; 1338 break; 1339 1340 case SYS_CNTHV_TVAL_EL2: 1341 tmr = TIMER_HVTIMER; 1342 treg = TIMER_REG_TVAL; 1343 break; 1344 1345 case SYS_CNTP_CTL_EL0: 1346 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1347 tmr = TIMER_HPTIMER; 1348 else 1349 tmr = TIMER_PTIMER; 1350 treg = TIMER_REG_CTL; 1351 break; 1352 1353 case SYS_CNTV_CTL_EL0: 1354 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1355 tmr = TIMER_HVTIMER; 1356 else 1357 tmr = TIMER_VTIMER; 1358 treg = TIMER_REG_CTL; 1359 break; 1360 1361 case SYS_AARCH32_CNTP_CTL: 1362 case SYS_CNTP_CTL_EL02: 1363 tmr = TIMER_PTIMER; 1364 treg = TIMER_REG_CTL; 1365 break; 1366 1367 case SYS_CNTV_CTL_EL02: 1368 tmr = TIMER_VTIMER; 1369 treg = TIMER_REG_CTL; 1370 break; 1371 1372 case SYS_CNTHP_CTL_EL2: 1373 tmr = TIMER_HPTIMER; 1374 treg = TIMER_REG_CTL; 1375 break; 1376 1377 case SYS_CNTHV_CTL_EL2: 1378 tmr = TIMER_HVTIMER; 1379 treg = TIMER_REG_CTL; 1380 break; 1381 1382 case SYS_CNTP_CVAL_EL0: 1383 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1384 tmr = TIMER_HPTIMER; 1385 else 1386 tmr = TIMER_PTIMER; 1387 treg = TIMER_REG_CVAL; 1388 break; 1389 1390 case SYS_CNTV_CVAL_EL0: 1391 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1392 tmr = TIMER_HVTIMER; 1393 else 1394 tmr = TIMER_VTIMER; 1395 treg = TIMER_REG_CVAL; 1396 break; 1397 1398 case SYS_AARCH32_CNTP_CVAL: 1399 case SYS_CNTP_CVAL_EL02: 1400 tmr = TIMER_PTIMER; 1401 treg = TIMER_REG_CVAL; 1402 break; 1403 1404 case SYS_CNTV_CVAL_EL02: 1405 tmr = TIMER_VTIMER; 1406 treg = TIMER_REG_CVAL; 1407 break; 1408 1409 case SYS_CNTHP_CVAL_EL2: 1410 tmr = TIMER_HPTIMER; 1411 treg = TIMER_REG_CVAL; 1412 break; 1413 1414 case SYS_CNTHV_CVAL_EL2: 1415 tmr = TIMER_HVTIMER; 1416 treg = TIMER_REG_CVAL; 1417 break; 1418 1419 case SYS_CNTPCT_EL0: 1420 case SYS_CNTPCTSS_EL0: 1421 if (is_hyp_ctxt(vcpu)) 1422 tmr = TIMER_HPTIMER; 1423 else 1424 tmr = TIMER_PTIMER; 1425 treg = TIMER_REG_CNT; 1426 break; 1427 1428 case SYS_AARCH32_CNTPCT: 1429 case SYS_AARCH32_CNTPCTSS: 1430 tmr = TIMER_PTIMER; 1431 treg = TIMER_REG_CNT; 1432 break; 1433 1434 case SYS_CNTVCT_EL0: 1435 case SYS_CNTVCTSS_EL0: 1436 if (is_hyp_ctxt(vcpu)) 1437 tmr = TIMER_HVTIMER; 1438 else 1439 tmr = TIMER_VTIMER; 1440 treg = TIMER_REG_CNT; 1441 break; 1442 1443 case SYS_AARCH32_CNTVCT: 1444 case SYS_AARCH32_CNTVCTSS: 1445 tmr = TIMER_VTIMER; 1446 treg = TIMER_REG_CNT; 1447 break; 1448 1449 default: 1450 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1451 return undef_access(vcpu, p, r); 1452 } 1453 1454 if (p->is_write) 1455 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1456 else 1457 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1458 1459 return true; 1460 } 1461 1462 static bool access_hv_timer(struct kvm_vcpu *vcpu, 1463 struct sys_reg_params *p, 1464 const struct sys_reg_desc *r) 1465 { 1466 if (!vcpu_el2_e2h_is_set(vcpu)) 1467 return undef_access(vcpu, p, r); 1468 1469 return access_arch_timer(vcpu, p, r); 1470 } 1471 1472 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1473 s64 new, s64 cur) 1474 { 1475 struct arm64_ftr_bits kvm_ftr = *ftrp; 1476 1477 /* Some features have different safe value type in KVM than host features */ 1478 switch (id) { 1479 case SYS_ID_AA64DFR0_EL1: 1480 switch (kvm_ftr.shift) { 1481 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1482 kvm_ftr.type = FTR_LOWER_SAFE; 1483 break; 1484 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1485 kvm_ftr.type = FTR_LOWER_SAFE; 1486 break; 1487 } 1488 break; 1489 case SYS_ID_DFR0_EL1: 1490 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1491 kvm_ftr.type = FTR_LOWER_SAFE; 1492 break; 1493 } 1494 1495 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1496 } 1497 1498 /* 1499 * arm64_check_features() - Check if a feature register value constitutes 1500 * a subset of features indicated by the idreg's KVM sanitised limit. 1501 * 1502 * This function will check if each feature field of @val is the "safe" value 1503 * against idreg's KVM sanitised limit return from reset() callback. 1504 * If a field value in @val is the same as the one in limit, it is always 1505 * considered the safe value regardless For register fields that are not in 1506 * writable, only the value in limit is considered the safe value. 1507 * 1508 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1509 */ 1510 static int arm64_check_features(struct kvm_vcpu *vcpu, 1511 const struct sys_reg_desc *rd, 1512 u64 val) 1513 { 1514 const struct arm64_ftr_reg *ftr_reg; 1515 const struct arm64_ftr_bits *ftrp = NULL; 1516 u32 id = reg_to_encoding(rd); 1517 u64 writable_mask = rd->val; 1518 u64 limit = rd->reset(vcpu, rd); 1519 u64 mask = 0; 1520 1521 /* 1522 * Hidden and unallocated ID registers may not have a corresponding 1523 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1524 * only safe value is 0. 1525 */ 1526 if (sysreg_visible_as_raz(vcpu, rd)) 1527 return val ? -E2BIG : 0; 1528 1529 ftr_reg = get_arm64_ftr_reg(id); 1530 if (!ftr_reg) 1531 return -EINVAL; 1532 1533 ftrp = ftr_reg->ftr_bits; 1534 1535 for (; ftrp && ftrp->width; ftrp++) { 1536 s64 f_val, f_lim, safe_val; 1537 u64 ftr_mask; 1538 1539 ftr_mask = arm64_ftr_mask(ftrp); 1540 if ((ftr_mask & writable_mask) != ftr_mask) 1541 continue; 1542 1543 f_val = arm64_ftr_value(ftrp, val); 1544 f_lim = arm64_ftr_value(ftrp, limit); 1545 mask |= ftr_mask; 1546 1547 if (f_val == f_lim) 1548 safe_val = f_val; 1549 else 1550 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1551 1552 if (safe_val != f_val) 1553 return -E2BIG; 1554 } 1555 1556 /* For fields that are not writable, values in limit are the safe values. */ 1557 if ((val & ~mask) != (limit & ~mask)) 1558 return -E2BIG; 1559 1560 return 0; 1561 } 1562 1563 static u8 pmuver_to_perfmon(u8 pmuver) 1564 { 1565 switch (pmuver) { 1566 case ID_AA64DFR0_EL1_PMUVer_IMP: 1567 return ID_DFR0_EL1_PerfMon_PMUv3; 1568 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1569 return ID_DFR0_EL1_PerfMon_IMPDEF; 1570 default: 1571 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1572 return pmuver; 1573 } 1574 } 1575 1576 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1577 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1578 1579 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1580 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1581 const struct sys_reg_desc *r) 1582 { 1583 u32 id = reg_to_encoding(r); 1584 u64 val; 1585 1586 if (sysreg_visible_as_raz(vcpu, r)) 1587 return 0; 1588 1589 val = read_sanitised_ftr_reg(id); 1590 1591 switch (id) { 1592 case SYS_ID_AA64DFR0_EL1: 1593 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1594 break; 1595 case SYS_ID_AA64PFR0_EL1: 1596 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1597 break; 1598 case SYS_ID_AA64PFR1_EL1: 1599 if (!kvm_has_mte(vcpu->kvm)) 1600 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1601 1602 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1603 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1604 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1605 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1606 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1607 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1608 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1609 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1610 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1611 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1612 break; 1613 case SYS_ID_AA64PFR2_EL1: 1614 /* We only expose FPMR */ 1615 val &= ID_AA64PFR2_EL1_FPMR; 1616 break; 1617 case SYS_ID_AA64ISAR1_EL1: 1618 if (!vcpu_has_ptrauth(vcpu)) 1619 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1620 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1621 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1622 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1623 break; 1624 case SYS_ID_AA64ISAR2_EL1: 1625 if (!vcpu_has_ptrauth(vcpu)) 1626 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1627 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1628 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1629 has_broken_cntvoff()) 1630 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1631 break; 1632 case SYS_ID_AA64ISAR3_EL1: 1633 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1634 break; 1635 case SYS_ID_AA64MMFR2_EL1: 1636 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1637 break; 1638 case SYS_ID_AA64MMFR3_EL1: 1639 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1640 ID_AA64MMFR3_EL1_S1PIE; 1641 break; 1642 case SYS_ID_MMFR4_EL1: 1643 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1644 break; 1645 } 1646 1647 return val; 1648 } 1649 1650 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1651 const struct sys_reg_desc *r) 1652 { 1653 return __kvm_read_sanitised_id_reg(vcpu, r); 1654 } 1655 1656 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1657 { 1658 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1659 } 1660 1661 static bool is_feature_id_reg(u32 encoding) 1662 { 1663 return (sys_reg_Op0(encoding) == 3 && 1664 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1665 sys_reg_CRn(encoding) == 0 && 1666 sys_reg_CRm(encoding) <= 7); 1667 } 1668 1669 /* 1670 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1671 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1672 * registers KVM maintains on a per-VM basis. 1673 */ 1674 static inline bool is_vm_ftr_id_reg(u32 id) 1675 { 1676 if (id == SYS_CTR_EL0) 1677 return true; 1678 1679 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1680 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1681 sys_reg_CRm(id) < 8); 1682 } 1683 1684 static inline bool is_vcpu_ftr_id_reg(u32 id) 1685 { 1686 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1687 } 1688 1689 static inline bool is_aa32_id_reg(u32 id) 1690 { 1691 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1692 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1693 sys_reg_CRm(id) <= 3); 1694 } 1695 1696 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1697 const struct sys_reg_desc *r) 1698 { 1699 u32 id = reg_to_encoding(r); 1700 1701 switch (id) { 1702 case SYS_ID_AA64ZFR0_EL1: 1703 if (!vcpu_has_sve(vcpu)) 1704 return REG_RAZ; 1705 break; 1706 } 1707 1708 return 0; 1709 } 1710 1711 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1712 const struct sys_reg_desc *r) 1713 { 1714 /* 1715 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1716 * EL. Promote to RAZ/WI in order to guarantee consistency between 1717 * systems. 1718 */ 1719 if (!kvm_supports_32bit_el0()) 1720 return REG_RAZ | REG_USER_WI; 1721 1722 return id_visibility(vcpu, r); 1723 } 1724 1725 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1726 const struct sys_reg_desc *r) 1727 { 1728 return REG_RAZ; 1729 } 1730 1731 /* cpufeature ID register access trap handlers */ 1732 1733 static bool access_id_reg(struct kvm_vcpu *vcpu, 1734 struct sys_reg_params *p, 1735 const struct sys_reg_desc *r) 1736 { 1737 if (p->is_write) 1738 return write_to_read_only(vcpu, p, r); 1739 1740 p->regval = read_id_reg(vcpu, r); 1741 1742 return true; 1743 } 1744 1745 /* Visibility overrides for SVE-specific control registers */ 1746 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1747 const struct sys_reg_desc *rd) 1748 { 1749 if (vcpu_has_sve(vcpu)) 1750 return 0; 1751 1752 return REG_HIDDEN; 1753 } 1754 1755 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1756 const struct sys_reg_desc *rd) 1757 { 1758 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1759 return 0; 1760 1761 return REG_HIDDEN; 1762 } 1763 1764 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1765 const struct sys_reg_desc *rd) 1766 { 1767 if (kvm_has_fpmr(vcpu->kvm)) 1768 return 0; 1769 1770 return REG_HIDDEN; 1771 } 1772 1773 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1774 { 1775 if (!vcpu_has_sve(vcpu)) 1776 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1777 1778 /* 1779 * The default is to expose CSV2 == 1 if the HW isn't affected. 1780 * Although this is a per-CPU feature, we make it global because 1781 * asymmetric systems are just a nuisance. 1782 * 1783 * Userspace can override this as long as it doesn't promise 1784 * the impossible. 1785 */ 1786 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1787 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1788 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1789 } 1790 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1791 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1792 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1793 } 1794 1795 if (kvm_vgic_global_state.type == VGIC_V3) { 1796 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1797 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1798 } 1799 1800 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1801 1802 /* 1803 * MPAM is disabled by default as KVM also needs a set of PARTID to 1804 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1805 * older kernels let the guest see the ID bit. 1806 */ 1807 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1808 1809 return val; 1810 } 1811 1812 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1813 ({ \ 1814 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1815 (val) &= ~reg##_##field##_MASK; \ 1816 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1817 min(__f_val, \ 1818 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1819 (val); \ 1820 }) 1821 1822 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1823 { 1824 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1825 1826 /* 1827 * Only initialize the PMU version if the vCPU was configured with one. 1828 */ 1829 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1830 if (kvm_vcpu_has_pmu(vcpu)) 1831 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1832 kvm_arm_pmu_get_pmuver_limit()); 1833 1834 /* Hide SPE from guests */ 1835 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1836 1837 /* Hide BRBE from guests */ 1838 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 1839 1840 return val; 1841 } 1842 1843 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1844 const struct sys_reg_desc *rd, 1845 u64 val) 1846 { 1847 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1848 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1849 1850 /* 1851 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1852 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1853 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1854 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1855 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1856 * 1857 * At minimum, we're on the hook to allow values that were given to 1858 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1859 * with a more sensible NI. The value of an ID register changing under 1860 * the nose of the guest is unfortunate, but is certainly no more 1861 * surprising than an ill-guided PMU driver poking at impdef system 1862 * registers that end in an UNDEF... 1863 */ 1864 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1865 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1866 1867 /* 1868 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1869 * nonzero minimum safe value. 1870 */ 1871 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1872 return -EINVAL; 1873 1874 return set_id_reg(vcpu, rd, val); 1875 } 1876 1877 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1878 const struct sys_reg_desc *rd) 1879 { 1880 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1881 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1882 1883 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1884 if (kvm_vcpu_has_pmu(vcpu)) 1885 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1886 1887 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1888 1889 return val; 1890 } 1891 1892 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1893 const struct sys_reg_desc *rd, 1894 u64 val) 1895 { 1896 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1897 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1898 1899 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1900 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1901 perfmon = 0; 1902 } 1903 1904 /* 1905 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1906 * it doesn't promise more than what the HW gives us on the 1907 * AArch64 side (as everything is emulated with that), and 1908 * that this is a PMUv3. 1909 */ 1910 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1911 return -EINVAL; 1912 1913 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1914 return -EINVAL; 1915 1916 return set_id_reg(vcpu, rd, val); 1917 } 1918 1919 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1920 const struct sys_reg_desc *rd, u64 user_val) 1921 { 1922 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1923 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1924 1925 /* 1926 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1927 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1928 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1929 * always returns an UNDEF for these registers. The guest must see 0 1930 * for this field. 1931 * 1932 * But KVM must also accept values from user-space that were provided 1933 * by KVM. On CPUs that support MPAM, permit user-space to write 1934 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1935 */ 1936 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1937 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1938 1939 return set_id_reg(vcpu, rd, user_val); 1940 } 1941 1942 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1943 const struct sys_reg_desc *rd, u64 user_val) 1944 { 1945 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1946 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1947 1948 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1949 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1950 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1951 1952 return set_id_reg(vcpu, rd, user_val); 1953 } 1954 1955 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1956 const struct sys_reg_desc *rd, u64 user_val) 1957 { 1958 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1959 1960 /* 1961 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1962 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1963 * on what hardware reports. 1964 * 1965 * Using a VIPT software model on PIPT will lead to over invalidation, 1966 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1967 * but not the other way around. This is handled via arm64_ftr_safe_value() 1968 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1969 * set as VIPT. 1970 */ 1971 switch (user_L1Ip) { 1972 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1973 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1974 return -EINVAL; 1975 case CTR_EL0_L1Ip_VIPT: 1976 case CTR_EL0_L1Ip_PIPT: 1977 return set_id_reg(vcpu, rd, user_val); 1978 default: 1979 return -ENOENT; 1980 } 1981 } 1982 1983 /* 1984 * cpufeature ID register user accessors 1985 * 1986 * For now, these registers are immutable for userspace, so no values 1987 * are stored, and for set_id_reg() we don't allow the effective value 1988 * to be changed. 1989 */ 1990 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1991 u64 *val) 1992 { 1993 /* 1994 * Avoid locking if the VM has already started, as the ID registers are 1995 * guaranteed to be invariant at that point. 1996 */ 1997 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1998 *val = read_id_reg(vcpu, rd); 1999 return 0; 2000 } 2001 2002 mutex_lock(&vcpu->kvm->arch.config_lock); 2003 *val = read_id_reg(vcpu, rd); 2004 mutex_unlock(&vcpu->kvm->arch.config_lock); 2005 2006 return 0; 2007 } 2008 2009 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2010 u64 val) 2011 { 2012 u32 id = reg_to_encoding(rd); 2013 int ret; 2014 2015 mutex_lock(&vcpu->kvm->arch.config_lock); 2016 2017 /* 2018 * Once the VM has started the ID registers are immutable. Reject any 2019 * write that does not match the final register value. 2020 */ 2021 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2022 if (val != read_id_reg(vcpu, rd)) 2023 ret = -EBUSY; 2024 else 2025 ret = 0; 2026 2027 mutex_unlock(&vcpu->kvm->arch.config_lock); 2028 return ret; 2029 } 2030 2031 ret = arm64_check_features(vcpu, rd, val); 2032 if (!ret) 2033 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2034 2035 mutex_unlock(&vcpu->kvm->arch.config_lock); 2036 2037 /* 2038 * arm64_check_features() returns -E2BIG to indicate the register's 2039 * feature set is a superset of the maximally-allowed register value. 2040 * While it would be nice to precisely describe this to userspace, the 2041 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2042 * writes return -EINVAL. 2043 */ 2044 if (ret == -E2BIG) 2045 ret = -EINVAL; 2046 return ret; 2047 } 2048 2049 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2050 { 2051 u64 *p = __vm_id_reg(&kvm->arch, reg); 2052 2053 lockdep_assert_held(&kvm->arch.config_lock); 2054 2055 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2056 return; 2057 2058 *p = val; 2059 } 2060 2061 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2062 u64 *val) 2063 { 2064 *val = 0; 2065 return 0; 2066 } 2067 2068 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2069 u64 val) 2070 { 2071 return 0; 2072 } 2073 2074 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2075 const struct sys_reg_desc *r) 2076 { 2077 if (p->is_write) 2078 return write_to_read_only(vcpu, p, r); 2079 2080 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2081 return true; 2082 } 2083 2084 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2085 const struct sys_reg_desc *r) 2086 { 2087 if (p->is_write) 2088 return write_to_read_only(vcpu, p, r); 2089 2090 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2091 return true; 2092 } 2093 2094 /* 2095 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2096 * by the physical CPU which the vcpu currently resides in. 2097 */ 2098 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2099 { 2100 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2101 u64 clidr; 2102 u8 loc; 2103 2104 if ((ctr_el0 & CTR_EL0_IDC)) { 2105 /* 2106 * Data cache clean to the PoU is not required so LoUU and LoUIS 2107 * will not be set and a unified cache, which will be marked as 2108 * LoC, will be added. 2109 * 2110 * If not DIC, let the unified cache L2 so that an instruction 2111 * cache can be added as L1 later. 2112 */ 2113 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2114 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2115 } else { 2116 /* 2117 * Data cache clean to the PoU is required so let L1 have a data 2118 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2119 * it can be marked as LoC too. 2120 */ 2121 loc = 1; 2122 clidr = 1 << CLIDR_LOUU_SHIFT; 2123 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2124 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2125 } 2126 2127 /* 2128 * Instruction cache invalidation to the PoU is required so let L1 have 2129 * an instruction cache. If L1 already has a data cache, it will be 2130 * CACHE_TYPE_SEPARATE. 2131 */ 2132 if (!(ctr_el0 & CTR_EL0_DIC)) 2133 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2134 2135 clidr |= loc << CLIDR_LOC_SHIFT; 2136 2137 /* 2138 * Add tag cache unified to data cache. Allocation tags and data are 2139 * unified in a cache line so that it looks valid even if there is only 2140 * one cache line. 2141 */ 2142 if (kvm_has_mte(vcpu->kvm)) 2143 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2144 2145 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2146 2147 return __vcpu_sys_reg(vcpu, r->reg); 2148 } 2149 2150 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2151 u64 val) 2152 { 2153 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2154 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2155 2156 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2157 return -EINVAL; 2158 2159 __vcpu_sys_reg(vcpu, rd->reg) = val; 2160 2161 return 0; 2162 } 2163 2164 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2165 const struct sys_reg_desc *r) 2166 { 2167 int reg = r->reg; 2168 2169 if (p->is_write) 2170 vcpu_write_sys_reg(vcpu, p->regval, reg); 2171 else 2172 p->regval = vcpu_read_sys_reg(vcpu, reg); 2173 return true; 2174 } 2175 2176 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2177 const struct sys_reg_desc *r) 2178 { 2179 u32 csselr; 2180 2181 if (p->is_write) 2182 return write_to_read_only(vcpu, p, r); 2183 2184 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2185 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2186 if (csselr < CSSELR_MAX) 2187 p->regval = get_ccsidr(vcpu, csselr); 2188 2189 return true; 2190 } 2191 2192 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2193 const struct sys_reg_desc *rd) 2194 { 2195 if (kvm_has_mte(vcpu->kvm)) 2196 return 0; 2197 2198 return REG_HIDDEN; 2199 } 2200 2201 #define MTE_REG(name) { \ 2202 SYS_DESC(SYS_##name), \ 2203 .access = undef_access, \ 2204 .reset = reset_unknown, \ 2205 .reg = name, \ 2206 .visibility = mte_visibility, \ 2207 } 2208 2209 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2210 const struct sys_reg_desc *rd) 2211 { 2212 if (vcpu_has_nv(vcpu)) 2213 return 0; 2214 2215 return REG_HIDDEN; 2216 } 2217 2218 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2219 struct sys_reg_params *p, 2220 const struct sys_reg_desc *r) 2221 { 2222 /* 2223 * We really shouldn't be here, and this is likely the result 2224 * of a misconfigured trap, as this register should target the 2225 * VNCR page, and nothing else. 2226 */ 2227 return bad_trap(vcpu, p, r, 2228 "trap of VNCR-backed register"); 2229 } 2230 2231 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2232 struct sys_reg_params *p, 2233 const struct sys_reg_desc *r) 2234 { 2235 /* 2236 * We really shouldn't be here, and this is likely the result 2237 * of a misconfigured trap, as this register should target the 2238 * corresponding EL1, and nothing else. 2239 */ 2240 return bad_trap(vcpu, p, r, 2241 "trap of EL2 register redirected to EL1"); 2242 } 2243 2244 #define EL2_REG(name, acc, rst, v) { \ 2245 SYS_DESC(SYS_##name), \ 2246 .access = acc, \ 2247 .reset = rst, \ 2248 .reg = name, \ 2249 .visibility = el2_visibility, \ 2250 .val = v, \ 2251 } 2252 2253 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2254 SYS_DESC(SYS_##name), \ 2255 .access = acc, \ 2256 .reset = rst, \ 2257 .reg = name, \ 2258 .visibility = filter, \ 2259 .val = v, \ 2260 } 2261 2262 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2263 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2264 2265 /* 2266 * Since reset() callback and field val are not used for idregs, they will be 2267 * used for specific purposes for idregs. 2268 * The reset() would return KVM sanitised register value. The value would be the 2269 * same as the host kernel sanitised value if there is no KVM sanitisation. 2270 * The val would be used as a mask indicating writable fields for the idreg. 2271 * Only bits with 1 are writable from userspace. This mask might not be 2272 * necessary in the future whenever all ID registers are enabled as writable 2273 * from userspace. 2274 */ 2275 2276 #define ID_DESC(name) \ 2277 SYS_DESC(SYS_##name), \ 2278 .access = access_id_reg, \ 2279 .get_user = get_id_reg \ 2280 2281 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2282 #define ID_SANITISED(name) { \ 2283 ID_DESC(name), \ 2284 .set_user = set_id_reg, \ 2285 .visibility = id_visibility, \ 2286 .reset = kvm_read_sanitised_id_reg, \ 2287 .val = 0, \ 2288 } 2289 2290 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2291 #define AA32_ID_SANITISED(name) { \ 2292 ID_DESC(name), \ 2293 .set_user = set_id_reg, \ 2294 .visibility = aa32_id_visibility, \ 2295 .reset = kvm_read_sanitised_id_reg, \ 2296 .val = 0, \ 2297 } 2298 2299 /* sys_reg_desc initialiser for writable ID registers */ 2300 #define ID_WRITABLE(name, mask) { \ 2301 ID_DESC(name), \ 2302 .set_user = set_id_reg, \ 2303 .visibility = id_visibility, \ 2304 .reset = kvm_read_sanitised_id_reg, \ 2305 .val = mask, \ 2306 } 2307 2308 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2309 #define ID_FILTERED(sysreg, name, mask) { \ 2310 ID_DESC(sysreg), \ 2311 .set_user = set_##name, \ 2312 .visibility = id_visibility, \ 2313 .reset = kvm_read_sanitised_id_reg, \ 2314 .val = (mask), \ 2315 } 2316 2317 /* 2318 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2319 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2320 * (1 <= crm < 8, 0 <= Op2 < 8). 2321 */ 2322 #define ID_UNALLOCATED(crm, op2) { \ 2323 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2324 .access = access_id_reg, \ 2325 .get_user = get_id_reg, \ 2326 .set_user = set_id_reg, \ 2327 .visibility = raz_visibility, \ 2328 .reset = kvm_read_sanitised_id_reg, \ 2329 .val = 0, \ 2330 } 2331 2332 /* 2333 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2334 * For now, these are exposed just like unallocated ID regs: they appear 2335 * RAZ for the guest. 2336 */ 2337 #define ID_HIDDEN(name) { \ 2338 ID_DESC(name), \ 2339 .set_user = set_id_reg, \ 2340 .visibility = raz_visibility, \ 2341 .reset = kvm_read_sanitised_id_reg, \ 2342 .val = 0, \ 2343 } 2344 2345 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2346 struct sys_reg_params *p, 2347 const struct sys_reg_desc *r) 2348 { 2349 if (p->is_write) 2350 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2351 else 2352 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2353 2354 return true; 2355 } 2356 2357 static bool access_elr(struct kvm_vcpu *vcpu, 2358 struct sys_reg_params *p, 2359 const struct sys_reg_desc *r) 2360 { 2361 if (p->is_write) 2362 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2363 else 2364 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2365 2366 return true; 2367 } 2368 2369 static bool access_spsr(struct kvm_vcpu *vcpu, 2370 struct sys_reg_params *p, 2371 const struct sys_reg_desc *r) 2372 { 2373 if (p->is_write) 2374 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2375 else 2376 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2377 2378 return true; 2379 } 2380 2381 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2382 struct sys_reg_params *p, 2383 const struct sys_reg_desc *r) 2384 { 2385 if (p->is_write) 2386 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2387 else 2388 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2389 2390 return true; 2391 } 2392 2393 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2394 { 2395 u64 val = r->val; 2396 2397 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2398 val |= HCR_E2H; 2399 2400 return __vcpu_sys_reg(vcpu, r->reg) = val; 2401 } 2402 2403 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2404 const struct sys_reg_desc *rd, 2405 unsigned int (*fn)(const struct kvm_vcpu *, 2406 const struct sys_reg_desc *)) 2407 { 2408 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2409 } 2410 2411 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2412 const struct sys_reg_desc *rd) 2413 { 2414 return __el2_visibility(vcpu, rd, sve_visibility); 2415 } 2416 2417 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2418 struct sys_reg_params *p, 2419 const struct sys_reg_desc *r) 2420 { 2421 unsigned int vq; 2422 2423 if (guest_hyp_sve_traps_enabled(vcpu)) { 2424 kvm_inject_nested_sve_trap(vcpu); 2425 return true; 2426 } 2427 2428 if (!p->is_write) { 2429 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2430 return true; 2431 } 2432 2433 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2434 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2435 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2436 2437 return true; 2438 } 2439 2440 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2441 struct sys_reg_params *p, 2442 const struct sys_reg_desc *r) 2443 { 2444 if (p->is_write) 2445 return write_to_read_only(vcpu, p, r); 2446 2447 p->regval = kvm_vgic_global_state.ich_vtr_el2; 2448 p->regval &= ~(ICH_VTR_EL2_DVIM | 2449 ICH_VTR_EL2_A3V | 2450 ICH_VTR_EL2_IDbits); 2451 p->regval |= ICH_VTR_EL2_nV4; 2452 2453 return true; 2454 } 2455 2456 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2457 struct sys_reg_params *p, 2458 const struct sys_reg_desc *r) 2459 { 2460 if (p->is_write) 2461 return write_to_read_only(vcpu, p, r); 2462 2463 p->regval = vgic_v3_get_misr(vcpu); 2464 2465 return true; 2466 } 2467 2468 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2469 struct sys_reg_params *p, 2470 const struct sys_reg_desc *r) 2471 { 2472 if (p->is_write) 2473 return write_to_read_only(vcpu, p, r); 2474 2475 p->regval = vgic_v3_get_eisr(vcpu); 2476 2477 return true; 2478 } 2479 2480 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 2481 struct sys_reg_params *p, 2482 const struct sys_reg_desc *r) 2483 { 2484 if (p->is_write) 2485 return write_to_read_only(vcpu, p, r); 2486 2487 p->regval = vgic_v3_get_elrsr(vcpu); 2488 2489 return true; 2490 } 2491 2492 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2493 const struct sys_reg_desc *rd) 2494 { 2495 if (kvm_has_s1poe(vcpu->kvm)) 2496 return 0; 2497 2498 return REG_HIDDEN; 2499 } 2500 2501 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2502 const struct sys_reg_desc *rd) 2503 { 2504 return __el2_visibility(vcpu, rd, s1poe_visibility); 2505 } 2506 2507 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2508 const struct sys_reg_desc *rd) 2509 { 2510 if (kvm_has_tcr2(vcpu->kvm)) 2511 return 0; 2512 2513 return REG_HIDDEN; 2514 } 2515 2516 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2517 const struct sys_reg_desc *rd) 2518 { 2519 return __el2_visibility(vcpu, rd, tcr2_visibility); 2520 } 2521 2522 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2523 const struct sys_reg_desc *rd) 2524 { 2525 if (kvm_has_s1pie(vcpu->kvm)) 2526 return 0; 2527 2528 return REG_HIDDEN; 2529 } 2530 2531 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2532 const struct sys_reg_desc *rd) 2533 { 2534 return __el2_visibility(vcpu, rd, s1pie_visibility); 2535 } 2536 2537 static bool access_mdcr(struct kvm_vcpu *vcpu, 2538 struct sys_reg_params *p, 2539 const struct sys_reg_desc *r) 2540 { 2541 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2542 2543 if (!access_rw(vcpu, p, r)) 2544 return false; 2545 2546 /* 2547 * Request a reload of the PMU to enable/disable the counters affected 2548 * by HPME. 2549 */ 2550 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME) 2551 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2552 2553 return true; 2554 } 2555 2556 2557 /* 2558 * Architected system registers. 2559 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2560 * 2561 * Debug handling: We do trap most, if not all debug related system 2562 * registers. The implementation is good enough to ensure that a guest 2563 * can use these with minimal performance degradation. The drawback is 2564 * that we don't implement any of the external debug architecture. 2565 * This should be revisited if we ever encounter a more demanding 2566 * guest... 2567 */ 2568 static const struct sys_reg_desc sys_reg_descs[] = { 2569 DBG_BCR_BVR_WCR_WVR_EL1(0), 2570 DBG_BCR_BVR_WCR_WVR_EL1(1), 2571 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2572 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2573 DBG_BCR_BVR_WCR_WVR_EL1(2), 2574 DBG_BCR_BVR_WCR_WVR_EL1(3), 2575 DBG_BCR_BVR_WCR_WVR_EL1(4), 2576 DBG_BCR_BVR_WCR_WVR_EL1(5), 2577 DBG_BCR_BVR_WCR_WVR_EL1(6), 2578 DBG_BCR_BVR_WCR_WVR_EL1(7), 2579 DBG_BCR_BVR_WCR_WVR_EL1(8), 2580 DBG_BCR_BVR_WCR_WVR_EL1(9), 2581 DBG_BCR_BVR_WCR_WVR_EL1(10), 2582 DBG_BCR_BVR_WCR_WVR_EL1(11), 2583 DBG_BCR_BVR_WCR_WVR_EL1(12), 2584 DBG_BCR_BVR_WCR_WVR_EL1(13), 2585 DBG_BCR_BVR_WCR_WVR_EL1(14), 2586 DBG_BCR_BVR_WCR_WVR_EL1(15), 2587 2588 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2589 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2590 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2591 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2592 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2593 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2594 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2595 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2596 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2597 2598 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2599 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2600 // DBGDTR[TR]X_EL0 share the same encoding 2601 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2602 2603 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2604 2605 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2606 2607 /* 2608 * ID regs: all ID_SANITISED() entries here must have corresponding 2609 * entries in arm64_ftr_regs[]. 2610 */ 2611 2612 /* AArch64 mappings of the AArch32 ID registers */ 2613 /* CRm=1 */ 2614 AA32_ID_SANITISED(ID_PFR0_EL1), 2615 AA32_ID_SANITISED(ID_PFR1_EL1), 2616 { SYS_DESC(SYS_ID_DFR0_EL1), 2617 .access = access_id_reg, 2618 .get_user = get_id_reg, 2619 .set_user = set_id_dfr0_el1, 2620 .visibility = aa32_id_visibility, 2621 .reset = read_sanitised_id_dfr0_el1, 2622 .val = ID_DFR0_EL1_PerfMon_MASK | 2623 ID_DFR0_EL1_CopDbg_MASK, }, 2624 ID_HIDDEN(ID_AFR0_EL1), 2625 AA32_ID_SANITISED(ID_MMFR0_EL1), 2626 AA32_ID_SANITISED(ID_MMFR1_EL1), 2627 AA32_ID_SANITISED(ID_MMFR2_EL1), 2628 AA32_ID_SANITISED(ID_MMFR3_EL1), 2629 2630 /* CRm=2 */ 2631 AA32_ID_SANITISED(ID_ISAR0_EL1), 2632 AA32_ID_SANITISED(ID_ISAR1_EL1), 2633 AA32_ID_SANITISED(ID_ISAR2_EL1), 2634 AA32_ID_SANITISED(ID_ISAR3_EL1), 2635 AA32_ID_SANITISED(ID_ISAR4_EL1), 2636 AA32_ID_SANITISED(ID_ISAR5_EL1), 2637 AA32_ID_SANITISED(ID_MMFR4_EL1), 2638 AA32_ID_SANITISED(ID_ISAR6_EL1), 2639 2640 /* CRm=3 */ 2641 AA32_ID_SANITISED(MVFR0_EL1), 2642 AA32_ID_SANITISED(MVFR1_EL1), 2643 AA32_ID_SANITISED(MVFR2_EL1), 2644 ID_UNALLOCATED(3,3), 2645 AA32_ID_SANITISED(ID_PFR2_EL1), 2646 ID_HIDDEN(ID_DFR1_EL1), 2647 AA32_ID_SANITISED(ID_MMFR5_EL1), 2648 ID_UNALLOCATED(3,7), 2649 2650 /* AArch64 ID registers */ 2651 /* CRm=4 */ 2652 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2653 ~(ID_AA64PFR0_EL1_AMU | 2654 ID_AA64PFR0_EL1_MPAM | 2655 ID_AA64PFR0_EL1_SVE | 2656 ID_AA64PFR0_EL1_RAS | 2657 ID_AA64PFR0_EL1_AdvSIMD | 2658 ID_AA64PFR0_EL1_FP)), 2659 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2660 ~(ID_AA64PFR1_EL1_PFAR | 2661 ID_AA64PFR1_EL1_DF2 | 2662 ID_AA64PFR1_EL1_MTEX | 2663 ID_AA64PFR1_EL1_THE | 2664 ID_AA64PFR1_EL1_GCS | 2665 ID_AA64PFR1_EL1_MTE_frac | 2666 ID_AA64PFR1_EL1_NMI | 2667 ID_AA64PFR1_EL1_RNDR_trap | 2668 ID_AA64PFR1_EL1_SME | 2669 ID_AA64PFR1_EL1_RES0 | 2670 ID_AA64PFR1_EL1_MPAM_frac | 2671 ID_AA64PFR1_EL1_RAS_frac | 2672 ID_AA64PFR1_EL1_MTE)), 2673 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2674 ID_UNALLOCATED(4,3), 2675 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2676 ID_HIDDEN(ID_AA64SMFR0_EL1), 2677 ID_UNALLOCATED(4,6), 2678 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2679 2680 /* CRm=5 */ 2681 /* 2682 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2683 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2684 * KVM does not trap + emulate the breakpoint registers, and as such 2685 * cannot support a layout that misaligns with the underlying hardware. 2686 * While it may be possible to describe a subset that aligns with 2687 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2688 * simplicity. 2689 * 2690 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2691 * of breakpoints for more details. 2692 */ 2693 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2694 ID_AA64DFR0_EL1_DoubleLock_MASK | 2695 ID_AA64DFR0_EL1_WRPs_MASK | 2696 ID_AA64DFR0_EL1_PMUVer_MASK | 2697 ID_AA64DFR0_EL1_DebugVer_MASK), 2698 ID_SANITISED(ID_AA64DFR1_EL1), 2699 ID_UNALLOCATED(5,2), 2700 ID_UNALLOCATED(5,3), 2701 ID_HIDDEN(ID_AA64AFR0_EL1), 2702 ID_HIDDEN(ID_AA64AFR1_EL1), 2703 ID_UNALLOCATED(5,6), 2704 ID_UNALLOCATED(5,7), 2705 2706 /* CRm=6 */ 2707 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2708 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2709 ID_AA64ISAR1_EL1_GPA | 2710 ID_AA64ISAR1_EL1_API | 2711 ID_AA64ISAR1_EL1_APA)), 2712 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2713 ID_AA64ISAR2_EL1_APA3 | 2714 ID_AA64ISAR2_EL1_GPA3)), 2715 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2716 ID_AA64ISAR3_EL1_FAMINMAX)), 2717 ID_UNALLOCATED(6,4), 2718 ID_UNALLOCATED(6,5), 2719 ID_UNALLOCATED(6,6), 2720 ID_UNALLOCATED(6,7), 2721 2722 /* CRm=7 */ 2723 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2724 ID_AA64MMFR0_EL1_TGRAN4_2 | 2725 ID_AA64MMFR0_EL1_TGRAN64_2 | 2726 ID_AA64MMFR0_EL1_TGRAN16_2 | 2727 ID_AA64MMFR0_EL1_ASIDBITS)), 2728 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2729 ID_AA64MMFR1_EL1_HCX | 2730 ID_AA64MMFR1_EL1_TWED | 2731 ID_AA64MMFR1_EL1_XNX | 2732 ID_AA64MMFR1_EL1_VH | 2733 ID_AA64MMFR1_EL1_VMIDBits)), 2734 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2735 ID_AA64MMFR2_EL1_EVT | 2736 ID_AA64MMFR2_EL1_FWB | 2737 ID_AA64MMFR2_EL1_IDS | 2738 ID_AA64MMFR2_EL1_NV | 2739 ID_AA64MMFR2_EL1_CCIDX)), 2740 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2741 ID_AA64MMFR3_EL1_S1PIE | 2742 ID_AA64MMFR3_EL1_S1POE)), 2743 ID_SANITISED(ID_AA64MMFR4_EL1), 2744 ID_UNALLOCATED(7,5), 2745 ID_UNALLOCATED(7,6), 2746 ID_UNALLOCATED(7,7), 2747 2748 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2749 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2750 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2751 2752 MTE_REG(RGSR_EL1), 2753 MTE_REG(GCR_EL1), 2754 2755 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2756 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2757 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2758 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2759 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2760 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2761 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2762 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2763 .visibility = tcr2_visibility }, 2764 2765 PTRAUTH_KEY(APIA), 2766 PTRAUTH_KEY(APIB), 2767 PTRAUTH_KEY(APDA), 2768 PTRAUTH_KEY(APDB), 2769 PTRAUTH_KEY(APGA), 2770 2771 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2772 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2773 2774 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2775 2776 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2777 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2778 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2779 2780 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2781 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2782 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2783 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2784 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2785 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2786 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2787 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2788 2789 MTE_REG(TFSR_EL1), 2790 MTE_REG(TFSRE0_EL1), 2791 2792 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2793 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2794 2795 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2796 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2797 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2798 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2799 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2800 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2801 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2802 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2803 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2804 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2805 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2806 /* PMBIDR_EL1 is not trapped */ 2807 2808 { PMU_SYS_REG(PMINTENSET_EL1), 2809 .access = access_pminten, .reg = PMINTENSET_EL1, 2810 .get_user = get_pmreg, .set_user = set_pmreg }, 2811 { PMU_SYS_REG(PMINTENCLR_EL1), 2812 .access = access_pminten, .reg = PMINTENSET_EL1, 2813 .get_user = get_pmreg, .set_user = set_pmreg }, 2814 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2815 2816 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2817 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2818 .visibility = s1pie_visibility }, 2819 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2820 .visibility = s1pie_visibility }, 2821 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2822 .visibility = s1poe_visibility }, 2823 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2824 2825 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2826 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2827 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2828 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2829 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2830 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2831 2832 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2833 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2834 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2835 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2836 2837 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2838 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2839 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2840 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2841 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2842 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2843 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2844 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2845 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2846 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2847 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2848 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2849 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2850 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2851 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2852 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2853 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2854 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2855 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2856 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2857 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2858 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2859 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2860 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2861 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2862 2863 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2864 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2865 2866 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2867 2868 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2869 2870 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2871 2872 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2873 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2874 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2875 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2876 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2877 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2878 ID_FILTERED(CTR_EL0, ctr_el0, 2879 CTR_EL0_DIC_MASK | 2880 CTR_EL0_IDC_MASK | 2881 CTR_EL0_DminLine_MASK | 2882 CTR_EL0_L1Ip_MASK | 2883 CTR_EL0_IminLine_MASK), 2884 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2885 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2886 2887 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2888 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2889 { PMU_SYS_REG(PMCNTENSET_EL0), 2890 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2891 .get_user = get_pmreg, .set_user = set_pmreg }, 2892 { PMU_SYS_REG(PMCNTENCLR_EL0), 2893 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2894 .get_user = get_pmreg, .set_user = set_pmreg }, 2895 { PMU_SYS_REG(PMOVSCLR_EL0), 2896 .access = access_pmovs, .reg = PMOVSSET_EL0, 2897 .get_user = get_pmreg, .set_user = set_pmreg }, 2898 /* 2899 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2900 * previously (and pointlessly) advertised in the past... 2901 */ 2902 { PMU_SYS_REG(PMSWINC_EL0), 2903 .get_user = get_raz_reg, .set_user = set_wi_reg, 2904 .access = access_pmswinc, .reset = NULL }, 2905 { PMU_SYS_REG(PMSELR_EL0), 2906 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2907 { PMU_SYS_REG(PMCEID0_EL0), 2908 .access = access_pmceid, .reset = NULL }, 2909 { PMU_SYS_REG(PMCEID1_EL0), 2910 .access = access_pmceid, .reset = NULL }, 2911 { PMU_SYS_REG(PMCCNTR_EL0), 2912 .access = access_pmu_evcntr, .reset = reset_unknown, 2913 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2914 { PMU_SYS_REG(PMXEVTYPER_EL0), 2915 .access = access_pmu_evtyper, .reset = NULL }, 2916 { PMU_SYS_REG(PMXEVCNTR_EL0), 2917 .access = access_pmu_evcntr, .reset = NULL }, 2918 /* 2919 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2920 * in 32bit mode. Here we choose to reset it as zero for consistency. 2921 */ 2922 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2923 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2924 { PMU_SYS_REG(PMOVSSET_EL0), 2925 .access = access_pmovs, .reg = PMOVSSET_EL0, 2926 .get_user = get_pmreg, .set_user = set_pmreg }, 2927 2928 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2929 .visibility = s1poe_visibility }, 2930 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2931 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2932 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2933 2934 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2935 2936 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2937 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2938 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2939 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2940 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2941 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2942 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2943 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2944 AMU_AMEVCNTR0_EL0(0), 2945 AMU_AMEVCNTR0_EL0(1), 2946 AMU_AMEVCNTR0_EL0(2), 2947 AMU_AMEVCNTR0_EL0(3), 2948 AMU_AMEVCNTR0_EL0(4), 2949 AMU_AMEVCNTR0_EL0(5), 2950 AMU_AMEVCNTR0_EL0(6), 2951 AMU_AMEVCNTR0_EL0(7), 2952 AMU_AMEVCNTR0_EL0(8), 2953 AMU_AMEVCNTR0_EL0(9), 2954 AMU_AMEVCNTR0_EL0(10), 2955 AMU_AMEVCNTR0_EL0(11), 2956 AMU_AMEVCNTR0_EL0(12), 2957 AMU_AMEVCNTR0_EL0(13), 2958 AMU_AMEVCNTR0_EL0(14), 2959 AMU_AMEVCNTR0_EL0(15), 2960 AMU_AMEVTYPER0_EL0(0), 2961 AMU_AMEVTYPER0_EL0(1), 2962 AMU_AMEVTYPER0_EL0(2), 2963 AMU_AMEVTYPER0_EL0(3), 2964 AMU_AMEVTYPER0_EL0(4), 2965 AMU_AMEVTYPER0_EL0(5), 2966 AMU_AMEVTYPER0_EL0(6), 2967 AMU_AMEVTYPER0_EL0(7), 2968 AMU_AMEVTYPER0_EL0(8), 2969 AMU_AMEVTYPER0_EL0(9), 2970 AMU_AMEVTYPER0_EL0(10), 2971 AMU_AMEVTYPER0_EL0(11), 2972 AMU_AMEVTYPER0_EL0(12), 2973 AMU_AMEVTYPER0_EL0(13), 2974 AMU_AMEVTYPER0_EL0(14), 2975 AMU_AMEVTYPER0_EL0(15), 2976 AMU_AMEVCNTR1_EL0(0), 2977 AMU_AMEVCNTR1_EL0(1), 2978 AMU_AMEVCNTR1_EL0(2), 2979 AMU_AMEVCNTR1_EL0(3), 2980 AMU_AMEVCNTR1_EL0(4), 2981 AMU_AMEVCNTR1_EL0(5), 2982 AMU_AMEVCNTR1_EL0(6), 2983 AMU_AMEVCNTR1_EL0(7), 2984 AMU_AMEVCNTR1_EL0(8), 2985 AMU_AMEVCNTR1_EL0(9), 2986 AMU_AMEVCNTR1_EL0(10), 2987 AMU_AMEVCNTR1_EL0(11), 2988 AMU_AMEVCNTR1_EL0(12), 2989 AMU_AMEVCNTR1_EL0(13), 2990 AMU_AMEVCNTR1_EL0(14), 2991 AMU_AMEVCNTR1_EL0(15), 2992 AMU_AMEVTYPER1_EL0(0), 2993 AMU_AMEVTYPER1_EL0(1), 2994 AMU_AMEVTYPER1_EL0(2), 2995 AMU_AMEVTYPER1_EL0(3), 2996 AMU_AMEVTYPER1_EL0(4), 2997 AMU_AMEVTYPER1_EL0(5), 2998 AMU_AMEVTYPER1_EL0(6), 2999 AMU_AMEVTYPER1_EL0(7), 3000 AMU_AMEVTYPER1_EL0(8), 3001 AMU_AMEVTYPER1_EL0(9), 3002 AMU_AMEVTYPER1_EL0(10), 3003 AMU_AMEVTYPER1_EL0(11), 3004 AMU_AMEVTYPER1_EL0(12), 3005 AMU_AMEVTYPER1_EL0(13), 3006 AMU_AMEVTYPER1_EL0(14), 3007 AMU_AMEVTYPER1_EL0(15), 3008 3009 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 3010 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer }, 3011 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3012 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3013 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3014 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 3015 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 3016 3017 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3018 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer }, 3019 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer }, 3020 3021 /* PMEVCNTRn_EL0 */ 3022 PMU_PMEVCNTR_EL0(0), 3023 PMU_PMEVCNTR_EL0(1), 3024 PMU_PMEVCNTR_EL0(2), 3025 PMU_PMEVCNTR_EL0(3), 3026 PMU_PMEVCNTR_EL0(4), 3027 PMU_PMEVCNTR_EL0(5), 3028 PMU_PMEVCNTR_EL0(6), 3029 PMU_PMEVCNTR_EL0(7), 3030 PMU_PMEVCNTR_EL0(8), 3031 PMU_PMEVCNTR_EL0(9), 3032 PMU_PMEVCNTR_EL0(10), 3033 PMU_PMEVCNTR_EL0(11), 3034 PMU_PMEVCNTR_EL0(12), 3035 PMU_PMEVCNTR_EL0(13), 3036 PMU_PMEVCNTR_EL0(14), 3037 PMU_PMEVCNTR_EL0(15), 3038 PMU_PMEVCNTR_EL0(16), 3039 PMU_PMEVCNTR_EL0(17), 3040 PMU_PMEVCNTR_EL0(18), 3041 PMU_PMEVCNTR_EL0(19), 3042 PMU_PMEVCNTR_EL0(20), 3043 PMU_PMEVCNTR_EL0(21), 3044 PMU_PMEVCNTR_EL0(22), 3045 PMU_PMEVCNTR_EL0(23), 3046 PMU_PMEVCNTR_EL0(24), 3047 PMU_PMEVCNTR_EL0(25), 3048 PMU_PMEVCNTR_EL0(26), 3049 PMU_PMEVCNTR_EL0(27), 3050 PMU_PMEVCNTR_EL0(28), 3051 PMU_PMEVCNTR_EL0(29), 3052 PMU_PMEVCNTR_EL0(30), 3053 /* PMEVTYPERn_EL0 */ 3054 PMU_PMEVTYPER_EL0(0), 3055 PMU_PMEVTYPER_EL0(1), 3056 PMU_PMEVTYPER_EL0(2), 3057 PMU_PMEVTYPER_EL0(3), 3058 PMU_PMEVTYPER_EL0(4), 3059 PMU_PMEVTYPER_EL0(5), 3060 PMU_PMEVTYPER_EL0(6), 3061 PMU_PMEVTYPER_EL0(7), 3062 PMU_PMEVTYPER_EL0(8), 3063 PMU_PMEVTYPER_EL0(9), 3064 PMU_PMEVTYPER_EL0(10), 3065 PMU_PMEVTYPER_EL0(11), 3066 PMU_PMEVTYPER_EL0(12), 3067 PMU_PMEVTYPER_EL0(13), 3068 PMU_PMEVTYPER_EL0(14), 3069 PMU_PMEVTYPER_EL0(15), 3070 PMU_PMEVTYPER_EL0(16), 3071 PMU_PMEVTYPER_EL0(17), 3072 PMU_PMEVTYPER_EL0(18), 3073 PMU_PMEVTYPER_EL0(19), 3074 PMU_PMEVTYPER_EL0(20), 3075 PMU_PMEVTYPER_EL0(21), 3076 PMU_PMEVTYPER_EL0(22), 3077 PMU_PMEVTYPER_EL0(23), 3078 PMU_PMEVTYPER_EL0(24), 3079 PMU_PMEVTYPER_EL0(25), 3080 PMU_PMEVTYPER_EL0(26), 3081 PMU_PMEVTYPER_EL0(27), 3082 PMU_PMEVTYPER_EL0(28), 3083 PMU_PMEVTYPER_EL0(29), 3084 PMU_PMEVTYPER_EL0(30), 3085 /* 3086 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3087 * in 32bit mode. Here we choose to reset it as zero for consistency. 3088 */ 3089 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3090 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3091 3092 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3093 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3094 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3095 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3096 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3097 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0), 3098 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3099 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3100 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3101 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3102 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3103 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3104 3105 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3106 sve_el2_visibility), 3107 3108 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3109 3110 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3111 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3112 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3113 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3114 tcr2_el2_visibility), 3115 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3116 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3117 3118 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3119 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3120 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3121 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3122 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3123 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3124 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3125 3126 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3127 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3128 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3129 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3130 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3131 3132 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3133 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3134 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3135 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3136 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3137 3138 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3139 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3140 3141 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3142 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3143 s1pie_el2_visibility), 3144 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3145 s1pie_el2_visibility), 3146 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3147 s1poe_el2_visibility), 3148 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3149 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3150 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3151 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3152 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3153 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3154 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3155 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3156 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3157 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3158 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3159 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3160 3161 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3162 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3163 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3164 3165 EL2_REG_VNCR(ICH_AP0R0_EL2, reset_val, 0), 3166 EL2_REG_VNCR(ICH_AP0R1_EL2, reset_val, 0), 3167 EL2_REG_VNCR(ICH_AP0R2_EL2, reset_val, 0), 3168 EL2_REG_VNCR(ICH_AP0R3_EL2, reset_val, 0), 3169 EL2_REG_VNCR(ICH_AP1R0_EL2, reset_val, 0), 3170 EL2_REG_VNCR(ICH_AP1R1_EL2, reset_val, 0), 3171 EL2_REG_VNCR(ICH_AP1R2_EL2, reset_val, 0), 3172 EL2_REG_VNCR(ICH_AP1R3_EL2, reset_val, 0), 3173 3174 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3175 3176 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3177 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3178 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3179 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3180 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3181 EL2_REG_VNCR(ICH_VMCR_EL2, reset_val, 0), 3182 3183 EL2_REG_VNCR(ICH_LR0_EL2, reset_val, 0), 3184 EL2_REG_VNCR(ICH_LR1_EL2, reset_val, 0), 3185 EL2_REG_VNCR(ICH_LR2_EL2, reset_val, 0), 3186 EL2_REG_VNCR(ICH_LR3_EL2, reset_val, 0), 3187 EL2_REG_VNCR(ICH_LR4_EL2, reset_val, 0), 3188 EL2_REG_VNCR(ICH_LR5_EL2, reset_val, 0), 3189 EL2_REG_VNCR(ICH_LR6_EL2, reset_val, 0), 3190 EL2_REG_VNCR(ICH_LR7_EL2, reset_val, 0), 3191 EL2_REG_VNCR(ICH_LR8_EL2, reset_val, 0), 3192 EL2_REG_VNCR(ICH_LR9_EL2, reset_val, 0), 3193 EL2_REG_VNCR(ICH_LR10_EL2, reset_val, 0), 3194 EL2_REG_VNCR(ICH_LR11_EL2, reset_val, 0), 3195 EL2_REG_VNCR(ICH_LR12_EL2, reset_val, 0), 3196 EL2_REG_VNCR(ICH_LR13_EL2, reset_val, 0), 3197 EL2_REG_VNCR(ICH_LR14_EL2, reset_val, 0), 3198 EL2_REG_VNCR(ICH_LR15_EL2, reset_val, 0), 3199 3200 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3201 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3202 3203 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3204 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3205 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3206 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0), 3207 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0), 3208 3209 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_hv_timer }, 3210 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0), 3211 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0), 3212 3213 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3214 3215 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3216 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3217 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3218 3219 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3220 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3221 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3222 3223 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3224 }; 3225 3226 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3227 const struct sys_reg_desc *r) 3228 { 3229 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3230 3231 __kvm_at_s1e01(vcpu, op, p->regval); 3232 3233 return true; 3234 } 3235 3236 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3237 const struct sys_reg_desc *r) 3238 { 3239 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3240 3241 /* There is no FGT associated with AT S1E2A :-( */ 3242 if (op == OP_AT_S1E2A && 3243 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3244 kvm_inject_undefined(vcpu); 3245 return false; 3246 } 3247 3248 __kvm_at_s1e2(vcpu, op, p->regval); 3249 3250 return true; 3251 } 3252 3253 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3254 const struct sys_reg_desc *r) 3255 { 3256 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3257 3258 __kvm_at_s12(vcpu, op, p->regval); 3259 3260 return true; 3261 } 3262 3263 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3264 { 3265 struct kvm *kvm = vpcu->kvm; 3266 u8 CRm = sys_reg_CRm(instr); 3267 3268 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3269 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3270 return false; 3271 3272 if (CRm == TLBI_CRm_nROS && 3273 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3274 return false; 3275 3276 return true; 3277 } 3278 3279 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3280 const struct sys_reg_desc *r) 3281 { 3282 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3283 3284 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3285 return undef_access(vcpu, p, r); 3286 3287 write_lock(&vcpu->kvm->mmu_lock); 3288 3289 /* 3290 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3291 * corresponding VMIDs. 3292 */ 3293 kvm_nested_s2_unmap(vcpu->kvm, true); 3294 3295 write_unlock(&vcpu->kvm->mmu_lock); 3296 3297 return true; 3298 } 3299 3300 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3301 { 3302 struct kvm *kvm = vpcu->kvm; 3303 u8 CRm = sys_reg_CRm(instr); 3304 u8 Op2 = sys_reg_Op2(instr); 3305 3306 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3307 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3308 return false; 3309 3310 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3311 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3312 return false; 3313 3314 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3315 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3316 return false; 3317 3318 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3319 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3320 return false; 3321 3322 return true; 3323 } 3324 3325 /* Only defined here as this is an internal "abstraction" */ 3326 union tlbi_info { 3327 struct { 3328 u64 start; 3329 u64 size; 3330 } range; 3331 3332 struct { 3333 u64 addr; 3334 } ipa; 3335 3336 struct { 3337 u64 addr; 3338 u32 encoding; 3339 } va; 3340 }; 3341 3342 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3343 const union tlbi_info *info) 3344 { 3345 /* 3346 * The unmap operation is allowed to drop the MMU lock and block, which 3347 * means that @mmu could be used for a different context than the one 3348 * currently being invalidated. 3349 * 3350 * This behavior is still safe, as: 3351 * 3352 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3353 * the entire MMU before reusing it, which still honors the intent 3354 * of a TLBI. 3355 * 3356 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3357 * and ERET to the guest), other vCPUs are allowed to use stale 3358 * translations. 3359 * 3360 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3361 * at worst may cause more aborts for shadow stage-2 fills. 3362 * 3363 * Dropping the MMU lock also implies that shadow stage-2 fills could 3364 * happen behind the back of the TLBI. This is still safe, though, as 3365 * the L1 needs to put its stage-2 in a consistent state before doing 3366 * the TLBI. 3367 */ 3368 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3369 } 3370 3371 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3372 const struct sys_reg_desc *r) 3373 { 3374 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3375 u64 limit, vttbr; 3376 3377 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3378 return undef_access(vcpu, p, r); 3379 3380 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3381 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3382 3383 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3384 &(union tlbi_info) { 3385 .range = { 3386 .start = 0, 3387 .size = limit, 3388 }, 3389 }, 3390 s2_mmu_unmap_range); 3391 3392 return true; 3393 } 3394 3395 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3396 const struct sys_reg_desc *r) 3397 { 3398 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3399 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3400 u64 base, range, tg, num, scale; 3401 int shift; 3402 3403 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3404 return undef_access(vcpu, p, r); 3405 3406 /* 3407 * Because the shadow S2 structure doesn't necessarily reflect that 3408 * of the guest's S2 (different base granule size, for example), we 3409 * decide to ignore TTL and only use the described range. 3410 */ 3411 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3412 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3413 num = FIELD_GET(GENMASK(43, 39), p->regval); 3414 base = p->regval & GENMASK(36, 0); 3415 3416 switch(tg) { 3417 case 1: 3418 shift = 12; 3419 break; 3420 case 2: 3421 shift = 14; 3422 break; 3423 case 3: 3424 default: /* IMPDEF: handle tg==0 as 64k */ 3425 shift = 16; 3426 break; 3427 } 3428 3429 base <<= shift; 3430 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3431 3432 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3433 &(union tlbi_info) { 3434 .range = { 3435 .start = base, 3436 .size = range, 3437 }, 3438 }, 3439 s2_mmu_unmap_range); 3440 3441 return true; 3442 } 3443 3444 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3445 const union tlbi_info *info) 3446 { 3447 unsigned long max_size; 3448 u64 base_addr; 3449 3450 /* 3451 * We drop a number of things from the supplied value: 3452 * 3453 * - NS bit: we're non-secure only. 3454 * 3455 * - IPA[51:48]: We don't support 52bit IPA just yet... 3456 * 3457 * And of course, adjust the IPA to be on an actual address. 3458 */ 3459 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3460 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3461 base_addr &= ~(max_size - 1); 3462 3463 /* 3464 * See comment in s2_mmu_unmap_range() for why this is allowed to 3465 * reschedule. 3466 */ 3467 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3468 } 3469 3470 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3471 const struct sys_reg_desc *r) 3472 { 3473 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3474 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3475 3476 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3477 return undef_access(vcpu, p, r); 3478 3479 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3480 &(union tlbi_info) { 3481 .ipa = { 3482 .addr = p->regval, 3483 }, 3484 }, 3485 s2_mmu_unmap_ipa); 3486 3487 return true; 3488 } 3489 3490 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3491 const union tlbi_info *info) 3492 { 3493 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3494 } 3495 3496 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3497 const struct sys_reg_desc *r) 3498 { 3499 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3500 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3501 3502 /* 3503 * If we're here, this is because we've trapped on a EL1 TLBI 3504 * instruction that affects the EL1 translation regime while 3505 * we're running in a context that doesn't allow us to let the 3506 * HW do its thing (aka vEL2): 3507 * 3508 * - HCR_EL2.E2H == 0 : a non-VHE guest 3509 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3510 * 3511 * We don't expect these helpers to ever be called when running 3512 * in a vEL1 context. 3513 */ 3514 3515 WARN_ON(!vcpu_is_el2(vcpu)); 3516 3517 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3518 return undef_access(vcpu, p, r); 3519 3520 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3521 &(union tlbi_info) { 3522 .va = { 3523 .addr = p->regval, 3524 .encoding = sys_encoding, 3525 }, 3526 }, 3527 s2_mmu_tlbi_s1e1); 3528 3529 return true; 3530 } 3531 3532 #define SYS_INSN(insn, access_fn) \ 3533 { \ 3534 SYS_DESC(OP_##insn), \ 3535 .access = (access_fn), \ 3536 } 3537 3538 static struct sys_reg_desc sys_insn_descs[] = { 3539 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3540 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3541 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3542 3543 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3544 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3545 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3546 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3547 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3548 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3549 3550 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3551 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3552 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3553 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3554 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3555 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3556 3557 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3558 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3559 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3560 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3561 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3562 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3563 3564 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3565 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3566 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3567 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3568 3569 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3570 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3571 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3572 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3573 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3574 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3575 3576 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3577 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3578 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3579 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3580 3581 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3582 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3583 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3584 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3585 3586 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3587 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3588 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3589 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3590 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3591 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3592 3593 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3594 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3595 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3596 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3597 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3598 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3599 3600 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3601 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3602 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3603 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3604 3605 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3606 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3607 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3608 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3609 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3610 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3611 3612 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3613 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3614 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3615 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3616 3617 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3618 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3619 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3620 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3621 3622 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3623 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3624 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3625 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3626 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3627 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3628 3629 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3630 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3631 SYS_INSN(AT_S12E1R, handle_at_s12), 3632 SYS_INSN(AT_S12E1W, handle_at_s12), 3633 SYS_INSN(AT_S12E0R, handle_at_s12), 3634 SYS_INSN(AT_S12E0W, handle_at_s12), 3635 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3636 3637 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3638 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3639 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3640 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3641 3642 SYS_INSN(TLBI_ALLE2OS, undef_access), 3643 SYS_INSN(TLBI_VAE2OS, undef_access), 3644 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3645 SYS_INSN(TLBI_VALE2OS, undef_access), 3646 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3647 3648 SYS_INSN(TLBI_RVAE2IS, undef_access), 3649 SYS_INSN(TLBI_RVALE2IS, undef_access), 3650 3651 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3652 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3653 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3654 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3655 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3656 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3657 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3658 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3659 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3660 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3661 SYS_INSN(TLBI_RVAE2OS, undef_access), 3662 SYS_INSN(TLBI_RVALE2OS, undef_access), 3663 SYS_INSN(TLBI_RVAE2, undef_access), 3664 SYS_INSN(TLBI_RVALE2, undef_access), 3665 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3666 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3667 3668 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3669 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3670 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3671 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3672 3673 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3674 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3675 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3676 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3677 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3678 3679 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3680 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3681 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3682 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3683 3684 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3685 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3686 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3687 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3688 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3689 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3690 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3691 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3692 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3693 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3694 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3695 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3696 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3697 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3698 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3699 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3700 SYS_INSN(TLBI_VAE2NXS, undef_access), 3701 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3702 SYS_INSN(TLBI_VALE2NXS, undef_access), 3703 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3704 }; 3705 3706 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3707 struct sys_reg_params *p, 3708 const struct sys_reg_desc *r) 3709 { 3710 if (p->is_write) { 3711 return ignore_write(vcpu, p); 3712 } else { 3713 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3714 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3715 3716 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3717 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3718 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3719 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3720 (1 << 15) | (el3 << 14) | (el3 << 12)); 3721 return true; 3722 } 3723 } 3724 3725 /* 3726 * AArch32 debug register mappings 3727 * 3728 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3729 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3730 * 3731 * None of the other registers share their location, so treat them as 3732 * if they were 64bit. 3733 */ 3734 #define DBG_BCR_BVR_WCR_WVR(n) \ 3735 /* DBGBVRn */ \ 3736 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 3737 trap_dbg_wb_reg, NULL, n }, \ 3738 /* DBGBCRn */ \ 3739 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 3740 /* DBGWVRn */ \ 3741 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 3742 /* DBGWCRn */ \ 3743 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 3744 3745 #define DBGBXVR(n) \ 3746 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 3747 trap_dbg_wb_reg, NULL, n } 3748 3749 /* 3750 * Trapped cp14 registers. We generally ignore most of the external 3751 * debug, on the principle that they don't really make sense to a 3752 * guest. Revisit this one day, would this principle change. 3753 */ 3754 static const struct sys_reg_desc cp14_regs[] = { 3755 /* DBGDIDR */ 3756 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3757 /* DBGDTRRXext */ 3758 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3759 3760 DBG_BCR_BVR_WCR_WVR(0), 3761 /* DBGDSCRint */ 3762 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3763 DBG_BCR_BVR_WCR_WVR(1), 3764 /* DBGDCCINT */ 3765 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3766 /* DBGDSCRext */ 3767 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3768 DBG_BCR_BVR_WCR_WVR(2), 3769 /* DBGDTR[RT]Xint */ 3770 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3771 /* DBGDTR[RT]Xext */ 3772 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3773 DBG_BCR_BVR_WCR_WVR(3), 3774 DBG_BCR_BVR_WCR_WVR(4), 3775 DBG_BCR_BVR_WCR_WVR(5), 3776 /* DBGWFAR */ 3777 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3778 /* DBGOSECCR */ 3779 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3780 DBG_BCR_BVR_WCR_WVR(6), 3781 /* DBGVCR */ 3782 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3783 DBG_BCR_BVR_WCR_WVR(7), 3784 DBG_BCR_BVR_WCR_WVR(8), 3785 DBG_BCR_BVR_WCR_WVR(9), 3786 DBG_BCR_BVR_WCR_WVR(10), 3787 DBG_BCR_BVR_WCR_WVR(11), 3788 DBG_BCR_BVR_WCR_WVR(12), 3789 DBG_BCR_BVR_WCR_WVR(13), 3790 DBG_BCR_BVR_WCR_WVR(14), 3791 DBG_BCR_BVR_WCR_WVR(15), 3792 3793 /* DBGDRAR (32bit) */ 3794 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3795 3796 DBGBXVR(0), 3797 /* DBGOSLAR */ 3798 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3799 DBGBXVR(1), 3800 /* DBGOSLSR */ 3801 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3802 DBGBXVR(2), 3803 DBGBXVR(3), 3804 /* DBGOSDLR */ 3805 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3806 DBGBXVR(4), 3807 /* DBGPRCR */ 3808 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3809 DBGBXVR(5), 3810 DBGBXVR(6), 3811 DBGBXVR(7), 3812 DBGBXVR(8), 3813 DBGBXVR(9), 3814 DBGBXVR(10), 3815 DBGBXVR(11), 3816 DBGBXVR(12), 3817 DBGBXVR(13), 3818 DBGBXVR(14), 3819 DBGBXVR(15), 3820 3821 /* DBGDSAR (32bit) */ 3822 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3823 3824 /* DBGDEVID2 */ 3825 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3826 /* DBGDEVID1 */ 3827 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3828 /* DBGDEVID */ 3829 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3830 /* DBGCLAIMSET */ 3831 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3832 /* DBGCLAIMCLR */ 3833 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3834 /* DBGAUTHSTATUS */ 3835 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3836 }; 3837 3838 /* Trapped cp14 64bit registers */ 3839 static const struct sys_reg_desc cp14_64_regs[] = { 3840 /* DBGDRAR (64bit) */ 3841 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3842 3843 /* DBGDSAR (64bit) */ 3844 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3845 }; 3846 3847 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3848 AA32(_map), \ 3849 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3850 .visibility = pmu_visibility 3851 3852 /* Macro to expand the PMEVCNTRn register */ 3853 #define PMU_PMEVCNTR(n) \ 3854 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3855 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3856 .access = access_pmu_evcntr } 3857 3858 /* Macro to expand the PMEVTYPERn register */ 3859 #define PMU_PMEVTYPER(n) \ 3860 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3861 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3862 .access = access_pmu_evtyper } 3863 /* 3864 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3865 * depending on the way they are accessed (as a 32bit or a 64bit 3866 * register). 3867 */ 3868 static const struct sys_reg_desc cp15_regs[] = { 3869 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3870 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3871 /* ACTLR */ 3872 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3873 /* ACTLR2 */ 3874 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3875 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3876 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3877 /* TTBCR */ 3878 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3879 /* TTBCR2 */ 3880 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3881 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3882 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3883 /* DFSR */ 3884 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3885 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3886 /* ADFSR */ 3887 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3888 /* AIFSR */ 3889 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3890 /* DFAR */ 3891 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3892 /* IFAR */ 3893 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3894 3895 /* 3896 * DC{C,I,CI}SW operations: 3897 */ 3898 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3899 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3900 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3901 3902 /* PMU */ 3903 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3904 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3905 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3906 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3907 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3908 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3909 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3910 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3911 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3912 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3913 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3914 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3915 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3916 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3917 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3918 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3919 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3920 /* PMMIR */ 3921 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3922 3923 /* PRRR/MAIR0 */ 3924 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3925 /* NMRR/MAIR1 */ 3926 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3927 /* AMAIR0 */ 3928 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3929 /* AMAIR1 */ 3930 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3931 3932 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3933 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3934 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3935 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3936 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3937 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3938 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3939 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3940 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3941 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3942 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3943 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3944 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3945 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3946 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3947 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3948 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3949 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3950 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3951 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3952 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3953 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3954 3955 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3956 3957 /* Arch Tmers */ 3958 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3959 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3960 3961 /* PMEVCNTRn */ 3962 PMU_PMEVCNTR(0), 3963 PMU_PMEVCNTR(1), 3964 PMU_PMEVCNTR(2), 3965 PMU_PMEVCNTR(3), 3966 PMU_PMEVCNTR(4), 3967 PMU_PMEVCNTR(5), 3968 PMU_PMEVCNTR(6), 3969 PMU_PMEVCNTR(7), 3970 PMU_PMEVCNTR(8), 3971 PMU_PMEVCNTR(9), 3972 PMU_PMEVCNTR(10), 3973 PMU_PMEVCNTR(11), 3974 PMU_PMEVCNTR(12), 3975 PMU_PMEVCNTR(13), 3976 PMU_PMEVCNTR(14), 3977 PMU_PMEVCNTR(15), 3978 PMU_PMEVCNTR(16), 3979 PMU_PMEVCNTR(17), 3980 PMU_PMEVCNTR(18), 3981 PMU_PMEVCNTR(19), 3982 PMU_PMEVCNTR(20), 3983 PMU_PMEVCNTR(21), 3984 PMU_PMEVCNTR(22), 3985 PMU_PMEVCNTR(23), 3986 PMU_PMEVCNTR(24), 3987 PMU_PMEVCNTR(25), 3988 PMU_PMEVCNTR(26), 3989 PMU_PMEVCNTR(27), 3990 PMU_PMEVCNTR(28), 3991 PMU_PMEVCNTR(29), 3992 PMU_PMEVCNTR(30), 3993 /* PMEVTYPERn */ 3994 PMU_PMEVTYPER(0), 3995 PMU_PMEVTYPER(1), 3996 PMU_PMEVTYPER(2), 3997 PMU_PMEVTYPER(3), 3998 PMU_PMEVTYPER(4), 3999 PMU_PMEVTYPER(5), 4000 PMU_PMEVTYPER(6), 4001 PMU_PMEVTYPER(7), 4002 PMU_PMEVTYPER(8), 4003 PMU_PMEVTYPER(9), 4004 PMU_PMEVTYPER(10), 4005 PMU_PMEVTYPER(11), 4006 PMU_PMEVTYPER(12), 4007 PMU_PMEVTYPER(13), 4008 PMU_PMEVTYPER(14), 4009 PMU_PMEVTYPER(15), 4010 PMU_PMEVTYPER(16), 4011 PMU_PMEVTYPER(17), 4012 PMU_PMEVTYPER(18), 4013 PMU_PMEVTYPER(19), 4014 PMU_PMEVTYPER(20), 4015 PMU_PMEVTYPER(21), 4016 PMU_PMEVTYPER(22), 4017 PMU_PMEVTYPER(23), 4018 PMU_PMEVTYPER(24), 4019 PMU_PMEVTYPER(25), 4020 PMU_PMEVTYPER(26), 4021 PMU_PMEVTYPER(27), 4022 PMU_PMEVTYPER(28), 4023 PMU_PMEVTYPER(29), 4024 PMU_PMEVTYPER(30), 4025 /* PMCCFILTR */ 4026 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4027 4028 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4029 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4030 4031 /* CCSIDR2 */ 4032 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4033 4034 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4035 }; 4036 4037 static const struct sys_reg_desc cp15_64_regs[] = { 4038 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4039 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4040 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4041 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4042 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4043 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4044 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4045 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4046 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4047 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4048 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4049 }; 4050 4051 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4052 bool is_32) 4053 { 4054 unsigned int i; 4055 4056 for (i = 0; i < n; i++) { 4057 if (!is_32 && table[i].reg && !table[i].reset) { 4058 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4059 &table[i], i, table[i].name); 4060 return false; 4061 } 4062 4063 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4064 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4065 &table[i], i, table[i - 1].name, table[i].name); 4066 return false; 4067 } 4068 } 4069 4070 return true; 4071 } 4072 4073 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4074 { 4075 kvm_inject_undefined(vcpu); 4076 return 1; 4077 } 4078 4079 static void perform_access(struct kvm_vcpu *vcpu, 4080 struct sys_reg_params *params, 4081 const struct sys_reg_desc *r) 4082 { 4083 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4084 4085 /* Check for regs disabled by runtime config */ 4086 if (sysreg_hidden(vcpu, r)) { 4087 kvm_inject_undefined(vcpu); 4088 return; 4089 } 4090 4091 /* 4092 * Not having an accessor means that we have configured a trap 4093 * that we don't know how to handle. This certainly qualifies 4094 * as a gross bug that should be fixed right away. 4095 */ 4096 BUG_ON(!r->access); 4097 4098 /* Skip instruction if instructed so */ 4099 if (likely(r->access(vcpu, params, r))) 4100 kvm_incr_pc(vcpu); 4101 } 4102 4103 /* 4104 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4105 * call the corresponding trap handler. 4106 * 4107 * @params: pointer to the descriptor of the access 4108 * @table: array of trap descriptors 4109 * @num: size of the trap descriptor array 4110 * 4111 * Return true if the access has been handled, false if not. 4112 */ 4113 static bool emulate_cp(struct kvm_vcpu *vcpu, 4114 struct sys_reg_params *params, 4115 const struct sys_reg_desc *table, 4116 size_t num) 4117 { 4118 const struct sys_reg_desc *r; 4119 4120 if (!table) 4121 return false; /* Not handled */ 4122 4123 r = find_reg(params, table, num); 4124 4125 if (r) { 4126 perform_access(vcpu, params, r); 4127 return true; 4128 } 4129 4130 /* Not handled */ 4131 return false; 4132 } 4133 4134 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4135 struct sys_reg_params *params) 4136 { 4137 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4138 int cp = -1; 4139 4140 switch (esr_ec) { 4141 case ESR_ELx_EC_CP15_32: 4142 case ESR_ELx_EC_CP15_64: 4143 cp = 15; 4144 break; 4145 case ESR_ELx_EC_CP14_MR: 4146 case ESR_ELx_EC_CP14_64: 4147 cp = 14; 4148 break; 4149 default: 4150 WARN_ON(1); 4151 } 4152 4153 print_sys_reg_msg(params, 4154 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4155 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4156 kvm_inject_undefined(vcpu); 4157 } 4158 4159 /** 4160 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4161 * @vcpu: The VCPU pointer 4162 * @global: &struct sys_reg_desc 4163 * @nr_global: size of the @global array 4164 */ 4165 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4166 const struct sys_reg_desc *global, 4167 size_t nr_global) 4168 { 4169 struct sys_reg_params params; 4170 u64 esr = kvm_vcpu_get_esr(vcpu); 4171 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4172 int Rt2 = (esr >> 10) & 0x1f; 4173 4174 params.CRm = (esr >> 1) & 0xf; 4175 params.is_write = ((esr & 1) == 0); 4176 4177 params.Op0 = 0; 4178 params.Op1 = (esr >> 16) & 0xf; 4179 params.Op2 = 0; 4180 params.CRn = 0; 4181 4182 /* 4183 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4184 * backends between AArch32 and AArch64, we get away with it. 4185 */ 4186 if (params.is_write) { 4187 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4188 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4189 } 4190 4191 /* 4192 * If the table contains a handler, handle the 4193 * potential register operation in the case of a read and return 4194 * with success. 4195 */ 4196 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4197 /* Split up the value between registers for the read side */ 4198 if (!params.is_write) { 4199 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4200 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4201 } 4202 4203 return 1; 4204 } 4205 4206 unhandled_cp_access(vcpu, ¶ms); 4207 return 1; 4208 } 4209 4210 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4211 4212 /* 4213 * The CP10 ID registers are architecturally mapped to AArch64 feature 4214 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4215 * from AArch32. 4216 */ 4217 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4218 { 4219 u8 reg_id = (esr >> 10) & 0xf; 4220 bool valid; 4221 4222 params->is_write = ((esr & 1) == 0); 4223 params->Op0 = 3; 4224 params->Op1 = 0; 4225 params->CRn = 0; 4226 params->CRm = 3; 4227 4228 /* CP10 ID registers are read-only */ 4229 valid = !params->is_write; 4230 4231 switch (reg_id) { 4232 /* MVFR0 */ 4233 case 0b0111: 4234 params->Op2 = 0; 4235 break; 4236 /* MVFR1 */ 4237 case 0b0110: 4238 params->Op2 = 1; 4239 break; 4240 /* MVFR2 */ 4241 case 0b0101: 4242 params->Op2 = 2; 4243 break; 4244 default: 4245 valid = false; 4246 } 4247 4248 if (valid) 4249 return true; 4250 4251 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4252 params->is_write ? "write" : "read", reg_id); 4253 return false; 4254 } 4255 4256 /** 4257 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4258 * VFP Register' from AArch32. 4259 * @vcpu: The vCPU pointer 4260 * 4261 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4262 * Work out the correct AArch64 system register encoding and reroute to the 4263 * AArch64 system register emulation. 4264 */ 4265 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4266 { 4267 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4268 u64 esr = kvm_vcpu_get_esr(vcpu); 4269 struct sys_reg_params params; 4270 4271 /* UNDEF on any unhandled register access */ 4272 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4273 kvm_inject_undefined(vcpu); 4274 return 1; 4275 } 4276 4277 if (emulate_sys_reg(vcpu, ¶ms)) 4278 vcpu_set_reg(vcpu, Rt, params.regval); 4279 4280 return 1; 4281 } 4282 4283 /** 4284 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4285 * CRn=0, which corresponds to the AArch32 feature 4286 * registers. 4287 * @vcpu: the vCPU pointer 4288 * @params: the system register access parameters. 4289 * 4290 * Our cp15 system register tables do not enumerate the AArch32 feature 4291 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4292 * register encoding can be trivially remapped into the AArch64 for the feature 4293 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4294 * 4295 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4296 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4297 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4298 * treat undefined registers in this range as RAZ. 4299 */ 4300 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4301 struct sys_reg_params *params) 4302 { 4303 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4304 4305 /* Treat impossible writes to RO registers as UNDEFINED */ 4306 if (params->is_write) { 4307 unhandled_cp_access(vcpu, params); 4308 return 1; 4309 } 4310 4311 params->Op0 = 3; 4312 4313 /* 4314 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4315 * Avoid conflicting with future expansion of AArch64 feature registers 4316 * and simply treat them as RAZ here. 4317 */ 4318 if (params->CRm > 3) 4319 params->regval = 0; 4320 else if (!emulate_sys_reg(vcpu, params)) 4321 return 1; 4322 4323 vcpu_set_reg(vcpu, Rt, params->regval); 4324 return 1; 4325 } 4326 4327 /** 4328 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4329 * @vcpu: The VCPU pointer 4330 * @params: &struct sys_reg_params 4331 * @global: &struct sys_reg_desc 4332 * @nr_global: size of the @global array 4333 */ 4334 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4335 struct sys_reg_params *params, 4336 const struct sys_reg_desc *global, 4337 size_t nr_global) 4338 { 4339 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4340 4341 params->regval = vcpu_get_reg(vcpu, Rt); 4342 4343 if (emulate_cp(vcpu, params, global, nr_global)) { 4344 if (!params->is_write) 4345 vcpu_set_reg(vcpu, Rt, params->regval); 4346 return 1; 4347 } 4348 4349 unhandled_cp_access(vcpu, params); 4350 return 1; 4351 } 4352 4353 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4354 { 4355 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4356 } 4357 4358 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4359 { 4360 struct sys_reg_params params; 4361 4362 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4363 4364 /* 4365 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4366 * system register table. Registers in the ID range where CRm=0 are 4367 * excluded from this scheme as they do not trivially map into AArch64 4368 * system register encodings. 4369 */ 4370 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4371 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4372 4373 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4374 } 4375 4376 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4377 { 4378 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4379 } 4380 4381 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4382 { 4383 struct sys_reg_params params; 4384 4385 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4386 4387 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4388 } 4389 4390 /** 4391 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4392 * @vcpu: The VCPU pointer 4393 * @params: Decoded system register parameters 4394 * 4395 * Return: true if the system register access was successful, false otherwise. 4396 */ 4397 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4398 struct sys_reg_params *params) 4399 { 4400 const struct sys_reg_desc *r; 4401 4402 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4403 if (likely(r)) { 4404 perform_access(vcpu, params, r); 4405 return true; 4406 } 4407 4408 print_sys_reg_msg(params, 4409 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4410 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4411 kvm_inject_undefined(vcpu); 4412 4413 return false; 4414 } 4415 4416 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4417 { 4418 unsigned long i, idreg_idx = 0; 4419 4420 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4421 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4422 4423 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4424 continue; 4425 4426 if (idreg_idx == pos) 4427 return r; 4428 4429 idreg_idx++; 4430 } 4431 4432 return NULL; 4433 } 4434 4435 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4436 { 4437 struct kvm *kvm = s->private; 4438 u8 *iter; 4439 4440 mutex_lock(&kvm->arch.config_lock); 4441 4442 iter = &kvm->arch.idreg_debugfs_iter; 4443 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4444 *iter == (u8)~0) { 4445 *iter = *pos; 4446 if (!idregs_debug_find(kvm, *iter)) 4447 iter = NULL; 4448 } else { 4449 iter = ERR_PTR(-EBUSY); 4450 } 4451 4452 mutex_unlock(&kvm->arch.config_lock); 4453 4454 return iter; 4455 } 4456 4457 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4458 { 4459 struct kvm *kvm = s->private; 4460 4461 (*pos)++; 4462 4463 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4464 kvm->arch.idreg_debugfs_iter++; 4465 4466 return &kvm->arch.idreg_debugfs_iter; 4467 } 4468 4469 return NULL; 4470 } 4471 4472 static void idregs_debug_stop(struct seq_file *s, void *v) 4473 { 4474 struct kvm *kvm = s->private; 4475 4476 if (IS_ERR(v)) 4477 return; 4478 4479 mutex_lock(&kvm->arch.config_lock); 4480 4481 kvm->arch.idreg_debugfs_iter = ~0; 4482 4483 mutex_unlock(&kvm->arch.config_lock); 4484 } 4485 4486 static int idregs_debug_show(struct seq_file *s, void *v) 4487 { 4488 const struct sys_reg_desc *desc; 4489 struct kvm *kvm = s->private; 4490 4491 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4492 4493 if (!desc->name) 4494 return 0; 4495 4496 seq_printf(s, "%20s:\t%016llx\n", 4497 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4498 4499 return 0; 4500 } 4501 4502 static const struct seq_operations idregs_debug_sops = { 4503 .start = idregs_debug_start, 4504 .next = idregs_debug_next, 4505 .stop = idregs_debug_stop, 4506 .show = idregs_debug_show, 4507 }; 4508 4509 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4510 4511 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4512 { 4513 kvm->arch.idreg_debugfs_iter = ~0; 4514 4515 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4516 &idregs_debug_fops); 4517 } 4518 4519 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4520 { 4521 u32 id = reg_to_encoding(reg); 4522 struct kvm *kvm = vcpu->kvm; 4523 4524 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4525 return; 4526 4527 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4528 } 4529 4530 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4531 const struct sys_reg_desc *reg) 4532 { 4533 if (kvm_vcpu_initialized(vcpu)) 4534 return; 4535 4536 reg->reset(vcpu, reg); 4537 } 4538 4539 /** 4540 * kvm_reset_sys_regs - sets system registers to reset value 4541 * @vcpu: The VCPU pointer 4542 * 4543 * This function finds the right table above and sets the registers on the 4544 * virtual CPU struct to their architecturally defined reset values. 4545 */ 4546 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4547 { 4548 struct kvm *kvm = vcpu->kvm; 4549 unsigned long i; 4550 4551 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4552 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4553 4554 if (!r->reset) 4555 continue; 4556 4557 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4558 reset_vm_ftr_id_reg(vcpu, r); 4559 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4560 reset_vcpu_ftr_id_reg(vcpu, r); 4561 else 4562 r->reset(vcpu, r); 4563 4564 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 4565 (void)__vcpu_sys_reg(vcpu, r->reg); 4566 } 4567 4568 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4569 } 4570 4571 /** 4572 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4573 * trap on a guest execution 4574 * @vcpu: The VCPU pointer 4575 */ 4576 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4577 { 4578 const struct sys_reg_desc *desc = NULL; 4579 struct sys_reg_params params; 4580 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4581 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4582 int sr_idx; 4583 4584 trace_kvm_handle_sys_reg(esr); 4585 4586 if (triage_sysreg_trap(vcpu, &sr_idx)) 4587 return 1; 4588 4589 params = esr_sys64_to_params(esr); 4590 params.regval = vcpu_get_reg(vcpu, Rt); 4591 4592 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4593 if (params.Op0 == 2 || params.Op0 == 3) 4594 desc = &sys_reg_descs[sr_idx]; 4595 else 4596 desc = &sys_insn_descs[sr_idx]; 4597 4598 perform_access(vcpu, ¶ms, desc); 4599 4600 /* Read from system register? */ 4601 if (!params.is_write && 4602 (params.Op0 == 2 || params.Op0 == 3)) 4603 vcpu_set_reg(vcpu, Rt, params.regval); 4604 4605 return 1; 4606 } 4607 4608 /****************************************************************************** 4609 * Userspace API 4610 *****************************************************************************/ 4611 4612 static bool index_to_params(u64 id, struct sys_reg_params *params) 4613 { 4614 switch (id & KVM_REG_SIZE_MASK) { 4615 case KVM_REG_SIZE_U64: 4616 /* Any unused index bits means it's not valid. */ 4617 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4618 | KVM_REG_ARM_COPROC_MASK 4619 | KVM_REG_ARM64_SYSREG_OP0_MASK 4620 | KVM_REG_ARM64_SYSREG_OP1_MASK 4621 | KVM_REG_ARM64_SYSREG_CRN_MASK 4622 | KVM_REG_ARM64_SYSREG_CRM_MASK 4623 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4624 return false; 4625 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4626 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4627 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4628 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4629 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4630 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4631 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4632 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4633 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4634 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4635 return true; 4636 default: 4637 return false; 4638 } 4639 } 4640 4641 const struct sys_reg_desc *get_reg_by_id(u64 id, 4642 const struct sys_reg_desc table[], 4643 unsigned int num) 4644 { 4645 struct sys_reg_params params; 4646 4647 if (!index_to_params(id, ¶ms)) 4648 return NULL; 4649 4650 return find_reg(¶ms, table, num); 4651 } 4652 4653 /* Decode an index value, and find the sys_reg_desc entry. */ 4654 static const struct sys_reg_desc * 4655 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4656 const struct sys_reg_desc table[], unsigned int num) 4657 4658 { 4659 const struct sys_reg_desc *r; 4660 4661 /* We only do sys_reg for now. */ 4662 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4663 return NULL; 4664 4665 r = get_reg_by_id(id, table, num); 4666 4667 /* Not saved in the sys_reg array and not otherwise accessible? */ 4668 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4669 r = NULL; 4670 4671 return r; 4672 } 4673 4674 /* 4675 * These are the invariant sys_reg registers: we let the guest see the 4676 * host versions of these, so they're part of the guest state. 4677 * 4678 * A future CPU may provide a mechanism to present different values to 4679 * the guest, or a future kvm may trap them. 4680 */ 4681 4682 #define FUNCTION_INVARIANT(reg) \ 4683 static u64 reset_##reg(struct kvm_vcpu *v, \ 4684 const struct sys_reg_desc *r) \ 4685 { \ 4686 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4687 return ((struct sys_reg_desc *)r)->val; \ 4688 } 4689 4690 FUNCTION_INVARIANT(midr_el1) 4691 FUNCTION_INVARIANT(revidr_el1) 4692 FUNCTION_INVARIANT(aidr_el1) 4693 4694 /* ->val is filled in by kvm_sys_reg_table_init() */ 4695 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4696 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4697 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4698 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4699 }; 4700 4701 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4702 { 4703 const struct sys_reg_desc *r; 4704 4705 r = get_reg_by_id(id, invariant_sys_regs, 4706 ARRAY_SIZE(invariant_sys_regs)); 4707 if (!r) 4708 return -ENOENT; 4709 4710 return put_user(r->val, uaddr); 4711 } 4712 4713 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4714 { 4715 const struct sys_reg_desc *r; 4716 u64 val; 4717 4718 r = get_reg_by_id(id, invariant_sys_regs, 4719 ARRAY_SIZE(invariant_sys_regs)); 4720 if (!r) 4721 return -ENOENT; 4722 4723 if (get_user(val, uaddr)) 4724 return -EFAULT; 4725 4726 /* This is what we mean by invariant: you can't change it. */ 4727 if (r->val != val) 4728 return -EINVAL; 4729 4730 return 0; 4731 } 4732 4733 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4734 { 4735 u32 val; 4736 u32 __user *uval = uaddr; 4737 4738 /* Fail if we have unknown bits set. */ 4739 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4740 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4741 return -ENOENT; 4742 4743 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4744 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4745 if (KVM_REG_SIZE(id) != 4) 4746 return -ENOENT; 4747 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4748 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4749 if (val >= CSSELR_MAX) 4750 return -ENOENT; 4751 4752 return put_user(get_ccsidr(vcpu, val), uval); 4753 default: 4754 return -ENOENT; 4755 } 4756 } 4757 4758 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4759 { 4760 u32 val, newval; 4761 u32 __user *uval = uaddr; 4762 4763 /* Fail if we have unknown bits set. */ 4764 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4765 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4766 return -ENOENT; 4767 4768 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4769 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4770 if (KVM_REG_SIZE(id) != 4) 4771 return -ENOENT; 4772 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4773 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4774 if (val >= CSSELR_MAX) 4775 return -ENOENT; 4776 4777 if (get_user(newval, uval)) 4778 return -EFAULT; 4779 4780 return set_ccsidr(vcpu, val, newval); 4781 default: 4782 return -ENOENT; 4783 } 4784 } 4785 4786 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4787 const struct sys_reg_desc table[], unsigned int num) 4788 { 4789 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4790 const struct sys_reg_desc *r; 4791 u64 val; 4792 int ret; 4793 4794 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4795 if (!r || sysreg_hidden(vcpu, r)) 4796 return -ENOENT; 4797 4798 if (r->get_user) { 4799 ret = (r->get_user)(vcpu, r, &val); 4800 } else { 4801 val = __vcpu_sys_reg(vcpu, r->reg); 4802 ret = 0; 4803 } 4804 4805 if (!ret) 4806 ret = put_user(val, uaddr); 4807 4808 return ret; 4809 } 4810 4811 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4812 { 4813 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4814 int err; 4815 4816 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4817 return demux_c15_get(vcpu, reg->id, uaddr); 4818 4819 err = get_invariant_sys_reg(reg->id, uaddr); 4820 if (err != -ENOENT) 4821 return err; 4822 4823 return kvm_sys_reg_get_user(vcpu, reg, 4824 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4825 } 4826 4827 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4828 const struct sys_reg_desc table[], unsigned int num) 4829 { 4830 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4831 const struct sys_reg_desc *r; 4832 u64 val; 4833 int ret; 4834 4835 if (get_user(val, uaddr)) 4836 return -EFAULT; 4837 4838 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4839 if (!r || sysreg_hidden(vcpu, r)) 4840 return -ENOENT; 4841 4842 if (sysreg_user_write_ignore(vcpu, r)) 4843 return 0; 4844 4845 if (r->set_user) { 4846 ret = (r->set_user)(vcpu, r, val); 4847 } else { 4848 __vcpu_sys_reg(vcpu, r->reg) = val; 4849 ret = 0; 4850 } 4851 4852 return ret; 4853 } 4854 4855 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4856 { 4857 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4858 int err; 4859 4860 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4861 return demux_c15_set(vcpu, reg->id, uaddr); 4862 4863 err = set_invariant_sys_reg(reg->id, uaddr); 4864 if (err != -ENOENT) 4865 return err; 4866 4867 return kvm_sys_reg_set_user(vcpu, reg, 4868 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4869 } 4870 4871 static unsigned int num_demux_regs(void) 4872 { 4873 return CSSELR_MAX; 4874 } 4875 4876 static int write_demux_regids(u64 __user *uindices) 4877 { 4878 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4879 unsigned int i; 4880 4881 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4882 for (i = 0; i < CSSELR_MAX; i++) { 4883 if (put_user(val | i, uindices)) 4884 return -EFAULT; 4885 uindices++; 4886 } 4887 return 0; 4888 } 4889 4890 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4891 { 4892 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4893 KVM_REG_ARM64_SYSREG | 4894 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4895 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4896 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4897 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4898 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4899 } 4900 4901 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4902 { 4903 if (!*uind) 4904 return true; 4905 4906 if (put_user(sys_reg_to_index(reg), *uind)) 4907 return false; 4908 4909 (*uind)++; 4910 return true; 4911 } 4912 4913 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4914 const struct sys_reg_desc *rd, 4915 u64 __user **uind, 4916 unsigned int *total) 4917 { 4918 /* 4919 * Ignore registers we trap but don't save, 4920 * and for which no custom user accessor is provided. 4921 */ 4922 if (!(rd->reg || rd->get_user)) 4923 return 0; 4924 4925 if (sysreg_hidden(vcpu, rd)) 4926 return 0; 4927 4928 if (!copy_reg_to_user(rd, uind)) 4929 return -EFAULT; 4930 4931 (*total)++; 4932 return 0; 4933 } 4934 4935 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4936 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4937 { 4938 const struct sys_reg_desc *i2, *end2; 4939 unsigned int total = 0; 4940 int err; 4941 4942 i2 = sys_reg_descs; 4943 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4944 4945 while (i2 != end2) { 4946 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4947 if (err) 4948 return err; 4949 } 4950 return total; 4951 } 4952 4953 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4954 { 4955 return ARRAY_SIZE(invariant_sys_regs) 4956 + num_demux_regs() 4957 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4958 } 4959 4960 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4961 { 4962 unsigned int i; 4963 int err; 4964 4965 /* Then give them all the invariant registers' indices. */ 4966 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4967 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4968 return -EFAULT; 4969 uindices++; 4970 } 4971 4972 err = walk_sys_regs(vcpu, uindices); 4973 if (err < 0) 4974 return err; 4975 uindices += err; 4976 4977 return write_demux_regids(uindices); 4978 } 4979 4980 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4981 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4982 sys_reg_Op1(r), \ 4983 sys_reg_CRn(r), \ 4984 sys_reg_CRm(r), \ 4985 sys_reg_Op2(r)) 4986 4987 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4988 { 4989 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4990 u64 __user *masks = (u64 __user *)range->addr; 4991 4992 /* Only feature id range is supported, reserved[13] must be zero. */ 4993 if (range->range || 4994 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4995 return -EINVAL; 4996 4997 /* Wipe the whole thing first */ 4998 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4999 return -EFAULT; 5000 5001 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5002 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5003 u32 encoding = reg_to_encoding(reg); 5004 u64 val; 5005 5006 if (!is_feature_id_reg(encoding) || !reg->set_user) 5007 continue; 5008 5009 if (!reg->val || 5010 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5011 continue; 5012 } 5013 val = reg->val; 5014 5015 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5016 return -EFAULT; 5017 } 5018 5019 return 0; 5020 } 5021 5022 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5023 { 5024 struct kvm *kvm = vcpu->kvm; 5025 5026 if (has_vhe() || has_hvhe()) 5027 vcpu->arch.hcr_el2 |= HCR_E2H; 5028 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5029 /* route synchronous external abort exceptions to EL2 */ 5030 vcpu->arch.hcr_el2 |= HCR_TEA; 5031 /* trap error record accesses */ 5032 vcpu->arch.hcr_el2 |= HCR_TERR; 5033 } 5034 5035 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5036 vcpu->arch.hcr_el2 |= HCR_FWB; 5037 5038 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5039 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5040 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5041 vcpu->arch.hcr_el2 |= HCR_TID4; 5042 else 5043 vcpu->arch.hcr_el2 |= HCR_TID2; 5044 5045 if (vcpu_el1_is_32bit(vcpu)) 5046 vcpu->arch.hcr_el2 &= ~HCR_RW; 5047 5048 if (kvm_has_mte(vcpu->kvm)) 5049 vcpu->arch.hcr_el2 |= HCR_ATA; 5050 5051 /* 5052 * In the absence of FGT, we cannot independently trap TLBI 5053 * Range instructions. This isn't great, but trapping all 5054 * TLBIs would be far worse. Live with it... 5055 */ 5056 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5057 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5058 } 5059 5060 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5061 { 5062 struct kvm *kvm = vcpu->kvm; 5063 5064 mutex_lock(&kvm->arch.config_lock); 5065 vcpu_set_hcr(vcpu); 5066 vcpu_set_ich_hcr(vcpu); 5067 5068 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 5069 /* 5070 * In general, all HCRX_EL2 bits are gated by a feature. 5071 * The only reason we can set SMPME without checking any 5072 * feature is that its effects are not directly observable 5073 * from the guest. 5074 */ 5075 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 5076 5077 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 5078 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 5079 5080 if (kvm_has_tcr2(kvm)) 5081 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 5082 5083 if (kvm_has_fpmr(kvm)) 5084 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 5085 } 5086 5087 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5088 goto out; 5089 5090 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 5091 HFGxTR_EL2_nMAIR2_EL1 | 5092 HFGxTR_EL2_nS2POR_EL1 | 5093 HFGxTR_EL2_nACCDATA_EL1 | 5094 HFGxTR_EL2_nSMPRI_EL1_MASK | 5095 HFGxTR_EL2_nTPIDR2_EL0_MASK); 5096 5097 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5098 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 5099 HFGITR_EL2_TLBIRVALE1OS | 5100 HFGITR_EL2_TLBIRVAAE1OS | 5101 HFGITR_EL2_TLBIRVAE1OS | 5102 HFGITR_EL2_TLBIVAALE1OS | 5103 HFGITR_EL2_TLBIVALE1OS | 5104 HFGITR_EL2_TLBIVAAE1OS | 5105 HFGITR_EL2_TLBIASIDE1OS | 5106 HFGITR_EL2_TLBIVAE1OS | 5107 HFGITR_EL2_TLBIVMALLE1OS); 5108 5109 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 5110 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 5111 HFGITR_EL2_TLBIRVALE1 | 5112 HFGITR_EL2_TLBIRVAAE1 | 5113 HFGITR_EL2_TLBIRVAE1 | 5114 HFGITR_EL2_TLBIRVAALE1IS| 5115 HFGITR_EL2_TLBIRVALE1IS | 5116 HFGITR_EL2_TLBIRVAAE1IS | 5117 HFGITR_EL2_TLBIRVAE1IS | 5118 HFGITR_EL2_TLBIRVAALE1OS| 5119 HFGITR_EL2_TLBIRVALE1OS | 5120 HFGITR_EL2_TLBIRVAAE1OS | 5121 HFGITR_EL2_TLBIRVAE1OS); 5122 5123 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 5124 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 5125 5126 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 5127 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 5128 HFGITR_EL2_ATS1E1WP); 5129 5130 if (!kvm_has_s1pie(kvm)) 5131 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 5132 HFGxTR_EL2_nPIR_EL1); 5133 5134 if (!kvm_has_s1poe(kvm)) 5135 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 5136 HFGxTR_EL2_nPOR_EL0); 5137 5138 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 5139 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 5140 HAFGRTR_EL2_RES1); 5141 5142 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) { 5143 kvm->arch.fgu[HDFGRTR_GROUP] |= (HDFGRTR_EL2_nBRBDATA | 5144 HDFGRTR_EL2_nBRBCTL | 5145 HDFGRTR_EL2_nBRBIDR); 5146 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nBRBINJ | 5147 HFGITR_EL2_nBRBIALL); 5148 } 5149 5150 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5151 out: 5152 mutex_unlock(&kvm->arch.config_lock); 5153 } 5154 5155 /* 5156 * Perform last adjustments to the ID registers that are implied by the 5157 * configuration outside of the ID regs themselves, as well as any 5158 * initialisation that directly depend on these ID registers (such as 5159 * RES0/RES1 behaviours). This is not the place to configure traps though. 5160 * 5161 * Because this can be called once per CPU, changes must be idempotent. 5162 */ 5163 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5164 { 5165 struct kvm *kvm = vcpu->kvm; 5166 5167 guard(mutex)(&kvm->arch.config_lock); 5168 5169 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5170 irqchip_in_kernel(kvm) && 5171 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5172 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5173 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5174 } 5175 5176 if (vcpu_has_nv(vcpu)) { 5177 int ret = kvm_init_nv_sysregs(vcpu); 5178 if (ret) 5179 return ret; 5180 } 5181 5182 return 0; 5183 } 5184 5185 int __init kvm_sys_reg_table_init(void) 5186 { 5187 bool valid = true; 5188 unsigned int i; 5189 int ret = 0; 5190 5191 /* Make sure tables are unique and in order. */ 5192 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5193 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5194 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5195 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5196 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5197 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5198 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5199 5200 if (!valid) 5201 return -EINVAL; 5202 5203 /* We abuse the reset function to overwrite the table itself. */ 5204 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5205 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5206 5207 ret = populate_nv_trap_config(); 5208 5209 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5210 ret = populate_sysreg_config(sys_reg_descs + i, i); 5211 5212 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5213 ret = populate_sysreg_config(sys_insn_descs + i, i); 5214 5215 return ret; 5216 } 5217