cs35l45-tables.c (6085f9e6dc1973cf98ee7f5dcf629939e50f1b84) cs35l45-tables.c (74b14e2850a34740c121cf2758d4181063d4c77c)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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41EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
42
43static const struct reg_default cs35l45_defaults[] = {
44 { CS35L45_BLOCK_ENABLES, 0x00003323 },
45 { CS35L45_BLOCK_ENABLES2, 0x00000010 },
46 { CS35L45_SYNC_GPIO1, 0x00000007 },
47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
48 { CS35L45_GPIO3, 0x00000005 },
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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41EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
42
43static const struct reg_default cs35l45_defaults[] = {
44 { CS35L45_BLOCK_ENABLES, 0x00003323 },
45 { CS35L45_BLOCK_ENABLES2, 0x00000010 },
46 { CS35L45_SYNC_GPIO1, 0x00000007 },
47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
48 { CS35L45_GPIO3, 0x00000005 },
49 { CS35L45_PWRMGT_CTL, 0x00000000 },
49 { CS35L45_REFCLK_INPUT, 0x00000510 },
50 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
51 { CS35L45_ASP_ENABLES1, 0x00000000 },
52 { CS35L45_ASP_CONTROL1, 0x00000028 },
53 { CS35L45_ASP_CONTROL2, 0x18180200 },
54 { CS35L45_ASP_CONTROL3, 0x00000002 },
55 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
56 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },
57 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 },
58 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 },
59 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
60 { CS35L45_DACPCM1_INPUT, 0x00000008 },
61 { CS35L45_ASPTX1_INPUT, 0x00000018 },
62 { CS35L45_ASPTX2_INPUT, 0x00000019 },
63 { CS35L45_ASPTX3_INPUT, 0x00000020 },
64 { CS35L45_ASPTX4_INPUT, 0x00000028 },
65 { CS35L45_ASPTX5_INPUT, 0x00000048 },
50 { CS35L45_REFCLK_INPUT, 0x00000510 },
51 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
52 { CS35L45_ASP_ENABLES1, 0x00000000 },
53 { CS35L45_ASP_CONTROL1, 0x00000028 },
54 { CS35L45_ASP_CONTROL2, 0x18180200 },
55 { CS35L45_ASP_CONTROL3, 0x00000002 },
56 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
57 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },
58 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 },
59 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 },
60 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
61 { CS35L45_DACPCM1_INPUT, 0x00000008 },
62 { CS35L45_ASPTX1_INPUT, 0x00000018 },
63 { CS35L45_ASPTX2_INPUT, 0x00000019 },
64 { CS35L45_ASPTX3_INPUT, 0x00000020 },
65 { CS35L45_ASPTX4_INPUT, 0x00000028 },
66 { CS35L45_ASPTX5_INPUT, 0x00000048 },
67 { CS35L45_DSP1_RX1_RATE, 0x00000001 },
68 { CS35L45_DSP1_RX2_RATE, 0x00000001 },
69 { CS35L45_DSP1_RX3_RATE, 0x00000001 },
70 { CS35L45_DSP1_RX4_RATE, 0x00000001 },
71 { CS35L45_DSP1_RX5_RATE, 0x00000001 },
72 { CS35L45_DSP1_RX6_RATE, 0x00000001 },
73 { CS35L45_DSP1_RX7_RATE, 0x00000001 },
74 { CS35L45_DSP1_RX8_RATE, 0x00000001 },
75 { CS35L45_DSP1_TX1_RATE, 0x00000001 },
76 { CS35L45_DSP1_TX2_RATE, 0x00000001 },
77 { CS35L45_DSP1_TX3_RATE, 0x00000001 },
78 { CS35L45_DSP1_TX4_RATE, 0x00000001 },
79 { CS35L45_DSP1_TX5_RATE, 0x00000001 },
80 { CS35L45_DSP1_TX6_RATE, 0x00000001 },
81 { CS35L45_DSP1_TX7_RATE, 0x00000001 },
82 { CS35L45_DSP1_TX8_RATE, 0x00000001 },
83 { CS35L45_DSP1RX1_INPUT, 0x00000008 },
84 { CS35L45_DSP1RX2_INPUT, 0x00000009 },
85 { CS35L45_DSP1RX3_INPUT, 0x00000018 },
86 { CS35L45_DSP1RX4_INPUT, 0x00000019 },
87 { CS35L45_DSP1RX5_INPUT, 0x00000020 },
88 { CS35L45_DSP1RX6_INPUT, 0x00000028 },
89 { CS35L45_DSP1RX7_INPUT, 0x0000003A },
90 { CS35L45_DSP1RX8_INPUT, 0x00000028 },
66 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
67 { CS35L45_IRQ1_CFG, 0x00000000 },
68 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
69 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
70 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
71 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
72 { CS35L45_IRQ1_MASK_5, 0x0EF80000 },
73 { CS35L45_IRQ1_MASK_6, 0x00000000 },

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95 case CS35L45_SFT_RESET:
96 case CS35L45_GLOBAL_ENABLES:
97 case CS35L45_BLOCK_ENABLES:
98 case CS35L45_BLOCK_ENABLES2:
99 case CS35L45_ERROR_RELEASE:
100 case CS35L45_SYNC_GPIO1:
101 case CS35L45_INTB_GPIO2_MCLK_REF:
102 case CS35L45_GPIO3:
91 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
92 { CS35L45_IRQ1_CFG, 0x00000000 },
93 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
94 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
95 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
96 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
97 { CS35L45_IRQ1_MASK_5, 0x0EF80000 },
98 { CS35L45_IRQ1_MASK_6, 0x00000000 },

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120 case CS35L45_SFT_RESET:
121 case CS35L45_GLOBAL_ENABLES:
122 case CS35L45_BLOCK_ENABLES:
123 case CS35L45_BLOCK_ENABLES2:
124 case CS35L45_ERROR_RELEASE:
125 case CS35L45_SYNC_GPIO1:
126 case CS35L45_INTB_GPIO2_MCLK_REF:
127 case CS35L45_GPIO3:
128 case CS35L45_PWRMGT_CTL:
103 case CS35L45_REFCLK_INPUT:
104 case CS35L45_GLOBAL_SAMPLE_RATE:
105 case CS35L45_ASP_ENABLES1:
106 case CS35L45_ASP_CONTROL1:
107 case CS35L45_ASP_CONTROL2:
108 case CS35L45_ASP_CONTROL3:
109 case CS35L45_ASP_FRAME_CONTROL1:
110 case CS35L45_ASP_FRAME_CONTROL2:
111 case CS35L45_ASP_FRAME_CONTROL5:
112 case CS35L45_ASP_DATA_CONTROL1:
113 case CS35L45_ASP_DATA_CONTROL5:
114 case CS35L45_DACPCM1_INPUT:
115 case CS35L45_ASPTX1_INPUT:
116 case CS35L45_ASPTX2_INPUT:
117 case CS35L45_ASPTX3_INPUT:
118 case CS35L45_ASPTX4_INPUT:
119 case CS35L45_ASPTX5_INPUT:
129 case CS35L45_REFCLK_INPUT:
130 case CS35L45_GLOBAL_SAMPLE_RATE:
131 case CS35L45_ASP_ENABLES1:
132 case CS35L45_ASP_CONTROL1:
133 case CS35L45_ASP_CONTROL2:
134 case CS35L45_ASP_CONTROL3:
135 case CS35L45_ASP_FRAME_CONTROL1:
136 case CS35L45_ASP_FRAME_CONTROL2:
137 case CS35L45_ASP_FRAME_CONTROL5:
138 case CS35L45_ASP_DATA_CONTROL1:
139 case CS35L45_ASP_DATA_CONTROL5:
140 case CS35L45_DACPCM1_INPUT:
141 case CS35L45_ASPTX1_INPUT:
142 case CS35L45_ASPTX2_INPUT:
143 case CS35L45_ASPTX3_INPUT:
144 case CS35L45_ASPTX4_INPUT:
145 case CS35L45_ASPTX5_INPUT:
146 case CS35L45_DSP1RX1_INPUT:
147 case CS35L45_DSP1RX2_INPUT:
148 case CS35L45_DSP1RX3_INPUT:
149 case CS35L45_DSP1RX4_INPUT:
150 case CS35L45_DSP1RX5_INPUT:
151 case CS35L45_DSP1RX6_INPUT:
152 case CS35L45_DSP1RX7_INPUT:
153 case CS35L45_DSP1RX8_INPUT:
120 case CS35L45_AMP_PCM_CONTROL:
121 case CS35L45_AMP_PCM_HPF_TST:
122 case CS35L45_IRQ1_CFG:
123 case CS35L45_IRQ1_STATUS:
124 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
125 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
126 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
127 case CS35L45_GPIO_STATUS1:
128 case CS35L45_GPIO1_CTRL1:
129 case CS35L45_GPIO2_CTRL1:
130 case CS35L45_GPIO3_CTRL1:
154 case CS35L45_AMP_PCM_CONTROL:
155 case CS35L45_AMP_PCM_HPF_TST:
156 case CS35L45_IRQ1_CFG:
157 case CS35L45_IRQ1_STATUS:
158 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
159 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
160 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
161 case CS35L45_GPIO_STATUS1:
162 case CS35L45_GPIO1_CTRL1:
163 case CS35L45_GPIO2_CTRL1:
164 case CS35L45_GPIO3_CTRL1:
165 case CS35L45_DSP_MBOX_1:
166 case CS35L45_DSP_MBOX_2:
167 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
168 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
169 case CS35L45_DSP1_SYS_ID:
170 case CS35L45_DSP1_CLOCK_FREQ:
171 case CS35L45_DSP1_RX1_RATE:
172 case CS35L45_DSP1_RX2_RATE:
173 case CS35L45_DSP1_RX3_RATE:
174 case CS35L45_DSP1_RX4_RATE:
175 case CS35L45_DSP1_RX5_RATE:
176 case CS35L45_DSP1_RX6_RATE:
177 case CS35L45_DSP1_RX7_RATE:
178 case CS35L45_DSP1_RX8_RATE:
179 case CS35L45_DSP1_TX1_RATE:
180 case CS35L45_DSP1_TX2_RATE:
181 case CS35L45_DSP1_TX3_RATE:
182 case CS35L45_DSP1_TX4_RATE:
183 case CS35L45_DSP1_TX5_RATE:
184 case CS35L45_DSP1_TX6_RATE:
185 case CS35L45_DSP1_TX7_RATE:
186 case CS35L45_DSP1_TX8_RATE:
187 case CS35L45_DSP1_SCRATCH1:
188 case CS35L45_DSP1_SCRATCH2:
189 case CS35L45_DSP1_SCRATCH3:
190 case CS35L45_DSP1_SCRATCH4:
191 case CS35L45_DSP1_CCM_CORE_CONTROL:
192 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
193 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
194 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
195 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
196 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
197 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
198 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
131 return true;
132 default:
133 return false;
134 }
135}
136
137static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
138{
139 switch (reg) {
140 case CS35L45_DEVID ... CS35L45_OTPID:
141 case CS35L45_SFT_RESET:
142 case CS35L45_GLOBAL_ENABLES:
143 case CS35L45_ERROR_RELEASE:
144 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
145 case CS35L45_IRQ1_STATUS:
146 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
147 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
148 case CS35L45_GPIO_STATUS1:
199 return true;
200 default:
201 return false;
202 }
203}
204
205static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
206{
207 switch (reg) {
208 case CS35L45_DEVID ... CS35L45_OTPID:
209 case CS35L45_SFT_RESET:
210 case CS35L45_GLOBAL_ENABLES:
211 case CS35L45_ERROR_RELEASE:
212 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
213 case CS35L45_IRQ1_STATUS:
214 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
215 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
216 case CS35L45_GPIO_STATUS1:
217 case CS35L45_DSP_MBOX_1:
218 case CS35L45_DSP_MBOX_2:
219 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
220 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
221 case CS35L45_DSP1_SYS_ID:
222 case CS35L45_DSP1_CLOCK_FREQ:
223 case CS35L45_DSP1_SCRATCH1:
224 case CS35L45_DSP1_SCRATCH2:
225 case CS35L45_DSP1_SCRATCH3:
226 case CS35L45_DSP1_SCRATCH4:
227 case CS35L45_DSP1_CCM_CORE_CONTROL:
228 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
229 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
230 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
231 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
232 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
233 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
234 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
149 return true;
150 default:
151 return false;
152 }
153}
154
155const struct regmap_config cs35l45_i2c_regmap = {
156 .reg_bits = 32,

--- 81 unchanged lines hidden --- 		235 return true;
236 default:
237 return false;
238 }
239}
240
241const struct regmap_config cs35l45_i2c_regmap = {
242 .reg_bits = 32,

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