1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4 // 5 // Copyright 2019-2022 Cirrus Logic, Inc. 6 // 7 // Author: James Schulman <james.schulman@cirrus.com> 8 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include "cs35l45.h" 13 14 static const struct reg_sequence cs35l45_patch[] = { 15 { 0x00000040, 0x00000055 }, 16 { 0x00000040, 0x000000AA }, 17 { 0x00000044, 0x00000055 }, 18 { 0x00000044, 0x000000AA }, 19 { 0x00006480, 0x0830500A }, 20 { 0x00007C60, 0x1000850B }, 21 { CS35L45_BOOST_OV_CFG, 0x007000D0 }, 22 { CS35L45_LDPM_CONFIG, 0x0001B636 }, 23 { 0x00002C08, 0x00000009 }, 24 { 0x00006850, 0x0A30FFC4 }, 25 { 0x00003820, 0x00040100 }, 26 { 0x00003824, 0x00000000 }, 27 { 0x00007CFC, 0x62870004 }, 28 { 0x00007C60, 0x1001850B }, 29 { 0x00000040, 0x00000000 }, 30 { 0x00000044, 0x00000000 }, 31 { CS35L45_BOOST_CCM_CFG, 0xF0000003 }, 32 { CS35L45_BOOST_DCM_CFG, 0x08710220 }, 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34 }; 35 36 int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37 { 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40 } 41 EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45); 42 43 static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_SYNC_GPIO1, 0x00000007 }, 47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 }, 48 { CS35L45_GPIO3, 0x00000005 }, 49 { CS35L45_PWRMGT_CTL, 0x00000000 }, 50 { CS35L45_REFCLK_INPUT, 0x00000510 }, 51 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 52 { CS35L45_ASP_ENABLES1, 0x00000000 }, 53 { CS35L45_ASP_CONTROL1, 0x00000028 }, 54 { CS35L45_ASP_CONTROL2, 0x18180200 }, 55 { CS35L45_ASP_CONTROL3, 0x00000002 }, 56 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 }, 57 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 }, 58 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 }, 59 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 }, 60 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 }, 61 { CS35L45_DACPCM1_INPUT, 0x00000008 }, 62 { CS35L45_ASPTX1_INPUT, 0x00000018 }, 63 { CS35L45_ASPTX2_INPUT, 0x00000019 }, 64 { CS35L45_ASPTX3_INPUT, 0x00000020 }, 65 { CS35L45_ASPTX4_INPUT, 0x00000028 }, 66 { CS35L45_ASPTX5_INPUT, 0x00000048 }, 67 { CS35L45_DSP1_RX1_RATE, 0x00000001 }, 68 { CS35L45_DSP1_RX2_RATE, 0x00000001 }, 69 { CS35L45_DSP1_RX3_RATE, 0x00000001 }, 70 { CS35L45_DSP1_RX4_RATE, 0x00000001 }, 71 { CS35L45_DSP1_RX5_RATE, 0x00000001 }, 72 { CS35L45_DSP1_RX6_RATE, 0x00000001 }, 73 { CS35L45_DSP1_RX7_RATE, 0x00000001 }, 74 { CS35L45_DSP1_RX8_RATE, 0x00000001 }, 75 { CS35L45_DSP1_TX1_RATE, 0x00000001 }, 76 { CS35L45_DSP1_TX2_RATE, 0x00000001 }, 77 { CS35L45_DSP1_TX3_RATE, 0x00000001 }, 78 { CS35L45_DSP1_TX4_RATE, 0x00000001 }, 79 { CS35L45_DSP1_TX5_RATE, 0x00000001 }, 80 { CS35L45_DSP1_TX6_RATE, 0x00000001 }, 81 { CS35L45_DSP1_TX7_RATE, 0x00000001 }, 82 { CS35L45_DSP1_TX8_RATE, 0x00000001 }, 83 { CS35L45_DSP1RX1_INPUT, 0x00000008 }, 84 { CS35L45_DSP1RX2_INPUT, 0x00000009 }, 85 { CS35L45_DSP1RX3_INPUT, 0x00000018 }, 86 { CS35L45_DSP1RX4_INPUT, 0x00000019 }, 87 { CS35L45_DSP1RX5_INPUT, 0x00000020 }, 88 { CS35L45_DSP1RX6_INPUT, 0x00000028 }, 89 { CS35L45_DSP1RX7_INPUT, 0x0000003A }, 90 { CS35L45_DSP1RX8_INPUT, 0x00000028 }, 91 { CS35L45_AMP_PCM_CONTROL, 0x00100000 }, 92 { CS35L45_IRQ1_CFG, 0x00000000 }, 93 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF }, 94 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF }, 95 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF }, 96 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF }, 97 { CS35L45_IRQ1_MASK_5, 0x0EF80000 }, 98 { CS35L45_IRQ1_MASK_6, 0x00000000 }, 99 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 }, 100 { CS35L45_IRQ1_MASK_8, 0x00003FFF }, 101 { CS35L45_IRQ1_MASK_9, 0x00000000 }, 102 { CS35L45_IRQ1_MASK_10, 0x00000000 }, 103 { CS35L45_IRQ1_MASK_11, 0x00000000 }, 104 { CS35L45_IRQ1_MASK_12, 0x00000000 }, 105 { CS35L45_IRQ1_MASK_13, 0x00000000 }, 106 { CS35L45_IRQ1_MASK_14, 0x00000001 }, 107 { CS35L45_IRQ1_MASK_15, 0x00000000 }, 108 { CS35L45_IRQ1_MASK_16, 0x00000000 }, 109 { CS35L45_IRQ1_MASK_17, 0x00000000 }, 110 { CS35L45_IRQ1_MASK_18, 0x3FE5D0FF }, 111 { CS35L45_GPIO1_CTRL1, 0x81000001 }, 112 { CS35L45_GPIO2_CTRL1, 0x81000001 }, 113 { CS35L45_GPIO3_CTRL1, 0x81000001 }, 114 }; 115 116 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg) 117 { 118 switch (reg) { 119 case CS35L45_DEVID ... CS35L45_OTPID: 120 case CS35L45_SFT_RESET: 121 case CS35L45_GLOBAL_ENABLES: 122 case CS35L45_BLOCK_ENABLES: 123 case CS35L45_BLOCK_ENABLES2: 124 case CS35L45_ERROR_RELEASE: 125 case CS35L45_SYNC_GPIO1: 126 case CS35L45_INTB_GPIO2_MCLK_REF: 127 case CS35L45_GPIO3: 128 case CS35L45_PWRMGT_CTL: 129 case CS35L45_REFCLK_INPUT: 130 case CS35L45_GLOBAL_SAMPLE_RATE: 131 case CS35L45_ASP_ENABLES1: 132 case CS35L45_ASP_CONTROL1: 133 case CS35L45_ASP_CONTROL2: 134 case CS35L45_ASP_CONTROL3: 135 case CS35L45_ASP_FRAME_CONTROL1: 136 case CS35L45_ASP_FRAME_CONTROL2: 137 case CS35L45_ASP_FRAME_CONTROL5: 138 case CS35L45_ASP_DATA_CONTROL1: 139 case CS35L45_ASP_DATA_CONTROL5: 140 case CS35L45_DACPCM1_INPUT: 141 case CS35L45_ASPTX1_INPUT: 142 case CS35L45_ASPTX2_INPUT: 143 case CS35L45_ASPTX3_INPUT: 144 case CS35L45_ASPTX4_INPUT: 145 case CS35L45_ASPTX5_INPUT: 146 case CS35L45_DSP1RX1_INPUT: 147 case CS35L45_DSP1RX2_INPUT: 148 case CS35L45_DSP1RX3_INPUT: 149 case CS35L45_DSP1RX4_INPUT: 150 case CS35L45_DSP1RX5_INPUT: 151 case CS35L45_DSP1RX6_INPUT: 152 case CS35L45_DSP1RX7_INPUT: 153 case CS35L45_DSP1RX8_INPUT: 154 case CS35L45_AMP_PCM_CONTROL: 155 case CS35L45_AMP_PCM_HPF_TST: 156 case CS35L45_IRQ1_CFG: 157 case CS35L45_IRQ1_STATUS: 158 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 159 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 160 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18: 161 case CS35L45_GPIO_STATUS1: 162 case CS35L45_GPIO1_CTRL1: 163 case CS35L45_GPIO2_CTRL1: 164 case CS35L45_GPIO3_CTRL1: 165 case CS35L45_DSP_MBOX_1: 166 case CS35L45_DSP_MBOX_2: 167 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4: 168 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4: 169 case CS35L45_DSP1_SYS_ID: 170 case CS35L45_DSP1_CLOCK_FREQ: 171 case CS35L45_DSP1_RX1_RATE: 172 case CS35L45_DSP1_RX2_RATE: 173 case CS35L45_DSP1_RX3_RATE: 174 case CS35L45_DSP1_RX4_RATE: 175 case CS35L45_DSP1_RX5_RATE: 176 case CS35L45_DSP1_RX6_RATE: 177 case CS35L45_DSP1_RX7_RATE: 178 case CS35L45_DSP1_RX8_RATE: 179 case CS35L45_DSP1_TX1_RATE: 180 case CS35L45_DSP1_TX2_RATE: 181 case CS35L45_DSP1_TX3_RATE: 182 case CS35L45_DSP1_TX4_RATE: 183 case CS35L45_DSP1_TX5_RATE: 184 case CS35L45_DSP1_TX6_RATE: 185 case CS35L45_DSP1_TX7_RATE: 186 case CS35L45_DSP1_TX8_RATE: 187 case CS35L45_DSP1_SCRATCH1: 188 case CS35L45_DSP1_SCRATCH2: 189 case CS35L45_DSP1_SCRATCH3: 190 case CS35L45_DSP1_SCRATCH4: 191 case CS35L45_DSP1_CCM_CORE_CONTROL: 192 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: 193 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: 194 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: 195 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: 196 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: 197 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: 198 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: 199 return true; 200 default: 201 return false; 202 } 203 } 204 205 static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg) 206 { 207 switch (reg) { 208 case CS35L45_DEVID ... CS35L45_OTPID: 209 case CS35L45_SFT_RESET: 210 case CS35L45_GLOBAL_ENABLES: 211 case CS35L45_ERROR_RELEASE: 212 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */ 213 case CS35L45_IRQ1_STATUS: 214 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 215 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 216 case CS35L45_GPIO_STATUS1: 217 case CS35L45_DSP_MBOX_1: 218 case CS35L45_DSP_MBOX_2: 219 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4: 220 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4: 221 case CS35L45_DSP1_SYS_ID: 222 case CS35L45_DSP1_CLOCK_FREQ: 223 case CS35L45_DSP1_SCRATCH1: 224 case CS35L45_DSP1_SCRATCH2: 225 case CS35L45_DSP1_SCRATCH3: 226 case CS35L45_DSP1_SCRATCH4: 227 case CS35L45_DSP1_CCM_CORE_CONTROL: 228 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: 229 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: 230 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: 231 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: 232 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: 233 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: 234 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: 235 return true; 236 default: 237 return false; 238 } 239 } 240 241 const struct regmap_config cs35l45_i2c_regmap = { 242 .reg_bits = 32, 243 .val_bits = 32, 244 .reg_stride = 4, 245 .reg_format_endian = REGMAP_ENDIAN_BIG, 246 .val_format_endian = REGMAP_ENDIAN_BIG, 247 .max_register = CS35L45_LASTREG, 248 .reg_defaults = cs35l45_defaults, 249 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 250 .volatile_reg = cs35l45_volatile_reg, 251 .readable_reg = cs35l45_readable_reg, 252 .cache_type = REGCACHE_RBTREE, 253 }; 254 EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45); 255 256 const struct regmap_config cs35l45_spi_regmap = { 257 .reg_bits = 32, 258 .val_bits = 32, 259 .pad_bits = 16, 260 .reg_stride = 4, 261 .reg_format_endian = REGMAP_ENDIAN_BIG, 262 .val_format_endian = REGMAP_ENDIAN_BIG, 263 .max_register = CS35L45_LASTREG, 264 .reg_defaults = cs35l45_defaults, 265 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 266 .volatile_reg = cs35l45_volatile_reg, 267 .readable_reg = cs35l45_readable_reg, 268 .cache_type = REGCACHE_RBTREE, 269 }; 270 EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45); 271 272 static const struct { 273 u8 cfg_id; 274 u32 freq; 275 } cs35l45_pll_refclk_freq[] = { 276 { 0x0C, 128000 }, 277 { 0x0F, 256000 }, 278 { 0x11, 384000 }, 279 { 0x12, 512000 }, 280 { 0x15, 768000 }, 281 { 0x17, 1024000 }, 282 { 0x19, 1411200 }, 283 { 0x1B, 1536000 }, 284 { 0x1C, 2116800 }, 285 { 0x1D, 2048000 }, 286 { 0x1E, 2304000 }, 287 { 0x1F, 2822400 }, 288 { 0x21, 3072000 }, 289 { 0x23, 4233600 }, 290 { 0x24, 4096000 }, 291 { 0x25, 4608000 }, 292 { 0x26, 5644800 }, 293 { 0x27, 6000000 }, 294 { 0x28, 6144000 }, 295 { 0x29, 6350400 }, 296 { 0x2A, 6912000 }, 297 { 0x2D, 7526400 }, 298 { 0x2E, 8467200 }, 299 { 0x2F, 8192000 }, 300 { 0x30, 9216000 }, 301 { 0x31, 11289600 }, 302 { 0x33, 12288000 }, 303 { 0x37, 16934400 }, 304 { 0x38, 18432000 }, 305 { 0x39, 22579200 }, 306 { 0x3B, 24576000 }, 307 }; 308 309 unsigned int cs35l45_get_clk_freq_id(unsigned int freq) 310 { 311 int i; 312 313 if (freq == 0) 314 return -EINVAL; 315 316 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 317 if (cs35l45_pll_refclk_freq[i].freq == freq) 318 return cs35l45_pll_refclk_freq[i].cfg_id; 319 } 320 321 return -EINVAL; 322 } 323 EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45); 324