1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4 // 5 // Copyright 2019-2022 Cirrus Logic, Inc. 6 // 7 // Author: James Schulman <james.schulman@cirrus.com> 8 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include "cs35l45.h" 13 14 static const struct reg_sequence cs35l45_patch[] = { 15 { 0x00000040, 0x00000055 }, 16 { 0x00000040, 0x000000AA }, 17 { 0x00000044, 0x00000055 }, 18 { 0x00000044, 0x000000AA }, 19 { 0x00006480, 0x0830500A }, 20 { 0x00007C60, 0x1000850B }, 21 { CS35L45_BOOST_OV_CFG, 0x007000D0 }, 22 { CS35L45_LDPM_CONFIG, 0x0001B636 }, 23 { 0x00002C08, 0x00000009 }, 24 { 0x00006850, 0x0A30FFC4 }, 25 { 0x00003820, 0x00040100 }, 26 { 0x00003824, 0x00000000 }, 27 { 0x00007CFC, 0x62870004 }, 28 { 0x00007C60, 0x1001850B }, 29 { 0x00000040, 0x00000000 }, 30 { 0x00000044, 0x00000000 }, 31 { CS35L45_BOOST_CCM_CFG, 0xF0000003 }, 32 { CS35L45_BOOST_DCM_CFG, 0x08710220 }, 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34 }; 35 36 int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37 { 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40 } 41 EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45); 42 43 static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_SYNC_GPIO1, 0x00000007 }, 47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 }, 48 { CS35L45_GPIO3, 0x00000005 }, 49 { CS35L45_REFCLK_INPUT, 0x00000510 }, 50 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 51 { CS35L45_ASP_ENABLES1, 0x00000000 }, 52 { CS35L45_ASP_CONTROL1, 0x00000028 }, 53 { CS35L45_ASP_CONTROL2, 0x18180200 }, 54 { CS35L45_ASP_CONTROL3, 0x00000002 }, 55 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 }, 56 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 }, 57 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 }, 58 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 }, 59 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 }, 60 { CS35L45_DACPCM1_INPUT, 0x00000008 }, 61 { CS35L45_ASPTX1_INPUT, 0x00000018 }, 62 { CS35L45_ASPTX2_INPUT, 0x00000019 }, 63 { CS35L45_ASPTX3_INPUT, 0x00000020 }, 64 { CS35L45_ASPTX4_INPUT, 0x00000028 }, 65 { CS35L45_ASPTX5_INPUT, 0x00000048 }, 66 { CS35L45_AMP_PCM_CONTROL, 0x00100000 }, 67 { CS35L45_IRQ1_CFG, 0x00000000 }, 68 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF }, 69 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF }, 70 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF }, 71 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF }, 72 { CS35L45_IRQ1_MASK_5, 0x0EF80000 }, 73 { CS35L45_IRQ1_MASK_6, 0x00000000 }, 74 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 }, 75 { CS35L45_IRQ1_MASK_8, 0x00003FFF }, 76 { CS35L45_IRQ1_MASK_9, 0x00000000 }, 77 { CS35L45_IRQ1_MASK_10, 0x00000000 }, 78 { CS35L45_IRQ1_MASK_11, 0x00000000 }, 79 { CS35L45_IRQ1_MASK_12, 0x00000000 }, 80 { CS35L45_IRQ1_MASK_13, 0x00000000 }, 81 { CS35L45_IRQ1_MASK_14, 0x00000001 }, 82 { CS35L45_IRQ1_MASK_15, 0x00000000 }, 83 { CS35L45_IRQ1_MASK_16, 0x00000000 }, 84 { CS35L45_IRQ1_MASK_17, 0x00000000 }, 85 { CS35L45_IRQ1_MASK_18, 0x3FE5D0FF }, 86 { CS35L45_GPIO1_CTRL1, 0x81000001 }, 87 { CS35L45_GPIO2_CTRL1, 0x81000001 }, 88 { CS35L45_GPIO3_CTRL1, 0x81000001 }, 89 }; 90 91 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg) 92 { 93 switch (reg) { 94 case CS35L45_DEVID ... CS35L45_OTPID: 95 case CS35L45_SFT_RESET: 96 case CS35L45_GLOBAL_ENABLES: 97 case CS35L45_BLOCK_ENABLES: 98 case CS35L45_BLOCK_ENABLES2: 99 case CS35L45_ERROR_RELEASE: 100 case CS35L45_SYNC_GPIO1: 101 case CS35L45_INTB_GPIO2_MCLK_REF: 102 case CS35L45_GPIO3: 103 case CS35L45_REFCLK_INPUT: 104 case CS35L45_GLOBAL_SAMPLE_RATE: 105 case CS35L45_ASP_ENABLES1: 106 case CS35L45_ASP_CONTROL1: 107 case CS35L45_ASP_CONTROL2: 108 case CS35L45_ASP_CONTROL3: 109 case CS35L45_ASP_FRAME_CONTROL1: 110 case CS35L45_ASP_FRAME_CONTROL2: 111 case CS35L45_ASP_FRAME_CONTROL5: 112 case CS35L45_ASP_DATA_CONTROL1: 113 case CS35L45_ASP_DATA_CONTROL5: 114 case CS35L45_DACPCM1_INPUT: 115 case CS35L45_ASPTX1_INPUT: 116 case CS35L45_ASPTX2_INPUT: 117 case CS35L45_ASPTX3_INPUT: 118 case CS35L45_ASPTX4_INPUT: 119 case CS35L45_ASPTX5_INPUT: 120 case CS35L45_AMP_PCM_CONTROL: 121 case CS35L45_AMP_PCM_HPF_TST: 122 case CS35L45_IRQ1_CFG: 123 case CS35L45_IRQ1_STATUS: 124 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 125 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 126 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18: 127 case CS35L45_GPIO_STATUS1: 128 case CS35L45_GPIO1_CTRL1: 129 case CS35L45_GPIO2_CTRL1: 130 case CS35L45_GPIO3_CTRL1: 131 return true; 132 default: 133 return false; 134 } 135 } 136 137 static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg) 138 { 139 switch (reg) { 140 case CS35L45_DEVID ... CS35L45_OTPID: 141 case CS35L45_SFT_RESET: 142 case CS35L45_GLOBAL_ENABLES: 143 case CS35L45_ERROR_RELEASE: 144 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */ 145 case CS35L45_IRQ1_STATUS: 146 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 147 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 148 case CS35L45_GPIO_STATUS1: 149 return true; 150 default: 151 return false; 152 } 153 } 154 155 const struct regmap_config cs35l45_i2c_regmap = { 156 .reg_bits = 32, 157 .val_bits = 32, 158 .reg_stride = 4, 159 .reg_format_endian = REGMAP_ENDIAN_BIG, 160 .val_format_endian = REGMAP_ENDIAN_BIG, 161 .max_register = CS35L45_LASTREG, 162 .reg_defaults = cs35l45_defaults, 163 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 164 .volatile_reg = cs35l45_volatile_reg, 165 .readable_reg = cs35l45_readable_reg, 166 .cache_type = REGCACHE_RBTREE, 167 }; 168 EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45); 169 170 const struct regmap_config cs35l45_spi_regmap = { 171 .reg_bits = 32, 172 .val_bits = 32, 173 .pad_bits = 16, 174 .reg_stride = 4, 175 .reg_format_endian = REGMAP_ENDIAN_BIG, 176 .val_format_endian = REGMAP_ENDIAN_BIG, 177 .max_register = CS35L45_LASTREG, 178 .reg_defaults = cs35l45_defaults, 179 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 180 .volatile_reg = cs35l45_volatile_reg, 181 .readable_reg = cs35l45_readable_reg, 182 .cache_type = REGCACHE_RBTREE, 183 }; 184 EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45); 185 186 static const struct { 187 u8 cfg_id; 188 u32 freq; 189 } cs35l45_pll_refclk_freq[] = { 190 { 0x0C, 128000 }, 191 { 0x0F, 256000 }, 192 { 0x11, 384000 }, 193 { 0x12, 512000 }, 194 { 0x15, 768000 }, 195 { 0x17, 1024000 }, 196 { 0x19, 1411200 }, 197 { 0x1B, 1536000 }, 198 { 0x1C, 2116800 }, 199 { 0x1D, 2048000 }, 200 { 0x1E, 2304000 }, 201 { 0x1F, 2822400 }, 202 { 0x21, 3072000 }, 203 { 0x23, 4233600 }, 204 { 0x24, 4096000 }, 205 { 0x25, 4608000 }, 206 { 0x26, 5644800 }, 207 { 0x27, 6000000 }, 208 { 0x28, 6144000 }, 209 { 0x29, 6350400 }, 210 { 0x2A, 6912000 }, 211 { 0x2D, 7526400 }, 212 { 0x2E, 8467200 }, 213 { 0x2F, 8192000 }, 214 { 0x30, 9216000 }, 215 { 0x31, 11289600 }, 216 { 0x33, 12288000 }, 217 { 0x37, 16934400 }, 218 { 0x38, 18432000 }, 219 { 0x39, 22579200 }, 220 { 0x3B, 24576000 }, 221 }; 222 223 unsigned int cs35l45_get_clk_freq_id(unsigned int freq) 224 { 225 int i; 226 227 if (freq == 0) 228 return -EINVAL; 229 230 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 231 if (cs35l45_pll_refclk_freq[i].freq == freq) 232 return cs35l45_pll_refclk_freq[i].cfg_id; 233 } 234 235 return -EINVAL; 236 } 237 EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45); 238