mmio.c (8a55712d124fd8a919e8a69b70643e1a97280b4b) mmio.c (4dbcb9125cc3e10a6d879c10e4f5816d05a87c49)
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/platform_device.h>
7#include <linux/pci.h>
8

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20 [INT1_MASK_CSR] = 0xd708c,
21 [INT_MCU_CMD_SOURCE] = 0xd51f0,
22 [INT_MCU_CMD_EVENT] = 0x3108,
23 [WFDMA0_ADDR] = 0xd4000,
24 [WFDMA0_PCIE1_ADDR] = 0xd8000,
25 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
26 [CBTOP1_PHY_END] = 0x77ffffff,
27 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/platform_device.h>
7#include <linux/pci.h>
8

--- 11 unchanged lines hidden (view full) ---

20 [INT1_MASK_CSR] = 0xd708c,
21 [INT_MCU_CMD_SOURCE] = 0xd51f0,
22 [INT_MCU_CMD_EVENT] = 0x3108,
23 [WFDMA0_ADDR] = 0xd4000,
24 [WFDMA0_PCIE1_ADDR] = 0xd8000,
25 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
26 [CBTOP1_PHY_END] = 0x77ffffff,
27 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
28 [FW_EXCEPTION_ADDR] = 0x219848,
28 [FW_ASSERT_STAT_ADDR] = 0x219848,
29 [FW_EXCEPT_TYPE_ADDR] = 0x21987c,
30 [FW_EXCEPT_COUNT_ADDR] = 0x219848,
31 [FW_CIRQ_COUNT_ADDR] = 0x216f94,
32 [FW_CIRQ_IDX_ADDR] = 0x216ef8,
33 [FW_CIRQ_LISR_ADDR] = 0x2170ac,
34 [FW_TASK_ID_ADDR] = 0x216f90,
35 [FW_TASK_IDX_ADDR] = 0x216f9c,
36 [FW_TASK_QID1_ADDR] = 0x219680,
37 [FW_TASK_QID2_ADDR] = 0x219760,
38 [FW_TASK_START_ADDR] = 0x219558,
39 [FW_TASK_END_ADDR] = 0x219554,
40 [FW_TASK_SIZE_ADDR] = 0x219560,
41 [FW_LAST_MSG_ID_ADDR] = 0x216f70,
42 [FW_EINT_INFO_ADDR] = 0x219818,
43 [FW_SCHED_INFO_ADDR] = 0x219828,
29 [SWDEF_BASE_ADDR] = 0x41f200,
30 [TXQ_WED_RING_BASE] = 0xd7300,
31 [RXQ_WED_RING_BASE] = 0xd7410,
32};
33
34static const u32 mt7916_reg[] = {
35 [INT_SOURCE_CSR] = 0xd4200,
36 [INT_MASK_CSR] = 0xd4204,
37 [INT1_SOURCE_CSR] = 0xd8200,
38 [INT1_MASK_CSR] = 0xd8204,
39 [INT_MCU_CMD_SOURCE] = 0xd41f0,
40 [INT_MCU_CMD_EVENT] = 0x2108,
41 [WFDMA0_ADDR] = 0xd4000,
42 [WFDMA0_PCIE1_ADDR] = 0xd8000,
43 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
44 [CBTOP1_PHY_END] = 0x7fffffff,
45 [INFRA_MCU_ADDR_END] = 0x7c085fff,
44 [SWDEF_BASE_ADDR] = 0x41f200,
45 [TXQ_WED_RING_BASE] = 0xd7300,
46 [RXQ_WED_RING_BASE] = 0xd7410,
47};
48
49static const u32 mt7916_reg[] = {
50 [INT_SOURCE_CSR] = 0xd4200,
51 [INT_MASK_CSR] = 0xd4204,
52 [INT1_SOURCE_CSR] = 0xd8200,
53 [INT1_MASK_CSR] = 0xd8204,
54 [INT_MCU_CMD_SOURCE] = 0xd41f0,
55 [INT_MCU_CMD_EVENT] = 0x2108,
56 [WFDMA0_ADDR] = 0xd4000,
57 [WFDMA0_PCIE1_ADDR] = 0xd8000,
58 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
59 [CBTOP1_PHY_END] = 0x7fffffff,
60 [INFRA_MCU_ADDR_END] = 0x7c085fff,
46 [FW_EXCEPTION_ADDR] = 0x022050bc,
61 [FW_ASSERT_STAT_ADDR] = 0x02204c14,
62 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4,
63 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc,
64 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
65 [FW_CIRQ_IDX_ADDR] = 0x02204f84,
66 [FW_CIRQ_LISR_ADDR] = 0x022050d0,
67 [FW_TASK_ID_ADDR] = 0x0220406c,
68 [FW_TASK_IDX_ADDR] = 0x0220500c,
69 [FW_TASK_QID1_ADDR] = 0x022028c8,
70 [FW_TASK_QID2_ADDR] = 0x02202a38,
71 [FW_TASK_START_ADDR] = 0x0220286c,
72 [FW_TASK_END_ADDR] = 0x02202870,
73 [FW_TASK_SIZE_ADDR] = 0x02202878,
74 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8,
75 [FW_EINT_INFO_ADDR] = 0x0220525c,
76 [FW_SCHED_INFO_ADDR] = 0x0220516c,
47 [SWDEF_BASE_ADDR] = 0x411400,
48 [TXQ_WED_RING_BASE] = 0xd7300,
49 [RXQ_WED_RING_BASE] = 0xd7410,
50};
51
52static const u32 mt7986_reg[] = {
53 [INT_SOURCE_CSR] = 0x24200,
54 [INT_MASK_CSR] = 0x24204,
55 [INT1_SOURCE_CSR] = 0x28200,
56 [INT1_MASK_CSR] = 0x28204,
57 [INT_MCU_CMD_SOURCE] = 0x241f0,
58 [INT_MCU_CMD_EVENT] = 0x54000108,
59 [WFDMA0_ADDR] = 0x24000,
60 [WFDMA0_PCIE1_ADDR] = 0x28000,
61 [WFDMA_EXT_CSR_ADDR] = 0x27000,
62 [CBTOP1_PHY_END] = 0x7fffffff,
63 [INFRA_MCU_ADDR_END] = 0x7c085fff,
77 [SWDEF_BASE_ADDR] = 0x411400,
78 [TXQ_WED_RING_BASE] = 0xd7300,
79 [RXQ_WED_RING_BASE] = 0xd7410,
80};
81
82static const u32 mt7986_reg[] = {
83 [INT_SOURCE_CSR] = 0x24200,
84 [INT_MASK_CSR] = 0x24204,
85 [INT1_SOURCE_CSR] = 0x28200,
86 [INT1_MASK_CSR] = 0x28204,
87 [INT_MCU_CMD_SOURCE] = 0x241f0,
88 [INT_MCU_CMD_EVENT] = 0x54000108,
89 [WFDMA0_ADDR] = 0x24000,
90 [WFDMA0_PCIE1_ADDR] = 0x28000,
91 [WFDMA_EXT_CSR_ADDR] = 0x27000,
92 [CBTOP1_PHY_END] = 0x7fffffff,
93 [INFRA_MCU_ADDR_END] = 0x7c085fff,
64 [FW_EXCEPTION_ADDR] = 0x02204ffc,
94 [FW_ASSERT_STAT_ADDR] = 0x02204b54,
95 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc,
96 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc,
97 [FW_CIRQ_COUNT_ADDR] = 0x022001ac,
98 [FW_CIRQ_IDX_ADDR] = 0x02204ec4,
99 [FW_CIRQ_LISR_ADDR] = 0x02205010,
100 [FW_TASK_ID_ADDR] = 0x02204fac,
101 [FW_TASK_IDX_ADDR] = 0x02204f4c,
102 [FW_TASK_QID1_ADDR] = 0x02202814,
103 [FW_TASK_QID2_ADDR] = 0x02202984,
104 [FW_TASK_START_ADDR] = 0x022027b8,
105 [FW_TASK_END_ADDR] = 0x022027bc,
106 [FW_TASK_SIZE_ADDR] = 0x022027c4,
107 [FW_LAST_MSG_ID_ADDR] = 0x02204f28,
108 [FW_EINT_INFO_ADDR] = 0x02205194,
109 [FW_SCHED_INFO_ADDR] = 0x022051a4,
65 [SWDEF_BASE_ADDR] = 0x411400,
66 [TXQ_WED_RING_BASE] = 0x24420,
67 [RXQ_WED_RING_BASE] = 0x24520,
68};
69
70static const u32 mt7915_offs[] = {
71 [TMAC_CDTR] = 0x090,
72 [TMAC_ODTR] = 0x094,

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452 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
453 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
454 return mt7915_reg_map_l1(dev, addr);
455 }
456
457 return mt7915_reg_map_l2(dev, addr);
458}
459
110 [SWDEF_BASE_ADDR] = 0x411400,
111 [TXQ_WED_RING_BASE] = 0x24420,
112 [RXQ_WED_RING_BASE] = 0x24520,
113};
114
115static const u32 mt7915_offs[] = {
116 [TMAC_CDTR] = 0x090,
117 [TMAC_ODTR] = 0x094,

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497 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
498 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
499 return mt7915_reg_map_l1(dev, addr);
500 }
501
502 return mt7915_reg_map_l2(dev, addr);
503}
504
505void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
506 size_t len)
507{
508 u32 addr = __mt7915_reg_addr(dev, offset);
509
510 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
511}
512
460static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
461{
462 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
463 u32 addr = __mt7915_reg_addr(dev, offset);
464
465 return dev->bus_ops->rr(mdev, addr);
466}
467

--- 395 unchanged lines hidden --- 		513static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
514{
515 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
516 u32 addr = __mt7915_reg_addr(dev, offset);
517
518 return dev->bus_ops->rr(mdev, addr);
519}
520

--- 395 unchanged lines hidden ---