1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pci.h> 8 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "../trace.h" 12 13 static bool wed_enable; 14 module_param(wed_enable, bool, 0644); 15 16 static const u32 mt7915_reg[] = { 17 [INT_SOURCE_CSR] = 0xd7010, 18 [INT_MASK_CSR] = 0xd7014, 19 [INT1_SOURCE_CSR] = 0xd7088, 20 [INT1_MASK_CSR] = 0xd708c, 21 [INT_MCU_CMD_SOURCE] = 0xd51f0, 22 [INT_MCU_CMD_EVENT] = 0x3108, 23 [WFDMA0_ADDR] = 0xd4000, 24 [WFDMA0_PCIE1_ADDR] = 0xd8000, 25 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 26 [CBTOP1_PHY_END] = 0x77ffffff, 27 [INFRA_MCU_ADDR_END] = 0x7c3fffff, 28 [FW_ASSERT_STAT_ADDR] = 0x219848, 29 [FW_EXCEPT_TYPE_ADDR] = 0x21987c, 30 [FW_EXCEPT_COUNT_ADDR] = 0x219848, 31 [FW_CIRQ_COUNT_ADDR] = 0x216f94, 32 [FW_CIRQ_IDX_ADDR] = 0x216ef8, 33 [FW_CIRQ_LISR_ADDR] = 0x2170ac, 34 [FW_TASK_ID_ADDR] = 0x216f90, 35 [FW_TASK_IDX_ADDR] = 0x216f9c, 36 [FW_TASK_QID1_ADDR] = 0x219680, 37 [FW_TASK_QID2_ADDR] = 0x219760, 38 [FW_TASK_START_ADDR] = 0x219558, 39 [FW_TASK_END_ADDR] = 0x219554, 40 [FW_TASK_SIZE_ADDR] = 0x219560, 41 [FW_LAST_MSG_ID_ADDR] = 0x216f70, 42 [FW_EINT_INFO_ADDR] = 0x219818, 43 [FW_SCHED_INFO_ADDR] = 0x219828, 44 [SWDEF_BASE_ADDR] = 0x41f200, 45 [TXQ_WED_RING_BASE] = 0xd7300, 46 [RXQ_WED_RING_BASE] = 0xd7410, 47 }; 48 49 static const u32 mt7916_reg[] = { 50 [INT_SOURCE_CSR] = 0xd4200, 51 [INT_MASK_CSR] = 0xd4204, 52 [INT1_SOURCE_CSR] = 0xd8200, 53 [INT1_MASK_CSR] = 0xd8204, 54 [INT_MCU_CMD_SOURCE] = 0xd41f0, 55 [INT_MCU_CMD_EVENT] = 0x2108, 56 [WFDMA0_ADDR] = 0xd4000, 57 [WFDMA0_PCIE1_ADDR] = 0xd8000, 58 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 59 [CBTOP1_PHY_END] = 0x7fffffff, 60 [INFRA_MCU_ADDR_END] = 0x7c085fff, 61 [FW_ASSERT_STAT_ADDR] = 0x02204c14, 62 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4, 63 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc, 64 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 65 [FW_CIRQ_IDX_ADDR] = 0x02204f84, 66 [FW_CIRQ_LISR_ADDR] = 0x022050d0, 67 [FW_TASK_ID_ADDR] = 0x0220406c, 68 [FW_TASK_IDX_ADDR] = 0x0220500c, 69 [FW_TASK_QID1_ADDR] = 0x022028c8, 70 [FW_TASK_QID2_ADDR] = 0x02202a38, 71 [FW_TASK_START_ADDR] = 0x0220286c, 72 [FW_TASK_END_ADDR] = 0x02202870, 73 [FW_TASK_SIZE_ADDR] = 0x02202878, 74 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8, 75 [FW_EINT_INFO_ADDR] = 0x0220525c, 76 [FW_SCHED_INFO_ADDR] = 0x0220516c, 77 [SWDEF_BASE_ADDR] = 0x411400, 78 [TXQ_WED_RING_BASE] = 0xd7300, 79 [RXQ_WED_RING_BASE] = 0xd7410, 80 }; 81 82 static const u32 mt7986_reg[] = { 83 [INT_SOURCE_CSR] = 0x24200, 84 [INT_MASK_CSR] = 0x24204, 85 [INT1_SOURCE_CSR] = 0x28200, 86 [INT1_MASK_CSR] = 0x28204, 87 [INT_MCU_CMD_SOURCE] = 0x241f0, 88 [INT_MCU_CMD_EVENT] = 0x54000108, 89 [WFDMA0_ADDR] = 0x24000, 90 [WFDMA0_PCIE1_ADDR] = 0x28000, 91 [WFDMA_EXT_CSR_ADDR] = 0x27000, 92 [CBTOP1_PHY_END] = 0x7fffffff, 93 [INFRA_MCU_ADDR_END] = 0x7c085fff, 94 [FW_ASSERT_STAT_ADDR] = 0x02204b54, 95 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc, 96 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc, 97 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 98 [FW_CIRQ_IDX_ADDR] = 0x02204ec4, 99 [FW_CIRQ_LISR_ADDR] = 0x02205010, 100 [FW_TASK_ID_ADDR] = 0x02204fac, 101 [FW_TASK_IDX_ADDR] = 0x02204f4c, 102 [FW_TASK_QID1_ADDR] = 0x02202814, 103 [FW_TASK_QID2_ADDR] = 0x02202984, 104 [FW_TASK_START_ADDR] = 0x022027b8, 105 [FW_TASK_END_ADDR] = 0x022027bc, 106 [FW_TASK_SIZE_ADDR] = 0x022027c4, 107 [FW_LAST_MSG_ID_ADDR] = 0x02204f28, 108 [FW_EINT_INFO_ADDR] = 0x02205194, 109 [FW_SCHED_INFO_ADDR] = 0x022051a4, 110 [SWDEF_BASE_ADDR] = 0x411400, 111 [TXQ_WED_RING_BASE] = 0x24420, 112 [RXQ_WED_RING_BASE] = 0x24520, 113 }; 114 115 static const u32 mt7915_offs[] = { 116 [TMAC_CDTR] = 0x090, 117 [TMAC_ODTR] = 0x094, 118 [TMAC_ATCR] = 0x098, 119 [TMAC_TRCR0] = 0x09c, 120 [TMAC_ICR0] = 0x0a4, 121 [TMAC_ICR1] = 0x0b4, 122 [TMAC_CTCR0] = 0x0f4, 123 [TMAC_TFCR0] = 0x1e0, 124 [MDP_BNRCFR0] = 0x070, 125 [MDP_BNRCFR1] = 0x074, 126 [ARB_DRNGR0] = 0x194, 127 [ARB_SCR] = 0x080, 128 [RMAC_MIB_AIRTIME14] = 0x3b8, 129 [AGG_AWSCR0] = 0x05c, 130 [AGG_PCR0] = 0x06c, 131 [AGG_ACR0] = 0x084, 132 [AGG_ACR4] = 0x08c, 133 [AGG_MRCR] = 0x098, 134 [AGG_ATCR1] = 0x0f0, 135 [AGG_ATCR3] = 0x0f4, 136 [LPON_UTTR0] = 0x080, 137 [LPON_UTTR1] = 0x084, 138 [LPON_FRCR] = 0x314, 139 [MIB_SDR3] = 0x014, 140 [MIB_SDR4] = 0x018, 141 [MIB_SDR5] = 0x01c, 142 [MIB_SDR7] = 0x024, 143 [MIB_SDR8] = 0x028, 144 [MIB_SDR9] = 0x02c, 145 [MIB_SDR10] = 0x030, 146 [MIB_SDR11] = 0x034, 147 [MIB_SDR12] = 0x038, 148 [MIB_SDR13] = 0x03c, 149 [MIB_SDR14] = 0x040, 150 [MIB_SDR15] = 0x044, 151 [MIB_SDR16] = 0x048, 152 [MIB_SDR17] = 0x04c, 153 [MIB_SDR18] = 0x050, 154 [MIB_SDR19] = 0x054, 155 [MIB_SDR20] = 0x058, 156 [MIB_SDR21] = 0x05c, 157 [MIB_SDR22] = 0x060, 158 [MIB_SDR23] = 0x064, 159 [MIB_SDR24] = 0x068, 160 [MIB_SDR25] = 0x06c, 161 [MIB_SDR27] = 0x074, 162 [MIB_SDR28] = 0x078, 163 [MIB_SDR29] = 0x07c, 164 [MIB_SDRVEC] = 0x080, 165 [MIB_SDR31] = 0x084, 166 [MIB_SDR32] = 0x088, 167 [MIB_SDRMUBF] = 0x090, 168 [MIB_DR8] = 0x0c0, 169 [MIB_DR9] = 0x0c4, 170 [MIB_DR11] = 0x0cc, 171 [MIB_MB_SDR0] = 0x100, 172 [MIB_MB_SDR1] = 0x104, 173 [TX_AGG_CNT] = 0x0a8, 174 [TX_AGG_CNT2] = 0x164, 175 [MIB_ARNG] = 0x4b8, 176 [WTBLON_TOP_WDUCR] = 0x0, 177 [WTBL_UPDATE] = 0x030, 178 [PLE_FL_Q_EMPTY] = 0x0b0, 179 [PLE_FL_Q_CTRL] = 0x1b0, 180 [PLE_AC_QEMPTY] = 0x500, 181 [PLE_FREEPG_CNT] = 0x100, 182 [PLE_FREEPG_HEAD_TAIL] = 0x104, 183 [PLE_PG_HIF_GROUP] = 0x110, 184 [PLE_HIF_PG_INFO] = 0x114, 185 [AC_OFFSET] = 0x040, 186 [ETBF_PAR_RPT0] = 0x068, 187 }; 188 189 static const u32 mt7916_offs[] = { 190 [TMAC_CDTR] = 0x0c8, 191 [TMAC_ODTR] = 0x0cc, 192 [TMAC_ATCR] = 0x00c, 193 [TMAC_TRCR0] = 0x010, 194 [TMAC_ICR0] = 0x014, 195 [TMAC_ICR1] = 0x018, 196 [TMAC_CTCR0] = 0x114, 197 [TMAC_TFCR0] = 0x0e4, 198 [MDP_BNRCFR0] = 0x090, 199 [MDP_BNRCFR1] = 0x094, 200 [ARB_DRNGR0] = 0x1e0, 201 [ARB_SCR] = 0x000, 202 [RMAC_MIB_AIRTIME14] = 0x0398, 203 [AGG_AWSCR0] = 0x030, 204 [AGG_PCR0] = 0x040, 205 [AGG_ACR0] = 0x054, 206 [AGG_ACR4] = 0x05c, 207 [AGG_MRCR] = 0x068, 208 [AGG_ATCR1] = 0x1a8, 209 [AGG_ATCR3] = 0x080, 210 [LPON_UTTR0] = 0x360, 211 [LPON_UTTR1] = 0x364, 212 [LPON_FRCR] = 0x37c, 213 [MIB_SDR3] = 0x698, 214 [MIB_SDR4] = 0x788, 215 [MIB_SDR5] = 0x780, 216 [MIB_SDR7] = 0x5a8, 217 [MIB_SDR8] = 0x78c, 218 [MIB_SDR9] = 0x024, 219 [MIB_SDR10] = 0x76c, 220 [MIB_SDR11] = 0x790, 221 [MIB_SDR12] = 0x558, 222 [MIB_SDR13] = 0x560, 223 [MIB_SDR14] = 0x564, 224 [MIB_SDR15] = 0x568, 225 [MIB_SDR16] = 0x7fc, 226 [MIB_SDR17] = 0x800, 227 [MIB_SDR18] = 0x030, 228 [MIB_SDR19] = 0x5ac, 229 [MIB_SDR20] = 0x5b0, 230 [MIB_SDR21] = 0x5b4, 231 [MIB_SDR22] = 0x770, 232 [MIB_SDR23] = 0x774, 233 [MIB_SDR24] = 0x778, 234 [MIB_SDR25] = 0x77c, 235 [MIB_SDR27] = 0x080, 236 [MIB_SDR28] = 0x084, 237 [MIB_SDR29] = 0x650, 238 [MIB_SDRVEC] = 0x5a8, 239 [MIB_SDR31] = 0x55c, 240 [MIB_SDR32] = 0x7a8, 241 [MIB_SDRMUBF] = 0x7ac, 242 [MIB_DR8] = 0x56c, 243 [MIB_DR9] = 0x570, 244 [MIB_DR11] = 0x574, 245 [MIB_MB_SDR0] = 0x688, 246 [MIB_MB_SDR1] = 0x690, 247 [TX_AGG_CNT] = 0x7dc, 248 [TX_AGG_CNT2] = 0x7ec, 249 [MIB_ARNG] = 0x0b0, 250 [WTBLON_TOP_WDUCR] = 0x200, 251 [WTBL_UPDATE] = 0x230, 252 [PLE_FL_Q_EMPTY] = 0x360, 253 [PLE_FL_Q_CTRL] = 0x3e0, 254 [PLE_AC_QEMPTY] = 0x600, 255 [PLE_FREEPG_CNT] = 0x380, 256 [PLE_FREEPG_HEAD_TAIL] = 0x384, 257 [PLE_PG_HIF_GROUP] = 0x00c, 258 [PLE_HIF_PG_INFO] = 0x388, 259 [AC_OFFSET] = 0x080, 260 [ETBF_PAR_RPT0] = 0x100, 261 }; 262 263 static const struct mt76_connac_reg_map mt7915_reg_map[] = { 264 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 265 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */ 266 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 267 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 268 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 269 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 270 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 271 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 272 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 273 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 274 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 275 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 276 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 277 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 278 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 279 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 280 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 281 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 282 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 283 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 284 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 285 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 286 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 287 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 288 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 289 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 290 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 291 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 292 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 293 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 294 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 295 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 296 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 297 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 298 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 299 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 300 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 301 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 302 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 303 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 304 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 305 { 0x0, 0x0, 0x0 }, /* imply end of search */ 306 }; 307 308 static const struct mt76_connac_reg_map mt7916_reg_map[] = { 309 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 310 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 311 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */ 312 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 313 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 314 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 315 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 316 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 317 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 318 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 319 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 320 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 321 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 322 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 323 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 324 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 325 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 326 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 327 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 328 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 329 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 330 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 331 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 332 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 333 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 334 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 335 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */ 336 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 337 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 338 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 339 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 340 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 341 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 342 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 343 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 344 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 345 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 346 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 347 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 348 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 349 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */ 350 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 351 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 352 { 0x0, 0x0, 0x0 }, /* imply end of search */ 353 }; 354 355 static const struct mt76_connac_reg_map mt7986_reg_map[] = { 356 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 357 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 358 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */ 359 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 360 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 361 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 362 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 363 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 364 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 365 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 366 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 367 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 368 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 369 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 370 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 371 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 372 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 373 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 374 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 375 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 376 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 377 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 378 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 379 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 380 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 381 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */ 382 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */ 383 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 384 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 385 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 386 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 387 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 388 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 389 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 390 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 391 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 392 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 393 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 394 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 395 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 396 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */ 397 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 398 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */ 399 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */ 400 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */ 401 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */ 402 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */ 403 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */ 404 { 0x0, 0x0, 0x0 }, /* imply end of search */ 405 }; 406 407 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 408 { 409 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 410 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 411 u32 l1_remap; 412 413 if (is_mt7986(&dev->mt76)) 414 return MT_CONN_INFRA_OFFSET(addr); 415 416 l1_remap = is_mt7915(&dev->mt76) ? 417 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916; 418 419 dev->bus_ops->rmw(&dev->mt76, l1_remap, 420 MT_HIF_REMAP_L1_MASK, 421 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 422 /* use read to push write */ 423 dev->bus_ops->rr(&dev->mt76, l1_remap); 424 425 return MT_HIF_REMAP_BASE_L1 + offset; 426 } 427 428 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 429 { 430 u32 offset, base; 431 432 if (is_mt7915(&dev->mt76)) { 433 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 434 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 435 436 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 437 MT_HIF_REMAP_L2_MASK, 438 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 439 440 /* use read to push write */ 441 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 442 } else { 443 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0; 444 445 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr); 446 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr); 447 448 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs, 449 MT_HIF_REMAP_L2_MASK_MT7916, 450 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base)); 451 452 /* use read to push write */ 453 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs); 454 455 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs); 456 } 457 458 return offset; 459 } 460 461 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 462 { 463 int i; 464 465 if (addr < 0x100000) 466 return addr; 467 468 if (!dev->reg.map) { 469 dev_err(dev->mt76.dev, "err: reg_map is null\n"); 470 return addr; 471 } 472 473 for (i = 0; i < dev->reg.map_size; i++) { 474 u32 ofs; 475 476 if (addr < dev->reg.map[i].phys) 477 continue; 478 479 ofs = addr - dev->reg.map[i].phys; 480 if (ofs > dev->reg.map[i].size) 481 continue; 482 483 return dev->reg.map[i].maps + ofs; 484 } 485 486 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 487 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 488 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 489 return mt7915_reg_map_l1(dev, addr); 490 491 if (dev_is_pci(dev->mt76.dev) && 492 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 493 (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) 494 return mt7915_reg_map_l1(dev, addr); 495 496 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 497 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 498 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 499 return mt7915_reg_map_l1(dev, addr); 500 } 501 502 return mt7915_reg_map_l2(dev, addr); 503 } 504 505 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset, 506 size_t len) 507 { 508 u32 addr = __mt7915_reg_addr(dev, offset); 509 510 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 511 } 512 513 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 514 { 515 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 516 u32 addr = __mt7915_reg_addr(dev, offset); 517 518 return dev->bus_ops->rr(mdev, addr); 519 } 520 521 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 522 { 523 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 524 u32 addr = __mt7915_reg_addr(dev, offset); 525 526 dev->bus_ops->wr(mdev, addr, val); 527 } 528 529 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 530 { 531 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 532 u32 addr = __mt7915_reg_addr(dev, offset); 533 534 return dev->bus_ops->rmw(mdev, addr, mask, val); 535 } 536 537 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 538 static int mt7915_mmio_wed_offload_enable(struct mtk_wed_device *wed) 539 { 540 struct mt7915_dev *dev; 541 struct mt7915_phy *phy; 542 int ret; 543 544 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 545 546 spin_lock_bh(&dev->mt76.token_lock); 547 dev->mt76.token_size = wed->wlan.token_start; 548 spin_unlock_bh(&dev->mt76.token_lock); 549 550 ret = wait_event_timeout(dev->mt76.tx_wait, 551 !dev->mt76.wed_token_count, HZ); 552 if (!ret) 553 return -EAGAIN; 554 555 phy = &dev->phy; 556 mt76_set(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H); 557 558 phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 559 if (phy) 560 mt76_set(dev, MT_AGG_ACR4(phy->band_idx), 561 MT_AGG_ACR_PPDU_TXS2H); 562 563 return 0; 564 } 565 566 static void mt7915_mmio_wed_offload_disable(struct mtk_wed_device *wed) 567 { 568 struct mt7915_dev *dev; 569 struct mt7915_phy *phy; 570 571 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 572 573 spin_lock_bh(&dev->mt76.token_lock); 574 dev->mt76.token_size = MT7915_TOKEN_SIZE; 575 spin_unlock_bh(&dev->mt76.token_lock); 576 577 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 578 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 579 */ 580 phy = &dev->phy; 581 mt76_clear(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H); 582 583 phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 584 if (phy) 585 mt76_clear(dev, MT_AGG_ACR4(phy->band_idx), 586 MT_AGG_ACR_PPDU_TXS2H); 587 } 588 #endif 589 590 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 591 bool pci, int *irq) 592 { 593 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 594 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 595 int ret; 596 597 if (!wed_enable) 598 return 0; 599 600 if (pci) { 601 struct pci_dev *pci_dev = pdev_ptr; 602 603 wed->wlan.pci_dev = pci_dev; 604 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 605 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) + 606 MT_INT_WED_SOURCE_CSR; 607 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) + 608 MT_INT_WED_MASK_CSR; 609 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) + 610 MT_WFDMA_EXT_CSR_BASE; 611 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) + 612 MT_TXQ_WED_RING_BASE; 613 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) + 614 MT_RXQ_WED_RING_BASE; 615 } else { 616 struct platform_device *plat_dev = pdev_ptr; 617 struct resource *res; 618 619 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 620 if (!res) 621 return -ENOMEM; 622 623 wed->wlan.platform_dev = plat_dev; 624 wed->wlan.bus_type = MTK_WED_BUS_AXI; 625 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR; 626 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR; 627 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE; 628 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE; 629 } 630 wed->wlan.nbuf = 4096; 631 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30; 632 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31; 633 wed->wlan.txfree_tbit = is_mt7915(&dev->mt76) ? 1 : 2; 634 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; 635 wed->wlan.init_buf = mt7915_wed_init_buf; 636 wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable; 637 wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable; 638 639 if (mtk_wed_device_attach(wed)) 640 return 0; 641 642 *irq = wed->irq; 643 dev->mt76.dma_dev = wed->dev; 644 645 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); 646 if (ret) 647 return ret; 648 649 return 1; 650 #else 651 return 0; 652 #endif 653 } 654 655 static int mt7915_mmio_init(struct mt76_dev *mdev, 656 void __iomem *mem_base, 657 u32 device_id) 658 { 659 struct mt76_bus_ops *bus_ops; 660 struct mt7915_dev *dev; 661 662 dev = container_of(mdev, struct mt7915_dev, mt76); 663 mt76_mmio_init(&dev->mt76, mem_base); 664 665 switch (device_id) { 666 case 0x7915: 667 dev->reg.reg_rev = mt7915_reg; 668 dev->reg.offs_rev = mt7915_offs; 669 dev->reg.map = mt7915_reg_map; 670 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map); 671 break; 672 case 0x7906: 673 dev->reg.reg_rev = mt7916_reg; 674 dev->reg.offs_rev = mt7916_offs; 675 dev->reg.map = mt7916_reg_map; 676 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map); 677 break; 678 case 0x7986: 679 dev->reg.reg_rev = mt7986_reg; 680 dev->reg.offs_rev = mt7916_offs; 681 dev->reg.map = mt7986_reg_map; 682 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map); 683 break; 684 default: 685 return -EINVAL; 686 } 687 688 dev->bus_ops = dev->mt76.bus; 689 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 690 GFP_KERNEL); 691 if (!bus_ops) 692 return -ENOMEM; 693 694 bus_ops->rr = mt7915_rr; 695 bus_ops->wr = mt7915_wr; 696 bus_ops->rmw = mt7915_rmw; 697 dev->mt76.bus = bus_ops; 698 699 mdev->rev = (device_id << 16) | 700 (mt76_rr(dev, MT_HW_REV) & 0xff); 701 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 702 703 return 0; 704 } 705 706 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, 707 bool write_reg, 708 u32 clear, u32 set) 709 { 710 struct mt76_dev *mdev = &dev->mt76; 711 unsigned long flags; 712 713 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 714 715 mdev->mmio.irqmask &= ~clear; 716 mdev->mmio.irqmask |= set; 717 718 if (write_reg) { 719 if (mtk_wed_device_active(&mdev->mmio.wed)) 720 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 721 mdev->mmio.irqmask); 722 else 723 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 724 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 725 } 726 727 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 728 } 729 730 static void mt7915_rx_poll_complete(struct mt76_dev *mdev, 731 enum mt76_rxq_id q) 732 { 733 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 734 735 mt7915_irq_enable(dev, MT_INT_RX(q)); 736 } 737 738 /* TODO: support 2/4/6/8 MSI-X vectors */ 739 static void mt7915_irq_tasklet(struct tasklet_struct *t) 740 { 741 struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet); 742 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 743 u32 intr, intr1, mask; 744 745 if (mtk_wed_device_active(wed)) { 746 mtk_wed_device_irq_set_mask(wed, 0); 747 if (dev->hif2) 748 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 749 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 750 } else { 751 mt76_wr(dev, MT_INT_MASK_CSR, 0); 752 if (dev->hif2) 753 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 754 755 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 756 intr &= dev->mt76.mmio.irqmask; 757 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 758 } 759 760 if (dev->hif2) { 761 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 762 intr1 &= dev->mt76.mmio.irqmask; 763 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 764 765 intr |= intr1; 766 } 767 768 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 769 770 mask = intr & MT_INT_RX_DONE_ALL; 771 if (intr & MT_INT_TX_DONE_MCU) 772 mask |= MT_INT_TX_DONE_MCU; 773 774 mt7915_irq_disable(dev, mask); 775 776 if (intr & MT_INT_TX_DONE_MCU) 777 napi_schedule(&dev->mt76.tx_napi); 778 779 if (intr & MT_INT_RX(MT_RXQ_MAIN)) 780 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 781 782 if (intr & MT_INT_RX(MT_RXQ_BAND1)) 783 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); 784 785 if (intr & MT_INT_RX(MT_RXQ_MCU)) 786 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 787 788 if (intr & MT_INT_RX(MT_RXQ_MCU_WA)) 789 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 790 791 if (!is_mt7915(&dev->mt76) && 792 (intr & MT_INT_RX(MT_RXQ_MAIN_WA))) 793 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); 794 795 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA)) 796 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 797 798 if (intr & MT_INT_MCU_CMD) { 799 u32 val = mt76_rr(dev, MT_MCU_CMD); 800 801 mt76_wr(dev, MT_MCU_CMD, val); 802 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 803 dev->recovery.state = val; 804 mt7915_reset(dev); 805 } 806 } 807 } 808 809 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) 810 { 811 struct mt7915_dev *dev = dev_instance; 812 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 813 814 if (mtk_wed_device_active(wed)) { 815 mtk_wed_device_irq_set_mask(wed, 0); 816 } else { 817 mt76_wr(dev, MT_INT_MASK_CSR, 0); 818 if (dev->hif2) 819 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 820 } 821 822 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 823 return IRQ_NONE; 824 825 tasklet_schedule(&dev->irq_tasklet); 826 827 return IRQ_HANDLED; 828 } 829 830 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 831 void __iomem *mem_base, u32 device_id) 832 { 833 static const struct mt76_driver_ops drv_ops = { 834 /* txwi_size = txd size + txp size */ 835 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 836 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 837 MT_DRV_AMSDU_OFFLOAD, 838 .survey_flags = SURVEY_INFO_TIME_TX | 839 SURVEY_INFO_TIME_RX | 840 SURVEY_INFO_TIME_BSS_RX, 841 .token_size = MT7915_TOKEN_SIZE, 842 .tx_prepare_skb = mt7915_tx_prepare_skb, 843 .tx_complete_skb = mt76_connac_tx_complete_skb, 844 .rx_skb = mt7915_queue_rx_skb, 845 .rx_check = mt7915_rx_check, 846 .rx_poll_complete = mt7915_rx_poll_complete, 847 .sta_ps = mt7915_sta_ps, 848 .sta_add = mt7915_mac_sta_add, 849 .sta_remove = mt7915_mac_sta_remove, 850 .update_survey = mt7915_update_channel, 851 }; 852 struct mt7915_dev *dev; 853 struct mt76_dev *mdev; 854 int ret; 855 856 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops); 857 if (!mdev) 858 return ERR_PTR(-ENOMEM); 859 860 dev = container_of(mdev, struct mt7915_dev, mt76); 861 862 ret = mt7915_mmio_init(mdev, mem_base, device_id); 863 if (ret) 864 goto error; 865 866 tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet); 867 868 return dev; 869 870 error: 871 mt76_free_device(&dev->mt76); 872 873 return ERR_PTR(ret); 874 } 875 876 static int __init mt7915_init(void) 877 { 878 int ret; 879 880 ret = pci_register_driver(&mt7915_hif_driver); 881 if (ret) 882 return ret; 883 884 ret = pci_register_driver(&mt7915_pci_driver); 885 if (ret) 886 goto error_pci; 887 888 if (IS_ENABLED(CONFIG_MT7986_WMAC)) { 889 ret = platform_driver_register(&mt7986_wmac_driver); 890 if (ret) 891 goto error_wmac; 892 } 893 894 return 0; 895 896 error_wmac: 897 pci_unregister_driver(&mt7915_pci_driver); 898 error_pci: 899 pci_unregister_driver(&mt7915_hif_driver); 900 901 return ret; 902 } 903 904 static void __exit mt7915_exit(void) 905 { 906 if (IS_ENABLED(CONFIG_MT7986_WMAC)) 907 platform_driver_unregister(&mt7986_wmac_driver); 908 909 pci_unregister_driver(&mt7915_pci_driver); 910 pci_unregister_driver(&mt7915_hif_driver); 911 } 912 913 module_init(mt7915_init); 914 module_exit(mt7915_exit); 915 MODULE_LICENSE("Dual BSD/GPL"); 916