1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pci.h> 8 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "../trace.h" 12 13 static bool wed_enable; 14 module_param(wed_enable, bool, 0644); 15 16 static const u32 mt7915_reg[] = { 17 [INT_SOURCE_CSR] = 0xd7010, 18 [INT_MASK_CSR] = 0xd7014, 19 [INT1_SOURCE_CSR] = 0xd7088, 20 [INT1_MASK_CSR] = 0xd708c, 21 [INT_MCU_CMD_SOURCE] = 0xd51f0, 22 [INT_MCU_CMD_EVENT] = 0x3108, 23 [WFDMA0_ADDR] = 0xd4000, 24 [WFDMA0_PCIE1_ADDR] = 0xd8000, 25 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 26 [CBTOP1_PHY_END] = 0x77ffffff, 27 [INFRA_MCU_ADDR_END] = 0x7c3fffff, 28 [FW_EXCEPTION_ADDR] = 0x219848, 29 [SWDEF_BASE_ADDR] = 0x41f200, 30 [TXQ_WED_RING_BASE] = 0xd7300, 31 [RXQ_WED_RING_BASE] = 0xd7410, 32 }; 33 34 static const u32 mt7916_reg[] = { 35 [INT_SOURCE_CSR] = 0xd4200, 36 [INT_MASK_CSR] = 0xd4204, 37 [INT1_SOURCE_CSR] = 0xd8200, 38 [INT1_MASK_CSR] = 0xd8204, 39 [INT_MCU_CMD_SOURCE] = 0xd41f0, 40 [INT_MCU_CMD_EVENT] = 0x2108, 41 [WFDMA0_ADDR] = 0xd4000, 42 [WFDMA0_PCIE1_ADDR] = 0xd8000, 43 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 44 [CBTOP1_PHY_END] = 0x7fffffff, 45 [INFRA_MCU_ADDR_END] = 0x7c085fff, 46 [FW_EXCEPTION_ADDR] = 0x022050bc, 47 [SWDEF_BASE_ADDR] = 0x411400, 48 [TXQ_WED_RING_BASE] = 0xd7300, 49 [RXQ_WED_RING_BASE] = 0xd7410, 50 }; 51 52 static const u32 mt7986_reg[] = { 53 [INT_SOURCE_CSR] = 0x24200, 54 [INT_MASK_CSR] = 0x24204, 55 [INT1_SOURCE_CSR] = 0x28200, 56 [INT1_MASK_CSR] = 0x28204, 57 [INT_MCU_CMD_SOURCE] = 0x241f0, 58 [INT_MCU_CMD_EVENT] = 0x54000108, 59 [WFDMA0_ADDR] = 0x24000, 60 [WFDMA0_PCIE1_ADDR] = 0x28000, 61 [WFDMA_EXT_CSR_ADDR] = 0x27000, 62 [CBTOP1_PHY_END] = 0x7fffffff, 63 [INFRA_MCU_ADDR_END] = 0x7c085fff, 64 [FW_EXCEPTION_ADDR] = 0x02204ffc, 65 [SWDEF_BASE_ADDR] = 0x411400, 66 [TXQ_WED_RING_BASE] = 0x24420, 67 [RXQ_WED_RING_BASE] = 0x24520, 68 }; 69 70 static const u32 mt7915_offs[] = { 71 [TMAC_CDTR] = 0x090, 72 [TMAC_ODTR] = 0x094, 73 [TMAC_ATCR] = 0x098, 74 [TMAC_TRCR0] = 0x09c, 75 [TMAC_ICR0] = 0x0a4, 76 [TMAC_ICR1] = 0x0b4, 77 [TMAC_CTCR0] = 0x0f4, 78 [TMAC_TFCR0] = 0x1e0, 79 [MDP_BNRCFR0] = 0x070, 80 [MDP_BNRCFR1] = 0x074, 81 [ARB_DRNGR0] = 0x194, 82 [ARB_SCR] = 0x080, 83 [RMAC_MIB_AIRTIME14] = 0x3b8, 84 [AGG_AWSCR0] = 0x05c, 85 [AGG_PCR0] = 0x06c, 86 [AGG_ACR0] = 0x084, 87 [AGG_ACR4] = 0x08c, 88 [AGG_MRCR] = 0x098, 89 [AGG_ATCR1] = 0x0f0, 90 [AGG_ATCR3] = 0x0f4, 91 [LPON_UTTR0] = 0x080, 92 [LPON_UTTR1] = 0x084, 93 [LPON_FRCR] = 0x314, 94 [MIB_SDR3] = 0x014, 95 [MIB_SDR4] = 0x018, 96 [MIB_SDR5] = 0x01c, 97 [MIB_SDR7] = 0x024, 98 [MIB_SDR8] = 0x028, 99 [MIB_SDR9] = 0x02c, 100 [MIB_SDR10] = 0x030, 101 [MIB_SDR11] = 0x034, 102 [MIB_SDR12] = 0x038, 103 [MIB_SDR13] = 0x03c, 104 [MIB_SDR14] = 0x040, 105 [MIB_SDR15] = 0x044, 106 [MIB_SDR16] = 0x048, 107 [MIB_SDR17] = 0x04c, 108 [MIB_SDR18] = 0x050, 109 [MIB_SDR19] = 0x054, 110 [MIB_SDR20] = 0x058, 111 [MIB_SDR21] = 0x05c, 112 [MIB_SDR22] = 0x060, 113 [MIB_SDR23] = 0x064, 114 [MIB_SDR24] = 0x068, 115 [MIB_SDR25] = 0x06c, 116 [MIB_SDR27] = 0x074, 117 [MIB_SDR28] = 0x078, 118 [MIB_SDR29] = 0x07c, 119 [MIB_SDRVEC] = 0x080, 120 [MIB_SDR31] = 0x084, 121 [MIB_SDR32] = 0x088, 122 [MIB_SDRMUBF] = 0x090, 123 [MIB_DR8] = 0x0c0, 124 [MIB_DR9] = 0x0c4, 125 [MIB_DR11] = 0x0cc, 126 [MIB_MB_SDR0] = 0x100, 127 [MIB_MB_SDR1] = 0x104, 128 [TX_AGG_CNT] = 0x0a8, 129 [TX_AGG_CNT2] = 0x164, 130 [MIB_ARNG] = 0x4b8, 131 [WTBLON_TOP_WDUCR] = 0x0, 132 [WTBL_UPDATE] = 0x030, 133 [PLE_FL_Q_EMPTY] = 0x0b0, 134 [PLE_FL_Q_CTRL] = 0x1b0, 135 [PLE_AC_QEMPTY] = 0x500, 136 [PLE_FREEPG_CNT] = 0x100, 137 [PLE_FREEPG_HEAD_TAIL] = 0x104, 138 [PLE_PG_HIF_GROUP] = 0x110, 139 [PLE_HIF_PG_INFO] = 0x114, 140 [AC_OFFSET] = 0x040, 141 [ETBF_PAR_RPT0] = 0x068, 142 }; 143 144 static const u32 mt7916_offs[] = { 145 [TMAC_CDTR] = 0x0c8, 146 [TMAC_ODTR] = 0x0cc, 147 [TMAC_ATCR] = 0x00c, 148 [TMAC_TRCR0] = 0x010, 149 [TMAC_ICR0] = 0x014, 150 [TMAC_ICR1] = 0x018, 151 [TMAC_CTCR0] = 0x114, 152 [TMAC_TFCR0] = 0x0e4, 153 [MDP_BNRCFR0] = 0x090, 154 [MDP_BNRCFR1] = 0x094, 155 [ARB_DRNGR0] = 0x1e0, 156 [ARB_SCR] = 0x000, 157 [RMAC_MIB_AIRTIME14] = 0x0398, 158 [AGG_AWSCR0] = 0x030, 159 [AGG_PCR0] = 0x040, 160 [AGG_ACR0] = 0x054, 161 [AGG_ACR4] = 0x05c, 162 [AGG_MRCR] = 0x068, 163 [AGG_ATCR1] = 0x1a8, 164 [AGG_ATCR3] = 0x080, 165 [LPON_UTTR0] = 0x360, 166 [LPON_UTTR1] = 0x364, 167 [LPON_FRCR] = 0x37c, 168 [MIB_SDR3] = 0x698, 169 [MIB_SDR4] = 0x788, 170 [MIB_SDR5] = 0x780, 171 [MIB_SDR7] = 0x5a8, 172 [MIB_SDR8] = 0x78c, 173 [MIB_SDR9] = 0x024, 174 [MIB_SDR10] = 0x76c, 175 [MIB_SDR11] = 0x790, 176 [MIB_SDR12] = 0x558, 177 [MIB_SDR13] = 0x560, 178 [MIB_SDR14] = 0x564, 179 [MIB_SDR15] = 0x568, 180 [MIB_SDR16] = 0x7fc, 181 [MIB_SDR17] = 0x800, 182 [MIB_SDR18] = 0x030, 183 [MIB_SDR19] = 0x5ac, 184 [MIB_SDR20] = 0x5b0, 185 [MIB_SDR21] = 0x5b4, 186 [MIB_SDR22] = 0x770, 187 [MIB_SDR23] = 0x774, 188 [MIB_SDR24] = 0x778, 189 [MIB_SDR25] = 0x77c, 190 [MIB_SDR27] = 0x080, 191 [MIB_SDR28] = 0x084, 192 [MIB_SDR29] = 0x650, 193 [MIB_SDRVEC] = 0x5a8, 194 [MIB_SDR31] = 0x55c, 195 [MIB_SDR32] = 0x7a8, 196 [MIB_SDRMUBF] = 0x7ac, 197 [MIB_DR8] = 0x56c, 198 [MIB_DR9] = 0x570, 199 [MIB_DR11] = 0x574, 200 [MIB_MB_SDR0] = 0x688, 201 [MIB_MB_SDR1] = 0x690, 202 [TX_AGG_CNT] = 0x7dc, 203 [TX_AGG_CNT2] = 0x7ec, 204 [MIB_ARNG] = 0x0b0, 205 [WTBLON_TOP_WDUCR] = 0x200, 206 [WTBL_UPDATE] = 0x230, 207 [PLE_FL_Q_EMPTY] = 0x360, 208 [PLE_FL_Q_CTRL] = 0x3e0, 209 [PLE_AC_QEMPTY] = 0x600, 210 [PLE_FREEPG_CNT] = 0x380, 211 [PLE_FREEPG_HEAD_TAIL] = 0x384, 212 [PLE_PG_HIF_GROUP] = 0x00c, 213 [PLE_HIF_PG_INFO] = 0x388, 214 [AC_OFFSET] = 0x080, 215 [ETBF_PAR_RPT0] = 0x100, 216 }; 217 218 static const struct mt76_connac_reg_map mt7915_reg_map[] = { 219 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 220 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */ 221 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 222 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 223 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 224 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 225 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 226 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 227 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 228 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 229 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 230 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 231 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 232 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 233 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 234 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 235 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 236 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 237 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 238 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 239 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 240 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 241 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 242 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 243 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 244 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 245 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 246 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 247 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 248 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 249 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 250 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 251 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 252 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 253 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 254 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 255 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 256 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 257 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 258 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 259 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 260 { 0x0, 0x0, 0x0 }, /* imply end of search */ 261 }; 262 263 static const struct mt76_connac_reg_map mt7916_reg_map[] = { 264 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 265 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 266 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */ 267 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 268 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 269 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 270 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 271 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 272 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 273 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 274 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 275 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 276 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 277 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 278 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 279 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 280 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 281 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 282 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 283 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 284 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 285 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 286 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 287 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 288 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 289 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 290 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */ 291 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 292 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 293 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 294 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 295 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 296 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 297 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 298 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 299 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 300 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 301 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 302 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 303 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 304 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */ 305 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 306 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 307 { 0x0, 0x0, 0x0 }, /* imply end of search */ 308 }; 309 310 static const struct mt76_connac_reg_map mt7986_reg_map[] = { 311 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 312 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 313 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */ 314 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 315 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 316 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 317 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 318 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 319 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 320 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 321 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 322 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 323 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 324 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 325 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 326 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 327 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 328 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 329 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 330 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 331 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 332 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 333 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 334 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 335 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 336 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */ 337 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */ 338 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 339 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 340 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 341 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 342 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 343 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 344 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 345 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 346 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 347 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 348 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 349 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 350 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 351 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */ 352 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 353 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */ 354 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */ 355 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */ 356 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */ 357 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */ 358 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */ 359 { 0x0, 0x0, 0x0 }, /* imply end of search */ 360 }; 361 362 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 363 { 364 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 365 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 366 u32 l1_remap; 367 368 if (is_mt7986(&dev->mt76)) 369 return MT_CONN_INFRA_OFFSET(addr); 370 371 l1_remap = is_mt7915(&dev->mt76) ? 372 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916; 373 374 dev->bus_ops->rmw(&dev->mt76, l1_remap, 375 MT_HIF_REMAP_L1_MASK, 376 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 377 /* use read to push write */ 378 dev->bus_ops->rr(&dev->mt76, l1_remap); 379 380 return MT_HIF_REMAP_BASE_L1 + offset; 381 } 382 383 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 384 { 385 u32 offset, base; 386 387 if (is_mt7915(&dev->mt76)) { 388 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 389 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 390 391 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 392 MT_HIF_REMAP_L2_MASK, 393 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 394 395 /* use read to push write */ 396 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 397 } else { 398 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0; 399 400 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr); 401 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr); 402 403 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs, 404 MT_HIF_REMAP_L2_MASK_MT7916, 405 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base)); 406 407 /* use read to push write */ 408 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs); 409 410 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs); 411 } 412 413 return offset; 414 } 415 416 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 417 { 418 int i; 419 420 if (addr < 0x100000) 421 return addr; 422 423 if (!dev->reg.map) { 424 dev_err(dev->mt76.dev, "err: reg_map is null\n"); 425 return addr; 426 } 427 428 for (i = 0; i < dev->reg.map_size; i++) { 429 u32 ofs; 430 431 if (addr < dev->reg.map[i].phys) 432 continue; 433 434 ofs = addr - dev->reg.map[i].phys; 435 if (ofs > dev->reg.map[i].size) 436 continue; 437 438 return dev->reg.map[i].maps + ofs; 439 } 440 441 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 442 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 443 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 444 return mt7915_reg_map_l1(dev, addr); 445 446 if (dev_is_pci(dev->mt76.dev) && 447 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 448 (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) 449 return mt7915_reg_map_l1(dev, addr); 450 451 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 452 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 453 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 454 return mt7915_reg_map_l1(dev, addr); 455 } 456 457 return mt7915_reg_map_l2(dev, addr); 458 } 459 460 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 461 { 462 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 463 u32 addr = __mt7915_reg_addr(dev, offset); 464 465 return dev->bus_ops->rr(mdev, addr); 466 } 467 468 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 469 { 470 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 471 u32 addr = __mt7915_reg_addr(dev, offset); 472 473 dev->bus_ops->wr(mdev, addr, val); 474 } 475 476 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 477 { 478 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 479 u32 addr = __mt7915_reg_addr(dev, offset); 480 481 return dev->bus_ops->rmw(mdev, addr, mask, val); 482 } 483 484 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 485 static int mt7915_mmio_wed_offload_enable(struct mtk_wed_device *wed) 486 { 487 struct mt7915_dev *dev; 488 struct mt7915_phy *phy; 489 int ret; 490 491 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 492 493 spin_lock_bh(&dev->mt76.token_lock); 494 dev->mt76.token_size = wed->wlan.token_start; 495 spin_unlock_bh(&dev->mt76.token_lock); 496 497 ret = wait_event_timeout(dev->mt76.tx_wait, 498 !dev->mt76.wed_token_count, HZ); 499 if (!ret) 500 return -EAGAIN; 501 502 phy = &dev->phy; 503 mt76_set(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H); 504 505 phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 506 if (phy) 507 mt76_set(dev, MT_AGG_ACR4(phy->band_idx), 508 MT_AGG_ACR_PPDU_TXS2H); 509 510 return 0; 511 } 512 513 static void mt7915_mmio_wed_offload_disable(struct mtk_wed_device *wed) 514 { 515 struct mt7915_dev *dev; 516 struct mt7915_phy *phy; 517 518 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 519 520 spin_lock_bh(&dev->mt76.token_lock); 521 dev->mt76.token_size = MT7915_TOKEN_SIZE; 522 spin_unlock_bh(&dev->mt76.token_lock); 523 524 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 525 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 526 */ 527 phy = &dev->phy; 528 mt76_clear(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H); 529 530 phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 531 if (phy) 532 mt76_clear(dev, MT_AGG_ACR4(phy->band_idx), 533 MT_AGG_ACR_PPDU_TXS2H); 534 } 535 #endif 536 537 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 538 bool pci, int *irq) 539 { 540 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 541 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 542 int ret; 543 544 if (!wed_enable) 545 return 0; 546 547 if (pci) { 548 struct pci_dev *pci_dev = pdev_ptr; 549 550 wed->wlan.pci_dev = pci_dev; 551 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 552 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) + 553 MT_INT_WED_SOURCE_CSR; 554 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) + 555 MT_INT_WED_MASK_CSR; 556 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) + 557 MT_WFDMA_EXT_CSR_BASE; 558 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) + 559 MT_TXQ_WED_RING_BASE; 560 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) + 561 MT_RXQ_WED_RING_BASE; 562 } else { 563 struct platform_device *plat_dev = pdev_ptr; 564 struct resource *res; 565 566 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 567 if (!res) 568 return -ENOMEM; 569 570 wed->wlan.platform_dev = plat_dev; 571 wed->wlan.bus_type = MTK_WED_BUS_AXI; 572 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR; 573 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR; 574 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE; 575 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE; 576 } 577 wed->wlan.nbuf = 4096; 578 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30; 579 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31; 580 wed->wlan.txfree_tbit = is_mt7915(&dev->mt76) ? 1 : 2; 581 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; 582 wed->wlan.init_buf = mt7915_wed_init_buf; 583 wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable; 584 wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable; 585 586 if (mtk_wed_device_attach(wed)) 587 return 0; 588 589 *irq = wed->irq; 590 dev->mt76.dma_dev = wed->dev; 591 592 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); 593 if (ret) 594 return ret; 595 596 return 1; 597 #else 598 return 0; 599 #endif 600 } 601 602 static int mt7915_mmio_init(struct mt76_dev *mdev, 603 void __iomem *mem_base, 604 u32 device_id) 605 { 606 struct mt76_bus_ops *bus_ops; 607 struct mt7915_dev *dev; 608 609 dev = container_of(mdev, struct mt7915_dev, mt76); 610 mt76_mmio_init(&dev->mt76, mem_base); 611 612 switch (device_id) { 613 case 0x7915: 614 dev->reg.reg_rev = mt7915_reg; 615 dev->reg.offs_rev = mt7915_offs; 616 dev->reg.map = mt7915_reg_map; 617 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map); 618 break; 619 case 0x7906: 620 dev->reg.reg_rev = mt7916_reg; 621 dev->reg.offs_rev = mt7916_offs; 622 dev->reg.map = mt7916_reg_map; 623 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map); 624 break; 625 case 0x7986: 626 dev->reg.reg_rev = mt7986_reg; 627 dev->reg.offs_rev = mt7916_offs; 628 dev->reg.map = mt7986_reg_map; 629 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map); 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 dev->bus_ops = dev->mt76.bus; 636 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 637 GFP_KERNEL); 638 if (!bus_ops) 639 return -ENOMEM; 640 641 bus_ops->rr = mt7915_rr; 642 bus_ops->wr = mt7915_wr; 643 bus_ops->rmw = mt7915_rmw; 644 dev->mt76.bus = bus_ops; 645 646 mdev->rev = (device_id << 16) | 647 (mt76_rr(dev, MT_HW_REV) & 0xff); 648 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 649 650 return 0; 651 } 652 653 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, 654 bool write_reg, 655 u32 clear, u32 set) 656 { 657 struct mt76_dev *mdev = &dev->mt76; 658 unsigned long flags; 659 660 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 661 662 mdev->mmio.irqmask &= ~clear; 663 mdev->mmio.irqmask |= set; 664 665 if (write_reg) { 666 if (mtk_wed_device_active(&mdev->mmio.wed)) 667 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 668 mdev->mmio.irqmask); 669 else 670 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 671 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 672 } 673 674 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 675 } 676 677 static void mt7915_rx_poll_complete(struct mt76_dev *mdev, 678 enum mt76_rxq_id q) 679 { 680 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 681 682 mt7915_irq_enable(dev, MT_INT_RX(q)); 683 } 684 685 /* TODO: support 2/4/6/8 MSI-X vectors */ 686 static void mt7915_irq_tasklet(struct tasklet_struct *t) 687 { 688 struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet); 689 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 690 u32 intr, intr1, mask; 691 692 if (mtk_wed_device_active(wed)) { 693 mtk_wed_device_irq_set_mask(wed, 0); 694 if (dev->hif2) 695 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 696 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 697 } else { 698 mt76_wr(dev, MT_INT_MASK_CSR, 0); 699 if (dev->hif2) 700 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 701 702 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 703 intr &= dev->mt76.mmio.irqmask; 704 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 705 } 706 707 if (dev->hif2) { 708 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 709 intr1 &= dev->mt76.mmio.irqmask; 710 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 711 712 intr |= intr1; 713 } 714 715 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 716 717 mask = intr & MT_INT_RX_DONE_ALL; 718 if (intr & MT_INT_TX_DONE_MCU) 719 mask |= MT_INT_TX_DONE_MCU; 720 721 mt7915_irq_disable(dev, mask); 722 723 if (intr & MT_INT_TX_DONE_MCU) 724 napi_schedule(&dev->mt76.tx_napi); 725 726 if (intr & MT_INT_RX(MT_RXQ_MAIN)) 727 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 728 729 if (intr & MT_INT_RX(MT_RXQ_BAND1)) 730 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); 731 732 if (intr & MT_INT_RX(MT_RXQ_MCU)) 733 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 734 735 if (intr & MT_INT_RX(MT_RXQ_MCU_WA)) 736 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 737 738 if (!is_mt7915(&dev->mt76) && 739 (intr & MT_INT_RX(MT_RXQ_MAIN_WA))) 740 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); 741 742 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA)) 743 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 744 745 if (intr & MT_INT_MCU_CMD) { 746 u32 val = mt76_rr(dev, MT_MCU_CMD); 747 748 mt76_wr(dev, MT_MCU_CMD, val); 749 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 750 dev->recovery.state = val; 751 mt7915_reset(dev); 752 } 753 } 754 } 755 756 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) 757 { 758 struct mt7915_dev *dev = dev_instance; 759 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 760 761 if (mtk_wed_device_active(wed)) { 762 mtk_wed_device_irq_set_mask(wed, 0); 763 } else { 764 mt76_wr(dev, MT_INT_MASK_CSR, 0); 765 if (dev->hif2) 766 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 767 } 768 769 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 770 return IRQ_NONE; 771 772 tasklet_schedule(&dev->irq_tasklet); 773 774 return IRQ_HANDLED; 775 } 776 777 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 778 void __iomem *mem_base, u32 device_id) 779 { 780 static const struct mt76_driver_ops drv_ops = { 781 /* txwi_size = txd size + txp size */ 782 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 783 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 784 MT_DRV_AMSDU_OFFLOAD, 785 .survey_flags = SURVEY_INFO_TIME_TX | 786 SURVEY_INFO_TIME_RX | 787 SURVEY_INFO_TIME_BSS_RX, 788 .token_size = MT7915_TOKEN_SIZE, 789 .tx_prepare_skb = mt7915_tx_prepare_skb, 790 .tx_complete_skb = mt76_connac_tx_complete_skb, 791 .rx_skb = mt7915_queue_rx_skb, 792 .rx_check = mt7915_rx_check, 793 .rx_poll_complete = mt7915_rx_poll_complete, 794 .sta_ps = mt7915_sta_ps, 795 .sta_add = mt7915_mac_sta_add, 796 .sta_remove = mt7915_mac_sta_remove, 797 .update_survey = mt7915_update_channel, 798 }; 799 struct mt7915_dev *dev; 800 struct mt76_dev *mdev; 801 int ret; 802 803 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops); 804 if (!mdev) 805 return ERR_PTR(-ENOMEM); 806 807 dev = container_of(mdev, struct mt7915_dev, mt76); 808 809 ret = mt7915_mmio_init(mdev, mem_base, device_id); 810 if (ret) 811 goto error; 812 813 tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet); 814 815 return dev; 816 817 error: 818 mt76_free_device(&dev->mt76); 819 820 return ERR_PTR(ret); 821 } 822 823 static int __init mt7915_init(void) 824 { 825 int ret; 826 827 ret = pci_register_driver(&mt7915_hif_driver); 828 if (ret) 829 return ret; 830 831 ret = pci_register_driver(&mt7915_pci_driver); 832 if (ret) 833 goto error_pci; 834 835 if (IS_ENABLED(CONFIG_MT7986_WMAC)) { 836 ret = platform_driver_register(&mt7986_wmac_driver); 837 if (ret) 838 goto error_wmac; 839 } 840 841 return 0; 842 843 error_wmac: 844 pci_unregister_driver(&mt7915_pci_driver); 845 error_pci: 846 pci_unregister_driver(&mt7915_hif_driver); 847 848 return ret; 849 } 850 851 static void __exit mt7915_exit(void) 852 { 853 if (IS_ENABLED(CONFIG_MT7986_WMAC)) 854 platform_driver_unregister(&mt7986_wmac_driver); 855 856 pci_unregister_driver(&mt7915_pci_driver); 857 pci_unregister_driver(&mt7915_hif_driver); 858 } 859 860 module_init(mt7915_init); 861 module_exit(mt7915_exit); 862 MODULE_LICENSE("Dual BSD/GPL"); 863