r9a07g043.dtsi (bc9e1dbb175706242a7160675b4f52d0380ae4ea) r9a07g043.dtsi (559f2b0708c70c49ae3143d481ee10351089e590)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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70 soc: soc {
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 ssi0: ssi@10049c00 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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70 soc: soc {
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 ssi0: ssi@10049c00 {
78 compatible = "renesas,r9a07g043-ssi",
79 "renesas,rz-ssi";
78 reg = <0 0x10049c00 0 0x400>;
80 reg = <0 0x10049c00 0 0x400>;
81 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
83 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
84 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
88 <&audio_clk1>, <&audio_clk2>;
89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
91 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
92 dma-names = "tx", "rx";
93 power-domains = <&cpg>;
79 #sound-dai-cells = <0>;
94 #sound-dai-cells = <0>;
80 /* place holder */
95 status = "disabled";
81 };
82
96 };
97
98 ssi1: ssi@1004a000 {
99 compatible = "renesas,r9a07g043-ssi",
100 "renesas,rz-ssi";
101 reg = <0 0x1004a000 0 0x400>;
102 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
104 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
105 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
109 <&audio_clk1>, <&audio_clk2>;
110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
112 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
113 dma-names = "tx", "rx";
114 power-domains = <&cpg>;
115 #sound-dai-cells = <0>;
116 status = "disabled";
117 };
118
119 ssi2: ssi@1004a400 {
120 compatible = "renesas,r9a07g043-ssi",
121 "renesas,rz-ssi";
122 reg = <0 0x1004a400 0 0x400>;
123 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
125 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
126 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
130 <&audio_clk1>, <&audio_clk2>;
131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
133 dmas = <&dmac 0x265f>;
134 dma-names = "rt";
135 power-domains = <&cpg>;
136 #sound-dai-cells = <0>;
137 status = "disabled";
138 };
139
140 ssi3: ssi@1004a800 {
141 compatible = "renesas,r9a07g043-ssi",
142 "renesas,rz-ssi";
143 reg = <0 0x1004a800 0 0x400>;
144 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
146 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
147 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
151 <&audio_clk1>, <&audio_clk2>;
152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
154 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
155 dma-names = "tx", "rx";
156 power-domains = <&cpg>;
157 #sound-dai-cells = <0>;
158 status = "disabled";
159 };
160
83 spi1: spi@1004b000 {
84 reg = <0 0x1004b000 0 0x400>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 /* place holder */
88 };
89
90 scif0: serial@1004b800 {

--- 458 unchanged lines hidden --- 		161 spi1: spi@1004b000 {
162 reg = <0 0x1004b000 0 0x400>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 /* place holder */
166 };
167
168 scif0: serial@1004b800 {

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