1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a55"; 51 reg = <0>; 52 device_type = "cpu"; 53 next-level-cache = <&L3_CA55>; 54 enable-method = "psci"; 55 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 56 }; 57 58 L3_CA55: cache-controller-0 { 59 compatible = "cache"; 60 cache-unified; 61 cache-size = <0x40000>; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0", "arm,psci-0.2"; 67 method = "smc"; 68 }; 69 70 soc: soc { 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 compatible = "renesas,r9a07g043-ssi", 79 "renesas,rz-ssi"; 80 reg = <0 0x10049c00 0 0x400>; 81 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 83 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 84 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 88 <&audio_clk1>, <&audio_clk2>; 89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 91 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 92 dma-names = "tx", "rx"; 93 power-domains = <&cpg>; 94 #sound-dai-cells = <0>; 95 status = "disabled"; 96 }; 97 98 ssi1: ssi@1004a000 { 99 compatible = "renesas,r9a07g043-ssi", 100 "renesas,rz-ssi"; 101 reg = <0 0x1004a000 0 0x400>; 102 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 104 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 105 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 109 <&audio_clk1>, <&audio_clk2>; 110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 112 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 113 dma-names = "tx", "rx"; 114 power-domains = <&cpg>; 115 #sound-dai-cells = <0>; 116 status = "disabled"; 117 }; 118 119 ssi2: ssi@1004a400 { 120 compatible = "renesas,r9a07g043-ssi", 121 "renesas,rz-ssi"; 122 reg = <0 0x1004a400 0 0x400>; 123 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 125 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 126 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 130 <&audio_clk1>, <&audio_clk2>; 131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 133 dmas = <&dmac 0x265f>; 134 dma-names = "rt"; 135 power-domains = <&cpg>; 136 #sound-dai-cells = <0>; 137 status = "disabled"; 138 }; 139 140 ssi3: ssi@1004a800 { 141 compatible = "renesas,r9a07g043-ssi", 142 "renesas,rz-ssi"; 143 reg = <0 0x1004a800 0 0x400>; 144 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 147 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 151 <&audio_clk1>, <&audio_clk2>; 152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 154 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 155 dma-names = "tx", "rx"; 156 power-domains = <&cpg>; 157 #sound-dai-cells = <0>; 158 status = "disabled"; 159 }; 160 161 spi1: spi@1004b000 { 162 reg = <0 0x1004b000 0 0x400>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 /* place holder */ 166 }; 167 168 scif0: serial@1004b800 { 169 compatible = "renesas,scif-r9a07g043", 170 "renesas,scif-r9a07g044"; 171 reg = <0 0x1004b800 0 0x400>; 172 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "eri", "rxi", "txi", 179 "bri", "dri", "tei"; 180 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 181 clock-names = "fck"; 182 power-domains = <&cpg>; 183 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 184 status = "disabled"; 185 }; 186 187 scif1: serial@1004bc00 { 188 compatible = "renesas,scif-r9a07g043", 189 "renesas,scif-r9a07g044"; 190 reg = <0 0x1004bc00 0 0x400>; 191 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 197 interrupt-names = "eri", "rxi", "txi", 198 "bri", "dri", "tei"; 199 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 200 clock-names = "fck"; 201 power-domains = <&cpg>; 202 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 203 status = "disabled"; 204 }; 205 206 scif2: serial@1004c000 { 207 compatible = "renesas,scif-r9a07g043", 208 "renesas,scif-r9a07g044"; 209 reg = <0 0x1004c000 0 0x400>; 210 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "eri", "rxi", "txi", 217 "bri", "dri", "tei"; 218 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 219 clock-names = "fck"; 220 power-domains = <&cpg>; 221 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 222 status = "disabled"; 223 }; 224 225 scif3: serial@1004c400 { 226 compatible = "renesas,scif-r9a07g043", 227 "renesas,scif-r9a07g044"; 228 reg = <0 0x1004c400 0 0x400>; 229 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "eri", "rxi", "txi", 236 "bri", "dri", "tei"; 237 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 238 clock-names = "fck"; 239 power-domains = <&cpg>; 240 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 241 status = "disabled"; 242 }; 243 244 scif4: serial@1004c800 { 245 compatible = "renesas,scif-r9a07g043", 246 "renesas,scif-r9a07g044"; 247 reg = <0 0x1004c800 0 0x400>; 248 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 254 interrupt-names = "eri", "rxi", "txi", 255 "bri", "dri", "tei"; 256 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 257 clock-names = "fck"; 258 power-domains = <&cpg>; 259 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 260 status = "disabled"; 261 }; 262 263 sci0: serial@1004d000 { 264 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 265 reg = <0 0x1004d000 0 0x400>; 266 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-names = "eri", "rxi", "txi", "tei"; 271 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 272 clock-names = "fck"; 273 power-domains = <&cpg>; 274 resets = <&cpg R9A07G043_SCI0_RST>; 275 status = "disabled"; 276 }; 277 278 sci1: serial@1004d400 { 279 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 280 reg = <0 0x1004d400 0 0x400>; 281 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "eri", "rxi", "txi", "tei"; 286 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 287 clock-names = "fck"; 288 power-domains = <&cpg>; 289 resets = <&cpg R9A07G043_SCI1_RST>; 290 status = "disabled"; 291 }; 292 293 canfd: can@10050000 { 294 reg = <0 0x10050000 0 0x8000>; 295 /* place holder */ 296 }; 297 298 i2c0: i2c@10058000 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 302 reg = <0 0x10058000 0 0x400>; 303 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 311 interrupt-names = "tei", "ri", "ti", "spi", "sti", 312 "naki", "ali", "tmoi"; 313 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 314 clock-frequency = <100000>; 315 resets = <&cpg R9A07G043_I2C0_MRST>; 316 power-domains = <&cpg>; 317 status = "disabled"; 318 }; 319 320 i2c1: i2c@10058400 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 324 reg = <0 0x10058400 0 0x400>; 325 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 333 interrupt-names = "tei", "ri", "ti", "spi", "sti", 334 "naki", "ali", "tmoi"; 335 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 336 clock-frequency = <100000>; 337 resets = <&cpg R9A07G043_I2C1_MRST>; 338 power-domains = <&cpg>; 339 status = "disabled"; 340 }; 341 342 i2c2: i2c@10058800 { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 346 reg = <0 0x10058800 0 0x400>; 347 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "tei", "ri", "ti", "spi", "sti", 356 "naki", "ali", "tmoi"; 357 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 358 clock-frequency = <100000>; 359 resets = <&cpg R9A07G043_I2C2_MRST>; 360 power-domains = <&cpg>; 361 status = "disabled"; 362 }; 363 364 i2c3: i2c@10058c00 { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 368 reg = <0 0x10058c00 0 0x400>; 369 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 371 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-names = "tei", "ri", "ti", "spi", "sti", 378 "naki", "ali", "tmoi"; 379 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 380 clock-frequency = <100000>; 381 resets = <&cpg R9A07G043_I2C3_MRST>; 382 power-domains = <&cpg>; 383 status = "disabled"; 384 }; 385 386 adc: adc@10059000 { 387 reg = <0 0x10059000 0 0x400>; 388 /* place holder */ 389 }; 390 391 sbc: spi@10060000 { 392 reg = <0 0x10060000 0 0x10000>, 393 <0 0x20000000 0 0x10000000>, 394 <0 0x10070000 0 0x10000>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 /* place holder */ 398 }; 399 400 cpg: clock-controller@11010000 { 401 compatible = "renesas,r9a07g043-cpg"; 402 reg = <0 0x11010000 0 0x10000>; 403 clocks = <&extal_clk>; 404 clock-names = "extal"; 405 #clock-cells = <2>; 406 #reset-cells = <1>; 407 #power-domain-cells = <0>; 408 }; 409 410 sysc: system-controller@11020000 { 411 compatible = "renesas,r9a07g043-sysc"; 412 reg = <0 0x11020000 0 0x10000>; 413 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "lpm_int", "ca55stbydone_int", 418 "cm33stbyr_int", "ca55_deny"; 419 status = "disabled"; 420 }; 421 422 pinctrl: pinctrl@11030000 { 423 compatible = "renesas,r9a07g043-pinctrl"; 424 reg = <0 0x11030000 0 0x10000>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 gpio-ranges = <&pinctrl 0 0 152>; 428 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 429 power-domains = <&cpg>; 430 resets = <&cpg R9A07G043_GPIO_RSTN>, 431 <&cpg R9A07G043_GPIO_PORT_RESETN>, 432 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 433 }; 434 435 dmac: dma-controller@11820000 { 436 compatible = "renesas,r9a07g043-dmac", 437 "renesas,rz-dmac"; 438 reg = <0 0x11820000 0 0x10000>, 439 <0 0x11830000 0 0x10000>; 440 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 457 interrupt-names = "error", 458 "ch0", "ch1", "ch2", "ch3", 459 "ch4", "ch5", "ch6", "ch7", 460 "ch8", "ch9", "ch10", "ch11", 461 "ch12", "ch13", "ch14", "ch15"; 462 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 463 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 464 power-domains = <&cpg>; 465 resets = <&cpg R9A07G043_DMAC_ARESETN>, 466 <&cpg R9A07G043_DMAC_RST_ASYNC>; 467 #dma-cells = <1>; 468 dma-channels = <16>; 469 }; 470 471 gic: interrupt-controller@11900000 { 472 compatible = "arm,gic-v3"; 473 #interrupt-cells = <3>; 474 #address-cells = <0>; 475 interrupt-controller; 476 reg = <0x0 0x11900000 0 0x40000>, 477 <0x0 0x11940000 0 0x60000>; 478 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 479 }; 480 481 sdhi0: mmc@11c00000 { 482 compatible = "renesas,sdhi-r9a07g043", 483 "renesas,rcar-gen3-sdhi"; 484 reg = <0x0 0x11c00000 0 0x10000>; 485 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 488 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 489 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 490 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 491 clock-names = "core", "clkh", "cd", "aclk"; 492 resets = <&cpg R9A07G043_SDHI0_IXRST>; 493 power-domains = <&cpg>; 494 status = "disabled"; 495 }; 496 497 sdhi1: mmc@11c10000 { 498 compatible = "renesas,sdhi-r9a07g043", 499 "renesas,rcar-gen3-sdhi"; 500 reg = <0x0 0x11c10000 0 0x10000>; 501 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 504 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 505 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 506 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 507 clock-names = "core", "clkh", "cd", "aclk"; 508 resets = <&cpg R9A07G043_SDHI1_IXRST>; 509 power-domains = <&cpg>; 510 status = "disabled"; 511 }; 512 513 eth0: ethernet@11c20000 { 514 compatible = "renesas,r9a07g043-gbeth", 515 "renesas,rzg2l-gbeth"; 516 reg = <0 0x11c20000 0 0x10000>; 517 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-names = "mux", "fil", "arp_ns"; 521 phy-mode = "rgmii"; 522 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 523 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 524 <&cpg CPG_CORE R9A07G043_CLK_HP>; 525 clock-names = "axi", "chi", "refclk"; 526 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 527 power-domains = <&cpg>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 eth1: ethernet@11c30000 { 534 compatible = "renesas,r9a07g043-gbeth", 535 "renesas,rzg2l-gbeth"; 536 reg = <0 0x11c30000 0 0x10000>; 537 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "mux", "fil", "arp_ns"; 541 phy-mode = "rgmii"; 542 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 543 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 544 <&cpg CPG_CORE R9A07G043_CLK_HP>; 545 clock-names = "axi", "chi", "refclk"; 546 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 547 power-domains = <&cpg>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 phyrst: usbphy-ctrl@11c40000 { 554 reg = <0 0x11c40000 0 0x10000>; 555 /* place holder */ 556 }; 557 558 ohci0: usb@11c50000 { 559 reg = <0 0x11c50000 0 0x100>; 560 /* place holder */ 561 }; 562 563 ohci1: usb@11c70000 { 564 reg = <0 0x11c70000 0 0x100>; 565 /* place holder */ 566 }; 567 568 ehci0: usb@11c50100 { 569 reg = <0 0x11c50100 0 0x100>; 570 /* place holder */ 571 }; 572 573 ehci1: usb@11c70100 { 574 reg = <0 0x11c70100 0 0x100>; 575 /* place holder */ 576 }; 577 578 usb2_phy0: usb-phy@11c50200 { 579 reg = <0 0x11c50200 0 0x700>; 580 /* place holder */ 581 }; 582 583 usb2_phy1: usb-phy@11c70200 { 584 reg = <0 0x11c70200 0 0x700>; 585 /* place holder */ 586 }; 587 588 hsusb: usb@11c60000 { 589 reg = <0 0x11c60000 0 0x10000>; 590 /* place holder */ 591 }; 592 593 wdt0: watchdog@12800800 { 594 reg = <0 0x12800800 0 0x400>; 595 /* place holder */ 596 }; 597 598 wdt2: watchdog@12800400 { 599 reg = <0 0x12800400 0 0x400>; 600 /* place holder */ 601 }; 602 603 ostm0: timer@12801000 { 604 reg = <0x0 0x12801000 0x0 0x400>; 605 /* place holder */ 606 }; 607 608 ostm1: timer@12801400 { 609 reg = <0x0 0x12801400 0x0 0x400>; 610 /* place holder */ 611 }; 612 613 ostm2: timer@12801800 { 614 reg = <0x0 0x12801800 0x0 0x400>; 615 /* place holder */ 616 }; 617 }; 618 619 timer { 620 compatible = "arm,armv8-timer"; 621 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 622 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 623 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 624 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 625 }; 626}; 627