1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a55"; 51 reg = <0>; 52 device_type = "cpu"; 53 next-level-cache = <&L3_CA55>; 54 enable-method = "psci"; 55 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 56 }; 57 58 L3_CA55: cache-controller-0 { 59 compatible = "cache"; 60 cache-unified; 61 cache-size = <0x40000>; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0", "arm,psci-0.2"; 67 method = "smc"; 68 }; 69 70 soc: soc { 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 reg = <0 0x10049c00 0 0x400>; 79 #sound-dai-cells = <0>; 80 /* place holder */ 81 }; 82 83 spi1: spi@1004b000 { 84 reg = <0 0x1004b000 0 0x400>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 /* place holder */ 88 }; 89 90 scif0: serial@1004b800 { 91 compatible = "renesas,scif-r9a07g043", 92 "renesas,scif-r9a07g044"; 93 reg = <0 0x1004b800 0 0x400>; 94 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-names = "eri", "rxi", "txi", 101 "bri", "dri", "tei"; 102 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 103 clock-names = "fck"; 104 power-domains = <&cpg>; 105 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 106 status = "disabled"; 107 }; 108 109 scif1: serial@1004bc00 { 110 compatible = "renesas,scif-r9a07g043", 111 "renesas,scif-r9a07g044"; 112 reg = <0 0x1004bc00 0 0x400>; 113 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "eri", "rxi", "txi", 120 "bri", "dri", "tei"; 121 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 122 clock-names = "fck"; 123 power-domains = <&cpg>; 124 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 125 status = "disabled"; 126 }; 127 128 scif2: serial@1004c000 { 129 compatible = "renesas,scif-r9a07g043", 130 "renesas,scif-r9a07g044"; 131 reg = <0 0x1004c000 0 0x400>; 132 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-names = "eri", "rxi", "txi", 139 "bri", "dri", "tei"; 140 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 141 clock-names = "fck"; 142 power-domains = <&cpg>; 143 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 144 status = "disabled"; 145 }; 146 147 scif3: serial@1004c400 { 148 compatible = "renesas,scif-r9a07g043", 149 "renesas,scif-r9a07g044"; 150 reg = <0 0x1004c400 0 0x400>; 151 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "eri", "rxi", "txi", 158 "bri", "dri", "tei"; 159 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 160 clock-names = "fck"; 161 power-domains = <&cpg>; 162 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 163 status = "disabled"; 164 }; 165 166 scif4: serial@1004c800 { 167 compatible = "renesas,scif-r9a07g043", 168 "renesas,scif-r9a07g044"; 169 reg = <0 0x1004c800 0 0x400>; 170 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "eri", "rxi", "txi", 177 "bri", "dri", "tei"; 178 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 179 clock-names = "fck"; 180 power-domains = <&cpg>; 181 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 182 status = "disabled"; 183 }; 184 185 sci0: serial@1004d000 { 186 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 187 reg = <0 0x1004d000 0 0x400>; 188 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-names = "eri", "rxi", "txi", "tei"; 193 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 194 clock-names = "fck"; 195 power-domains = <&cpg>; 196 resets = <&cpg R9A07G043_SCI0_RST>; 197 status = "disabled"; 198 }; 199 200 sci1: serial@1004d400 { 201 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 202 reg = <0 0x1004d400 0 0x400>; 203 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-names = "eri", "rxi", "txi", "tei"; 208 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 209 clock-names = "fck"; 210 power-domains = <&cpg>; 211 resets = <&cpg R9A07G043_SCI1_RST>; 212 status = "disabled"; 213 }; 214 215 canfd: can@10050000 { 216 reg = <0 0x10050000 0 0x8000>; 217 /* place holder */ 218 }; 219 220 i2c0: i2c@10058000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 224 reg = <0 0x10058000 0 0x400>; 225 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 227 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-names = "tei", "ri", "ti", "spi", "sti", 234 "naki", "ali", "tmoi"; 235 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 236 clock-frequency = <100000>; 237 resets = <&cpg R9A07G043_I2C0_MRST>; 238 power-domains = <&cpg>; 239 status = "disabled"; 240 }; 241 242 i2c1: i2c@10058400 { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 246 reg = <0 0x10058400 0 0x400>; 247 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 250 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-names = "tei", "ri", "ti", "spi", "sti", 256 "naki", "ali", "tmoi"; 257 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 258 clock-frequency = <100000>; 259 resets = <&cpg R9A07G043_I2C1_MRST>; 260 power-domains = <&cpg>; 261 status = "disabled"; 262 }; 263 264 i2c2: i2c@10058800 { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 268 reg = <0 0x10058800 0 0x400>; 269 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 271 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "tei", "ri", "ti", "spi", "sti", 278 "naki", "ali", "tmoi"; 279 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 280 clock-frequency = <100000>; 281 resets = <&cpg R9A07G043_I2C2_MRST>; 282 power-domains = <&cpg>; 283 status = "disabled"; 284 }; 285 286 i2c3: i2c@10058c00 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 290 reg = <0 0x10058c00 0 0x400>; 291 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "tei", "ri", "ti", "spi", "sti", 300 "naki", "ali", "tmoi"; 301 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 302 clock-frequency = <100000>; 303 resets = <&cpg R9A07G043_I2C3_MRST>; 304 power-domains = <&cpg>; 305 status = "disabled"; 306 }; 307 308 adc: adc@10059000 { 309 reg = <0 0x10059000 0 0x400>; 310 /* place holder */ 311 }; 312 313 sbc: spi@10060000 { 314 reg = <0 0x10060000 0 0x10000>, 315 <0 0x20000000 0 0x10000000>, 316 <0 0x10070000 0 0x10000>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 /* place holder */ 320 }; 321 322 cpg: clock-controller@11010000 { 323 compatible = "renesas,r9a07g043-cpg"; 324 reg = <0 0x11010000 0 0x10000>; 325 clocks = <&extal_clk>; 326 clock-names = "extal"; 327 #clock-cells = <2>; 328 #reset-cells = <1>; 329 #power-domain-cells = <0>; 330 }; 331 332 sysc: system-controller@11020000 { 333 compatible = "renesas,r9a07g043-sysc"; 334 reg = <0 0x11020000 0 0x10000>; 335 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 339 interrupt-names = "lpm_int", "ca55stbydone_int", 340 "cm33stbyr_int", "ca55_deny"; 341 status = "disabled"; 342 }; 343 344 pinctrl: pinctrl@11030000 { 345 compatible = "renesas,r9a07g043-pinctrl"; 346 reg = <0 0x11030000 0 0x10000>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 gpio-ranges = <&pinctrl 0 0 152>; 350 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 351 power-domains = <&cpg>; 352 resets = <&cpg R9A07G043_GPIO_RSTN>, 353 <&cpg R9A07G043_GPIO_PORT_RESETN>, 354 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 355 }; 356 357 dmac: dma-controller@11820000 { 358 compatible = "renesas,r9a07g043-dmac", 359 "renesas,rz-dmac"; 360 reg = <0 0x11820000 0 0x10000>, 361 <0 0x11830000 0 0x10000>; 362 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 363 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 364 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 365 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 366 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 369 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 370 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 371 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 373 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 374 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 375 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 379 interrupt-names = "error", 380 "ch0", "ch1", "ch2", "ch3", 381 "ch4", "ch5", "ch6", "ch7", 382 "ch8", "ch9", "ch10", "ch11", 383 "ch12", "ch13", "ch14", "ch15"; 384 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 385 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 386 power-domains = <&cpg>; 387 resets = <&cpg R9A07G043_DMAC_ARESETN>, 388 <&cpg R9A07G043_DMAC_RST_ASYNC>; 389 #dma-cells = <1>; 390 dma-channels = <16>; 391 }; 392 393 gic: interrupt-controller@11900000 { 394 compatible = "arm,gic-v3"; 395 #interrupt-cells = <3>; 396 #address-cells = <0>; 397 interrupt-controller; 398 reg = <0x0 0x11900000 0 0x40000>, 399 <0x0 0x11940000 0 0x60000>; 400 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 401 }; 402 403 sdhi0: mmc@11c00000 { 404 compatible = "renesas,sdhi-r9a07g043", 405 "renesas,rcar-gen3-sdhi"; 406 reg = <0x0 0x11c00000 0 0x10000>; 407 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 410 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 411 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 412 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 413 clock-names = "core", "clkh", "cd", "aclk"; 414 resets = <&cpg R9A07G043_SDHI0_IXRST>; 415 power-domains = <&cpg>; 416 status = "disabled"; 417 }; 418 419 sdhi1: mmc@11c10000 { 420 compatible = "renesas,sdhi-r9a07g043", 421 "renesas,rcar-gen3-sdhi"; 422 reg = <0x0 0x11c10000 0 0x10000>; 423 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 426 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 427 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 428 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 429 clock-names = "core", "clkh", "cd", "aclk"; 430 resets = <&cpg R9A07G043_SDHI1_IXRST>; 431 power-domains = <&cpg>; 432 status = "disabled"; 433 }; 434 435 eth0: ethernet@11c20000 { 436 compatible = "renesas,r9a07g043-gbeth", 437 "renesas,rzg2l-gbeth"; 438 reg = <0 0x11c20000 0 0x10000>; 439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 442 interrupt-names = "mux", "fil", "arp_ns"; 443 phy-mode = "rgmii"; 444 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 445 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 446 <&cpg CPG_CORE R9A07G043_CLK_HP>; 447 clock-names = "axi", "chi", "refclk"; 448 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 449 power-domains = <&cpg>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 eth1: ethernet@11c30000 { 456 compatible = "renesas,r9a07g043-gbeth", 457 "renesas,rzg2l-gbeth"; 458 reg = <0 0x11c30000 0 0x10000>; 459 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "mux", "fil", "arp_ns"; 463 phy-mode = "rgmii"; 464 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 465 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 466 <&cpg CPG_CORE R9A07G043_CLK_HP>; 467 clock-names = "axi", "chi", "refclk"; 468 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 469 power-domains = <&cpg>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 phyrst: usbphy-ctrl@11c40000 { 476 reg = <0 0x11c40000 0 0x10000>; 477 /* place holder */ 478 }; 479 480 ohci0: usb@11c50000 { 481 reg = <0 0x11c50000 0 0x100>; 482 /* place holder */ 483 }; 484 485 ohci1: usb@11c70000 { 486 reg = <0 0x11c70000 0 0x100>; 487 /* place holder */ 488 }; 489 490 ehci0: usb@11c50100 { 491 reg = <0 0x11c50100 0 0x100>; 492 /* place holder */ 493 }; 494 495 ehci1: usb@11c70100 { 496 reg = <0 0x11c70100 0 0x100>; 497 /* place holder */ 498 }; 499 500 usb2_phy0: usb-phy@11c50200 { 501 reg = <0 0x11c50200 0 0x700>; 502 /* place holder */ 503 }; 504 505 usb2_phy1: usb-phy@11c70200 { 506 reg = <0 0x11c70200 0 0x700>; 507 /* place holder */ 508 }; 509 510 hsusb: usb@11c60000 { 511 reg = <0 0x11c60000 0 0x10000>; 512 /* place holder */ 513 }; 514 515 wdt0: watchdog@12800800 { 516 reg = <0 0x12800800 0 0x400>; 517 /* place holder */ 518 }; 519 520 wdt2: watchdog@12800400 { 521 reg = <0 0x12800400 0 0x400>; 522 /* place holder */ 523 }; 524 525 ostm0: timer@12801000 { 526 reg = <0x0 0x12801000 0x0 0x400>; 527 /* place holder */ 528 }; 529 530 ostm1: timer@12801400 { 531 reg = <0x0 0x12801400 0x0 0x400>; 532 /* place holder */ 533 }; 534 535 ostm2: timer@12801800 { 536 reg = <0x0 0x12801800 0x0 0x400>; 537 /* place holder */ 538 }; 539 }; 540 541 timer { 542 compatible = "arm,armv8-timer"; 543 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 544 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 545 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 546 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 547 }; 548}; 549