mt8195.dtsi (ee3f54cf6ea8f7032946689de1cafc1c467f6d11) mt8195.dtsi (ecc0af6a3fe6ae47a341438f299b9439a6572def)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16#include <dt-bindings/reset/mt8195-resets.h>
16
17/ {
18 compatible = "mediatek,mt8195";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {

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1180 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1181 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1182 "xhci_ck";
1183 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1184 wakeup-source;
1185 status = "disabled";
1186 };
1187
17
18/ {
19 compatible = "mediatek,mt8195";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {

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1181 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1182 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1183 "xhci_ck";
1184 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1185 wakeup-source;
1186 status = "disabled";
1187 };
1188
1189 pcie0: pcie@112f0000 {
1190 compatible = "mediatek,mt8195-pcie",
1191 "mediatek,mt8192-pcie";
1192 device_type = "pci";
1193 #address-cells = <3>;
1194 #size-cells = <2>;
1195 reg = <0 0x112f0000 0 0x4000>;
1196 reg-names = "pcie-mac";
1197 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1198 bus-range = <0x00 0xff>;
1199 ranges = <0x81000000 0 0x20000000
1200 0x0 0x20000000 0 0x200000>,
1201 <0x82000000 0 0x20200000
1202 0x0 0x20200000 0 0x3e00000>;
1203
1204 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1205 iommu-map-mask = <0x0>;
1206
1207 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1208 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1209 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1210 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1211 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1212 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1213 clock-names = "pl_250m", "tl_26m", "tl_96m",
1214 "tl_32k", "peri_26m", "peri_mem";
1215 assigned-clocks = <&topckgen CLK_TOP_TL>;
1216 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1217
1218 phys = <&pciephy>;
1219 phy-names = "pcie-phy";
1220
1221 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1222
1223 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1224 reset-names = "mac";
1225
1226 #interrupt-cells = <1>;
1227 interrupt-map-mask = <0 0 0 7>;
1228 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1229 <0 0 0 2 &pcie_intc0 1>,
1230 <0 0 0 3 &pcie_intc0 2>,
1231 <0 0 0 4 &pcie_intc0 3>;
1232 status = "disabled";
1233
1234 pcie_intc0: interrupt-controller {
1235 interrupt-controller;
1236 #address-cells = <0>;
1237 #interrupt-cells = <1>;
1238 };
1239 };
1240
1241 pcie1: pcie@112f8000 {
1242 compatible = "mediatek,mt8195-pcie",
1243 "mediatek,mt8192-pcie";
1244 device_type = "pci";
1245 #address-cells = <3>;
1246 #size-cells = <2>;
1247 reg = <0 0x112f8000 0 0x4000>;
1248 reg-names = "pcie-mac";
1249 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1250 bus-range = <0x00 0xff>;
1251 ranges = <0x81000000 0 0x24000000
1252 0x0 0x24000000 0 0x200000>,
1253 <0x82000000 0 0x24200000
1254 0x0 0x24200000 0 0x3e00000>;
1255
1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1257 iommu-map-mask = <0x0>;
1258
1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1260 <&clk26m>,
1261 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1262 <&clk26m>,
1263 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1264 /* Designer has connect pcie1 with peri_mem_p0 clock */
1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1266 clock-names = "pl_250m", "tl_26m", "tl_96m",
1267 "tl_32k", "peri_26m", "peri_mem";
1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1270
1271 phys = <&u3port1 PHY_TYPE_PCIE>;
1272 phy-names = "pcie-phy";
1273 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1274
1275 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1276 reset-names = "mac";
1277
1278 #interrupt-cells = <1>;
1279 interrupt-map-mask = <0 0 0 7>;
1280 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1281 <0 0 0 2 &pcie_intc1 1>,
1282 <0 0 0 3 &pcie_intc1 2>,
1283 <0 0 0 4 &pcie_intc1 3>;
1284 status = "disabled";
1285
1286 pcie_intc1: interrupt-controller {
1287 interrupt-controller;
1288 #address-cells = <0>;
1289 #interrupt-cells = <1>;
1290 };
1291 };
1292
1188 nor_flash: spi@1132c000 {
1189 compatible = "mediatek,mt8195-nor",
1190 "mediatek,mt8173-nor";
1191 reg = <0 0x1132c000 0 0x1000>;
1192 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1193 clocks = <&topckgen CLK_TOP_SPINOR>,
1194 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1195 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;

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1239 u2_intr_p2: usb2-intr-p2@189,1 {
1240 reg = <0x189 0x1>;
1241 bits = <2 5>;
1242 };
1243 u2_intr_p3: usb2-intr-p3@189,2 {
1244 reg = <0x189 0x2>;
1245 bits = <7 5>;
1246 };
1293 nor_flash: spi@1132c000 {
1294 compatible = "mediatek,mt8195-nor",
1295 "mediatek,mt8173-nor";
1296 reg = <0 0x1132c000 0 0x1000>;
1297 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1298 clocks = <&topckgen CLK_TOP_SPINOR>,
1299 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1300 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;

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1344 u2_intr_p2: usb2-intr-p2@189,1 {
1345 reg = <0x189 0x1>;
1346 bits = <2 5>;
1347 };
1348 u2_intr_p3: usb2-intr-p3@189,2 {
1349 reg = <0x189 0x2>;
1350 bits = <7 5>;
1351 };
1352 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1353 reg = <0x190 0x1>;
1354 bits = <0 4>;
1355 };
1356 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1357 reg = <0x190 0x1>;
1358 bits = <4 4>;
1359 };
1360 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1361 reg = <0x191 0x1>;
1362 bits = <0 4>;
1363 };
1364 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1365 reg = <0x191 0x1>;
1366 bits = <4 4>;
1367 };
1368 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1369 reg = <0x192 0x1>;
1370 bits = <0 4>;
1371 };
1372 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1373 reg = <0x192 0x1>;
1374 bits = <4 4>;
1375 };
1376 pciephy_glb_intr: pciephy-glb-intr@193 {
1377 reg = <0x193 0x1>;
1378 bits = <0 4>;
1379 };
1247 };
1248
1249 u3phy2: t-phy@11c40000 {
1250 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1251 #address-cells = <1>;
1252 #size-cells = <1>;
1253 ranges = <0 0 0x11c40000 0x700>;
1254 status = "disabled";

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1459 nvmem-cells = <&u3_intr_p0>,
1460 <&u3_rx_imp_p0>,
1461 <&u3_tx_imp_p0>;
1462 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1463 #phy-cells = <1>;
1464 };
1465 };
1466
1380 };
1381
1382 u3phy2: t-phy@11c40000 {
1383 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1384 #address-cells = <1>;
1385 #size-cells = <1>;
1386 ranges = <0 0 0x11c40000 0x700>;
1387 status = "disabled";

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1592 nvmem-cells = <&u3_intr_p0>,
1593 <&u3_rx_imp_p0>,
1594 <&u3_tx_imp_p0>;
1595 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1596 #phy-cells = <1>;
1597 };
1598 };
1599
1600 pciephy: phy@11e80000 {
1601 compatible = "mediatek,mt8195-pcie-phy";
1602 reg = <0 0x11e80000 0 0x10000>;
1603 reg-names = "sif";
1604 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1605 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1606 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1607 <&pciephy_rx_ln1>;
1608 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1609 "tx_ln0_nmos", "rx_ln0",
1610 "tx_ln1_pmos", "tx_ln1_nmos",
1611 "rx_ln1";
1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1613 #phy-cells = <0>;
1614 status = "disabled";
1615 };
1616
1467 ufsphy: ufs-phy@11fa0000 {
1468 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1469 reg = <0 0x11fa0000 0 0xc000>;
1470 clocks = <&clk26m>, <&clk26m>;
1471 clock-names = "unipro", "mp";
1472 #phy-cells = <0>;
1473 status = "disabled";
1474 };

--- 712 unchanged lines hidden --- 		1617 ufsphy: ufs-phy@11fa0000 {
1618 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1619 reg = <0 0x11fa0000 0 0xc000>;
1620 clocks = <&clk26m>, <&clk26m>;
1621 clock-names = "unipro", "mp";
1622 #phy-cells = <0>;
1623 status = "disabled";
1624 };

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