1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16 17/ { 18 compatible = "mediatek,mt8195"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gce0 = &gce0; 25 gce1 = &gce1; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a55"; 35 reg = <0x000>; 36 enable-method = "psci"; 37 performance-domains = <&performance 0>; 38 clock-frequency = <1701000000>; 39 capacity-dmips-mhz = <578>; 40 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 41 next-level-cache = <&l2_0>; 42 #cooling-cells = <2>; 43 }; 44 45 cpu1: cpu@100 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a55"; 48 reg = <0x100>; 49 enable-method = "psci"; 50 performance-domains = <&performance 0>; 51 clock-frequency = <1701000000>; 52 capacity-dmips-mhz = <578>; 53 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 54 next-level-cache = <&l2_0>; 55 #cooling-cells = <2>; 56 }; 57 58 cpu2: cpu@200 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x200>; 62 enable-method = "psci"; 63 performance-domains = <&performance 0>; 64 clock-frequency = <1701000000>; 65 capacity-dmips-mhz = <578>; 66 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 cpu3: cpu@300 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x300>; 75 enable-method = "psci"; 76 performance-domains = <&performance 0>; 77 clock-frequency = <1701000000>; 78 capacity-dmips-mhz = <578>; 79 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 80 next-level-cache = <&l2_0>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu4: cpu@400 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a78"; 87 reg = <0x400>; 88 enable-method = "psci"; 89 performance-domains = <&performance 1>; 90 clock-frequency = <2171000000>; 91 capacity-dmips-mhz = <1024>; 92 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 93 next-level-cache = <&l2_1>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu5: cpu@500 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a78"; 100 reg = <0x500>; 101 enable-method = "psci"; 102 performance-domains = <&performance 1>; 103 clock-frequency = <2171000000>; 104 capacity-dmips-mhz = <1024>; 105 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 106 next-level-cache = <&l2_1>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu6: cpu@600 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a78"; 113 reg = <0x600>; 114 enable-method = "psci"; 115 performance-domains = <&performance 1>; 116 clock-frequency = <2171000000>; 117 capacity-dmips-mhz = <1024>; 118 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 119 next-level-cache = <&l2_1>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu7: cpu@700 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a78"; 126 reg = <0x700>; 127 enable-method = "psci"; 128 performance-domains = <&performance 1>; 129 clock-frequency = <2171000000>; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 132 next-level-cache = <&l2_1>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu-map { 137 cluster0 { 138 core0 { 139 cpu = <&cpu0>; 140 }; 141 142 core1 { 143 cpu = <&cpu1>; 144 }; 145 146 core2 { 147 cpu = <&cpu2>; 148 }; 149 150 core3 { 151 cpu = <&cpu3>; 152 }; 153 }; 154 155 cluster1 { 156 core0 { 157 cpu = <&cpu4>; 158 }; 159 160 core1 { 161 cpu = <&cpu5>; 162 }; 163 164 core2 { 165 cpu = <&cpu6>; 166 }; 167 168 core3 { 169 cpu = <&cpu7>; 170 }; 171 }; 172 }; 173 174 idle-states { 175 entry-method = "psci"; 176 177 cpu_off_l: cpu-off-l { 178 compatible = "arm,idle-state"; 179 arm,psci-suspend-param = <0x00010001>; 180 local-timer-stop; 181 entry-latency-us = <50>; 182 exit-latency-us = <95>; 183 min-residency-us = <580>; 184 }; 185 186 cpu_off_b: cpu-off-b { 187 compatible = "arm,idle-state"; 188 arm,psci-suspend-param = <0x00010001>; 189 local-timer-stop; 190 entry-latency-us = <45>; 191 exit-latency-us = <140>; 192 min-residency-us = <740>; 193 }; 194 195 cluster_off_l: cluster-off-l { 196 compatible = "arm,idle-state"; 197 arm,psci-suspend-param = <0x01010002>; 198 local-timer-stop; 199 entry-latency-us = <55>; 200 exit-latency-us = <155>; 201 min-residency-us = <840>; 202 }; 203 204 cluster_off_b: cluster-off-b { 205 compatible = "arm,idle-state"; 206 arm,psci-suspend-param = <0x01010002>; 207 local-timer-stop; 208 entry-latency-us = <50>; 209 exit-latency-us = <200>; 210 min-residency-us = <1000>; 211 }; 212 }; 213 214 l2_0: l2-cache0 { 215 compatible = "cache"; 216 cache-level = <2>; 217 next-level-cache = <&l3_0>; 218 }; 219 220 l2_1: l2-cache1 { 221 compatible = "cache"; 222 cache-level = <2>; 223 next-level-cache = <&l3_0>; 224 }; 225 226 l3_0: l3-cache { 227 compatible = "cache"; 228 cache-level = <3>; 229 }; 230 }; 231 232 dsu-pmu { 233 compatible = "arm,dsu-pmu"; 234 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 235 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 236 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 237 }; 238 239 dmic_codec: dmic-codec { 240 compatible = "dmic-codec"; 241 num-channels = <2>; 242 wakeup-delay-ms = <50>; 243 }; 244 245 sound: mt8195-sound { 246 mediatek,platform = <&afe>; 247 status = "disabled"; 248 }; 249 250 clk26m: oscillator-26m { 251 compatible = "fixed-clock"; 252 #clock-cells = <0>; 253 clock-frequency = <26000000>; 254 clock-output-names = "clk26m"; 255 }; 256 257 clk32k: oscillator-32k { 258 compatible = "fixed-clock"; 259 #clock-cells = <0>; 260 clock-frequency = <32768>; 261 clock-output-names = "clk32k"; 262 }; 263 264 performance: performance-controller@11bc10 { 265 compatible = "mediatek,cpufreq-hw"; 266 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 267 #performance-domain-cells = <1>; 268 }; 269 270 pmu-a55 { 271 compatible = "arm,cortex-a55-pmu"; 272 interrupt-parent = <&gic>; 273 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 274 }; 275 276 pmu-a78 { 277 compatible = "arm,cortex-a78-pmu"; 278 interrupt-parent = <&gic>; 279 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 280 }; 281 282 psci { 283 compatible = "arm,psci-1.0"; 284 method = "smc"; 285 }; 286 287 timer: timer { 288 compatible = "arm,armv8-timer"; 289 interrupt-parent = <&gic>; 290 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 291 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 292 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 293 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 294 }; 295 296 soc { 297 #address-cells = <2>; 298 #size-cells = <2>; 299 compatible = "simple-bus"; 300 ranges; 301 302 gic: interrupt-controller@c000000 { 303 compatible = "arm,gic-v3"; 304 #interrupt-cells = <4>; 305 #redistributor-regions = <1>; 306 interrupt-parent = <&gic>; 307 interrupt-controller; 308 reg = <0 0x0c000000 0 0x40000>, 309 <0 0x0c040000 0 0x200000>; 310 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 311 312 ppi-partitions { 313 ppi_cluster0: interrupt-partition-0 { 314 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 315 }; 316 317 ppi_cluster1: interrupt-partition-1 { 318 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 319 }; 320 }; 321 }; 322 323 topckgen: syscon@10000000 { 324 compatible = "mediatek,mt8195-topckgen", "syscon"; 325 reg = <0 0x10000000 0 0x1000>; 326 #clock-cells = <1>; 327 }; 328 329 infracfg_ao: syscon@10001000 { 330 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 331 reg = <0 0x10001000 0 0x1000>; 332 #clock-cells = <1>; 333 #reset-cells = <1>; 334 }; 335 336 pericfg: syscon@10003000 { 337 compatible = "mediatek,mt8195-pericfg", "syscon"; 338 reg = <0 0x10003000 0 0x1000>; 339 #clock-cells = <1>; 340 }; 341 342 pio: pinctrl@10005000 { 343 compatible = "mediatek,mt8195-pinctrl"; 344 reg = <0 0x10005000 0 0x1000>, 345 <0 0x11d10000 0 0x1000>, 346 <0 0x11d30000 0 0x1000>, 347 <0 0x11d40000 0 0x1000>, 348 <0 0x11e20000 0 0x1000>, 349 <0 0x11eb0000 0 0x1000>, 350 <0 0x11f40000 0 0x1000>, 351 <0 0x1000b000 0 0x1000>; 352 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 353 "iocfg_br", "iocfg_lm", "iocfg_rb", 354 "iocfg_tl", "eint"; 355 gpio-controller; 356 #gpio-cells = <2>; 357 gpio-ranges = <&pio 0 0 144>; 358 interrupt-controller; 359 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 360 #interrupt-cells = <2>; 361 }; 362 363 scpsys: syscon@10006000 { 364 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 365 reg = <0 0x10006000 0 0x1000>; 366 367 /* System Power Manager */ 368 spm: power-controller { 369 compatible = "mediatek,mt8195-power-controller"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 #power-domain-cells = <1>; 373 374 /* power domain of the SoC */ 375 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 376 reg = <MT8195_POWER_DOMAIN_MFG0>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 #power-domain-cells = <1>; 380 381 power-domain@MT8195_POWER_DOMAIN_MFG1 { 382 reg = <MT8195_POWER_DOMAIN_MFG1>; 383 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 384 clock-names = "mfg"; 385 mediatek,infracfg = <&infracfg_ao>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 #power-domain-cells = <1>; 389 390 power-domain@MT8195_POWER_DOMAIN_MFG2 { 391 reg = <MT8195_POWER_DOMAIN_MFG2>; 392 #power-domain-cells = <0>; 393 }; 394 395 power-domain@MT8195_POWER_DOMAIN_MFG3 { 396 reg = <MT8195_POWER_DOMAIN_MFG3>; 397 #power-domain-cells = <0>; 398 }; 399 400 power-domain@MT8195_POWER_DOMAIN_MFG4 { 401 reg = <MT8195_POWER_DOMAIN_MFG4>; 402 #power-domain-cells = <0>; 403 }; 404 405 power-domain@MT8195_POWER_DOMAIN_MFG5 { 406 reg = <MT8195_POWER_DOMAIN_MFG5>; 407 #power-domain-cells = <0>; 408 }; 409 410 power-domain@MT8195_POWER_DOMAIN_MFG6 { 411 reg = <MT8195_POWER_DOMAIN_MFG6>; 412 #power-domain-cells = <0>; 413 }; 414 }; 415 }; 416 417 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 418 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 419 clocks = <&topckgen CLK_TOP_VPP>, 420 <&topckgen CLK_TOP_CAM>, 421 <&topckgen CLK_TOP_CCU>, 422 <&topckgen CLK_TOP_IMG>, 423 <&topckgen CLK_TOP_VENC>, 424 <&topckgen CLK_TOP_VDEC>, 425 <&topckgen CLK_TOP_WPE_VPP>, 426 <&topckgen CLK_TOP_CFG_VPP0>, 427 <&vppsys0 CLK_VPP0_SMI_COMMON>, 428 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 429 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 430 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 431 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 432 <&vppsys0 CLK_VPP0_GALS_INFRA>, 433 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 434 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 435 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 436 <&vppsys0 CLK_VPP0_SMI_REORDER>, 437 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 438 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 439 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 440 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 441 <&vppsys0 CLK_VPP0_SMI_RSI>, 442 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 443 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 444 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 445 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 446 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 447 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 448 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 449 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 450 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 451 "vppsys0-12", "vppsys0-13", "vppsys0-14", 452 "vppsys0-15", "vppsys0-16", "vppsys0-17", 453 "vppsys0-18"; 454 mediatek,infracfg = <&infracfg_ao>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 #power-domain-cells = <1>; 458 459 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 460 reg = <MT8195_POWER_DOMAIN_VDEC1>; 461 clocks = <&vdecsys CLK_VDEC_LARB1>; 462 clock-names = "vdec1-0"; 463 mediatek,infracfg = <&infracfg_ao>; 464 #power-domain-cells = <0>; 465 }; 466 467 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 468 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 469 mediatek,infracfg = <&infracfg_ao>; 470 #power-domain-cells = <0>; 471 }; 472 473 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 474 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 475 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 476 <&vdosys0 CLK_VDO0_SMI_GALS>, 477 <&vdosys0 CLK_VDO0_SMI_COMMON>, 478 <&vdosys0 CLK_VDO0_SMI_EMI>, 479 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 480 <&vdosys0 CLK_VDO0_SMI_LARB>, 481 <&vdosys0 CLK_VDO0_SMI_RSI>; 482 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 483 "vdosys0-2", "vdosys0-3", 484 "vdosys0-4", "vdosys0-5"; 485 mediatek,infracfg = <&infracfg_ao>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 #power-domain-cells = <1>; 489 490 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 491 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 492 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 493 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 494 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 495 clock-names = "vppsys1", "vppsys1-0", 496 "vppsys1-1"; 497 mediatek,infracfg = <&infracfg_ao>; 498 #power-domain-cells = <0>; 499 }; 500 501 power-domain@MT8195_POWER_DOMAIN_WPESYS { 502 reg = <MT8195_POWER_DOMAIN_WPESYS>; 503 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 504 <&wpesys CLK_WPE_SMI_LARB8>, 505 <&wpesys CLK_WPE_SMI_LARB7_P>, 506 <&wpesys CLK_WPE_SMI_LARB8_P>; 507 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 508 "wepsys-3"; 509 mediatek,infracfg = <&infracfg_ao>; 510 #power-domain-cells = <0>; 511 }; 512 513 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 514 reg = <MT8195_POWER_DOMAIN_VDEC0>; 515 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 516 clock-names = "vdec0-0"; 517 mediatek,infracfg = <&infracfg_ao>; 518 #power-domain-cells = <0>; 519 }; 520 521 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 522 reg = <MT8195_POWER_DOMAIN_VDEC2>; 523 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 524 clock-names = "vdec2-0"; 525 mediatek,infracfg = <&infracfg_ao>; 526 #power-domain-cells = <0>; 527 }; 528 529 power-domain@MT8195_POWER_DOMAIN_VENC { 530 reg = <MT8195_POWER_DOMAIN_VENC>; 531 mediatek,infracfg = <&infracfg_ao>; 532 #power-domain-cells = <0>; 533 }; 534 535 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 536 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 537 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 538 <&vdosys1 CLK_VDO1_SMI_LARB2>, 539 <&vdosys1 CLK_VDO1_SMI_LARB3>, 540 <&vdosys1 CLK_VDO1_GALS>; 541 clock-names = "vdosys1", "vdosys1-0", 542 "vdosys1-1", "vdosys1-2"; 543 mediatek,infracfg = <&infracfg_ao>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 #power-domain-cells = <1>; 547 548 power-domain@MT8195_POWER_DOMAIN_DP_TX { 549 reg = <MT8195_POWER_DOMAIN_DP_TX>; 550 mediatek,infracfg = <&infracfg_ao>; 551 #power-domain-cells = <0>; 552 }; 553 554 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 555 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 556 mediatek,infracfg = <&infracfg_ao>; 557 #power-domain-cells = <0>; 558 }; 559 560 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 561 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 562 clocks = <&topckgen CLK_TOP_HDMI_APB>; 563 clock-names = "hdmi_tx"; 564 #power-domain-cells = <0>; 565 }; 566 }; 567 568 power-domain@MT8195_POWER_DOMAIN_IMG { 569 reg = <MT8195_POWER_DOMAIN_IMG>; 570 clocks = <&imgsys CLK_IMG_LARB9>, 571 <&imgsys CLK_IMG_GALS>; 572 clock-names = "img-0", "img-1"; 573 mediatek,infracfg = <&infracfg_ao>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 #power-domain-cells = <1>; 577 578 power-domain@MT8195_POWER_DOMAIN_DIP { 579 reg = <MT8195_POWER_DOMAIN_DIP>; 580 #power-domain-cells = <0>; 581 }; 582 583 power-domain@MT8195_POWER_DOMAIN_IPE { 584 reg = <MT8195_POWER_DOMAIN_IPE>; 585 clocks = <&topckgen CLK_TOP_IPE>, 586 <&imgsys CLK_IMG_IPE>, 587 <&ipesys CLK_IPE_SMI_LARB12>; 588 clock-names = "ipe", "ipe-0", "ipe-1"; 589 mediatek,infracfg = <&infracfg_ao>; 590 #power-domain-cells = <0>; 591 }; 592 }; 593 594 power-domain@MT8195_POWER_DOMAIN_CAM { 595 reg = <MT8195_POWER_DOMAIN_CAM>; 596 clocks = <&camsys CLK_CAM_LARB13>, 597 <&camsys CLK_CAM_LARB14>, 598 <&camsys CLK_CAM_CAM2MM0_GALS>, 599 <&camsys CLK_CAM_CAM2MM1_GALS>, 600 <&camsys CLK_CAM_CAM2SYS_GALS>; 601 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 602 "cam-4"; 603 mediatek,infracfg = <&infracfg_ao>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 #power-domain-cells = <1>; 607 608 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 609 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 610 #power-domain-cells = <0>; 611 }; 612 613 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 614 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 615 #power-domain-cells = <0>; 616 }; 617 618 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 619 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 620 #power-domain-cells = <0>; 621 }; 622 }; 623 }; 624 }; 625 626 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 627 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 628 mediatek,infracfg = <&infracfg_ao>; 629 #power-domain-cells = <0>; 630 }; 631 632 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 633 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 634 mediatek,infracfg = <&infracfg_ao>; 635 #power-domain-cells = <0>; 636 }; 637 638 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 639 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 640 #power-domain-cells = <0>; 641 }; 642 643 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 644 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 645 #power-domain-cells = <0>; 646 }; 647 648 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 649 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 650 clocks = <&topckgen CLK_TOP_SENINF>, 651 <&topckgen CLK_TOP_SENINF2>; 652 clock-names = "csi_rx_top", "csi_rx_top1"; 653 #power-domain-cells = <0>; 654 }; 655 656 power-domain@MT8195_POWER_DOMAIN_ETHER { 657 reg = <MT8195_POWER_DOMAIN_ETHER>; 658 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 659 clock-names = "ether"; 660 #power-domain-cells = <0>; 661 }; 662 663 power-domain@MT8195_POWER_DOMAIN_ADSP { 664 reg = <MT8195_POWER_DOMAIN_ADSP>; 665 clocks = <&topckgen CLK_TOP_ADSP>, 666 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 667 clock-names = "adsp", "adsp1"; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 mediatek,infracfg = <&infracfg_ao>; 671 #power-domain-cells = <1>; 672 673 power-domain@MT8195_POWER_DOMAIN_AUDIO { 674 reg = <MT8195_POWER_DOMAIN_AUDIO>; 675 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 676 <&topckgen CLK_TOP_AUD_INTBUS>, 677 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 678 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 679 clock-names = "audio", "audio1", "audio2", 680 "audio3"; 681 mediatek,infracfg = <&infracfg_ao>; 682 #power-domain-cells = <0>; 683 }; 684 }; 685 }; 686 }; 687 688 watchdog: watchdog@10007000 { 689 compatible = "mediatek,mt8195-wdt", 690 "mediatek,mt6589-wdt"; 691 mediatek,disable-extrst; 692 reg = <0 0x10007000 0 0x100>; 693 #reset-cells = <1>; 694 }; 695 696 apmixedsys: syscon@1000c000 { 697 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 698 reg = <0 0x1000c000 0 0x1000>; 699 #clock-cells = <1>; 700 }; 701 702 systimer: timer@10017000 { 703 compatible = "mediatek,mt8195-timer", 704 "mediatek,mt6765-timer"; 705 reg = <0 0x10017000 0 0x1000>; 706 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 707 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 708 }; 709 710 pwrap: pwrap@10024000 { 711 compatible = "mediatek,mt8195-pwrap", "syscon"; 712 reg = <0 0x10024000 0 0x1000>; 713 reg-names = "pwrap"; 714 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 715 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 716 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 717 clock-names = "spi", "wrap"; 718 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 719 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 720 }; 721 722 spmi: spmi@10027000 { 723 compatible = "mediatek,mt8195-spmi"; 724 reg = <0 0x10027000 0 0x000e00>, 725 <0 0x10029000 0 0x000100>; 726 reg-names = "pmif", "spmimst"; 727 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 728 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 729 <&topckgen CLK_TOP_SPMI_M_MST>; 730 clock-names = "pmif_sys_ck", 731 "pmif_tmr_ck", 732 "spmimst_clk_mux"; 733 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 734 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 735 }; 736 737 iommu_infra: infra-iommu@10315000 { 738 compatible = "mediatek,mt8195-iommu-infra"; 739 reg = <0 0x10315000 0 0x5000>; 740 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 741 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 742 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 743 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 744 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 745 #iommu-cells = <1>; 746 }; 747 748 gce0: mailbox@10320000 { 749 compatible = "mediatek,mt8195-gce"; 750 reg = <0 0x10320000 0 0x4000>; 751 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 752 #mbox-cells = <2>; 753 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 754 }; 755 756 gce1: mailbox@10330000 { 757 compatible = "mediatek,mt8195-gce"; 758 reg = <0 0x10330000 0 0x4000>; 759 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 760 #mbox-cells = <2>; 761 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 762 }; 763 764 scp: scp@10500000 { 765 compatible = "mediatek,mt8195-scp"; 766 reg = <0 0x10500000 0 0x100000>, 767 <0 0x10720000 0 0xe0000>, 768 <0 0x10700000 0 0x8000>; 769 reg-names = "sram", "cfg", "l1tcm"; 770 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 771 status = "disabled"; 772 }; 773 774 scp_adsp: clock-controller@10720000 { 775 compatible = "mediatek,mt8195-scp_adsp"; 776 reg = <0 0x10720000 0 0x1000>; 777 #clock-cells = <1>; 778 }; 779 780 adsp: dsp@10803000 { 781 compatible = "mediatek,mt8195-dsp"; 782 reg = <0 0x10803000 0 0x1000>, 783 <0 0x10840000 0 0x40000>; 784 reg-names = "cfg", "sram"; 785 clocks = <&topckgen CLK_TOP_ADSP>, 786 <&clk26m>, 787 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 788 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 789 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 790 <&topckgen CLK_TOP_AUDIO_H>; 791 clock-names = "adsp_sel", 792 "clk26m_ck", 793 "audio_local_bus", 794 "mainpll_d7_d2", 795 "scp_adsp_audiodsp", 796 "audio_h"; 797 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 798 mbox-names = "rx", "tx"; 799 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 800 status = "disabled"; 801 }; 802 803 adsp_mailbox0: mailbox@10816000 { 804 compatible = "mediatek,mt8195-adsp-mbox"; 805 #mbox-cells = <0>; 806 reg = <0 0x10816000 0 0x1000>; 807 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 808 }; 809 810 adsp_mailbox1: mailbox@10817000 { 811 compatible = "mediatek,mt8195-adsp-mbox"; 812 #mbox-cells = <0>; 813 reg = <0 0x10817000 0 0x1000>; 814 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 815 }; 816 817 afe: mt8195-afe-pcm@10890000 { 818 compatible = "mediatek,mt8195-audio"; 819 reg = <0 0x10890000 0 0x10000>; 820 mediatek,topckgen = <&topckgen>; 821 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 822 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 823 resets = <&watchdog 14>; 824 reset-names = "audiosys"; 825 clocks = <&clk26m>, 826 <&apmixedsys CLK_APMIXED_APLL1>, 827 <&apmixedsys CLK_APMIXED_APLL2>, 828 <&topckgen CLK_TOP_APLL12_DIV0>, 829 <&topckgen CLK_TOP_APLL12_DIV1>, 830 <&topckgen CLK_TOP_APLL12_DIV2>, 831 <&topckgen CLK_TOP_APLL12_DIV3>, 832 <&topckgen CLK_TOP_APLL12_DIV9>, 833 <&topckgen CLK_TOP_A1SYS_HP>, 834 <&topckgen CLK_TOP_AUD_INTBUS>, 835 <&topckgen CLK_TOP_AUDIO_H>, 836 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 837 <&topckgen CLK_TOP_DPTX_MCK>, 838 <&topckgen CLK_TOP_I2SO1_MCK>, 839 <&topckgen CLK_TOP_I2SO2_MCK>, 840 <&topckgen CLK_TOP_I2SI1_MCK>, 841 <&topckgen CLK_TOP_I2SI2_MCK>, 842 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 843 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 844 clock-names = "clk26m", 845 "apll1_ck", 846 "apll2_ck", 847 "apll12_div0", 848 "apll12_div1", 849 "apll12_div2", 850 "apll12_div3", 851 "apll12_div9", 852 "a1sys_hp_sel", 853 "aud_intbus_sel", 854 "audio_h_sel", 855 "audio_local_bus_sel", 856 "dptx_m_sel", 857 "i2so1_m_sel", 858 "i2so2_m_sel", 859 "i2si1_m_sel", 860 "i2si2_m_sel", 861 "infra_ao_audio_26m_b", 862 "scp_adsp_audiodsp"; 863 status = "disabled"; 864 }; 865 866 uart0: serial@11001100 { 867 compatible = "mediatek,mt8195-uart", 868 "mediatek,mt6577-uart"; 869 reg = <0 0x11001100 0 0x100>; 870 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 871 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 872 clock-names = "baud", "bus"; 873 status = "disabled"; 874 }; 875 876 uart1: serial@11001200 { 877 compatible = "mediatek,mt8195-uart", 878 "mediatek,mt6577-uart"; 879 reg = <0 0x11001200 0 0x100>; 880 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 881 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 882 clock-names = "baud", "bus"; 883 status = "disabled"; 884 }; 885 886 uart2: serial@11001300 { 887 compatible = "mediatek,mt8195-uart", 888 "mediatek,mt6577-uart"; 889 reg = <0 0x11001300 0 0x100>; 890 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 891 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 892 clock-names = "baud", "bus"; 893 status = "disabled"; 894 }; 895 896 uart3: serial@11001400 { 897 compatible = "mediatek,mt8195-uart", 898 "mediatek,mt6577-uart"; 899 reg = <0 0x11001400 0 0x100>; 900 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 901 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 902 clock-names = "baud", "bus"; 903 status = "disabled"; 904 }; 905 906 uart4: serial@11001500 { 907 compatible = "mediatek,mt8195-uart", 908 "mediatek,mt6577-uart"; 909 reg = <0 0x11001500 0 0x100>; 910 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 911 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 912 clock-names = "baud", "bus"; 913 status = "disabled"; 914 }; 915 916 uart5: serial@11001600 { 917 compatible = "mediatek,mt8195-uart", 918 "mediatek,mt6577-uart"; 919 reg = <0 0x11001600 0 0x100>; 920 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 921 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 922 clock-names = "baud", "bus"; 923 status = "disabled"; 924 }; 925 926 auxadc: auxadc@11002000 { 927 compatible = "mediatek,mt8195-auxadc", 928 "mediatek,mt8173-auxadc"; 929 reg = <0 0x11002000 0 0x1000>; 930 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 931 clock-names = "main"; 932 #io-channel-cells = <1>; 933 status = "disabled"; 934 }; 935 936 pericfg_ao: syscon@11003000 { 937 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 938 reg = <0 0x11003000 0 0x1000>; 939 #clock-cells = <1>; 940 }; 941 942 spi0: spi@1100a000 { 943 compatible = "mediatek,mt8195-spi", 944 "mediatek,mt6765-spi"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 reg = <0 0x1100a000 0 0x1000>; 948 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 949 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 950 <&topckgen CLK_TOP_SPI>, 951 <&infracfg_ao CLK_INFRA_AO_SPI0>; 952 clock-names = "parent-clk", "sel-clk", "spi-clk"; 953 status = "disabled"; 954 }; 955 956 spi1: spi@11010000 { 957 compatible = "mediatek,mt8195-spi", 958 "mediatek,mt6765-spi"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 reg = <0 0x11010000 0 0x1000>; 962 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 963 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 964 <&topckgen CLK_TOP_SPI>, 965 <&infracfg_ao CLK_INFRA_AO_SPI1>; 966 clock-names = "parent-clk", "sel-clk", "spi-clk"; 967 status = "disabled"; 968 }; 969 970 spi2: spi@11012000 { 971 compatible = "mediatek,mt8195-spi", 972 "mediatek,mt6765-spi"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 reg = <0 0x11012000 0 0x1000>; 976 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 977 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 978 <&topckgen CLK_TOP_SPI>, 979 <&infracfg_ao CLK_INFRA_AO_SPI2>; 980 clock-names = "parent-clk", "sel-clk", "spi-clk"; 981 status = "disabled"; 982 }; 983 984 spi3: spi@11013000 { 985 compatible = "mediatek,mt8195-spi", 986 "mediatek,mt6765-spi"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 reg = <0 0x11013000 0 0x1000>; 990 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 991 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 992 <&topckgen CLK_TOP_SPI>, 993 <&infracfg_ao CLK_INFRA_AO_SPI3>; 994 clock-names = "parent-clk", "sel-clk", "spi-clk"; 995 status = "disabled"; 996 }; 997 998 spi4: spi@11018000 { 999 compatible = "mediatek,mt8195-spi", 1000 "mediatek,mt6765-spi"; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 reg = <0 0x11018000 0 0x1000>; 1004 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1005 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1006 <&topckgen CLK_TOP_SPI>, 1007 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1008 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1009 status = "disabled"; 1010 }; 1011 1012 spi5: spi@11019000 { 1013 compatible = "mediatek,mt8195-spi", 1014 "mediatek,mt6765-spi"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 reg = <0 0x11019000 0 0x1000>; 1018 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1019 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1020 <&topckgen CLK_TOP_SPI>, 1021 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1022 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1023 status = "disabled"; 1024 }; 1025 1026 spis0: spi@1101d000 { 1027 compatible = "mediatek,mt8195-spi-slave"; 1028 reg = <0 0x1101d000 0 0x1000>; 1029 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1030 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1031 clock-names = "spi"; 1032 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1033 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1034 status = "disabled"; 1035 }; 1036 1037 spis1: spi@1101e000 { 1038 compatible = "mediatek,mt8195-spi-slave"; 1039 reg = <0 0x1101e000 0 0x1000>; 1040 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1041 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1042 clock-names = "spi"; 1043 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1044 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1045 status = "disabled"; 1046 }; 1047 1048 xhci0: usb@11200000 { 1049 compatible = "mediatek,mt8195-xhci", 1050 "mediatek,mtk-xhci"; 1051 reg = <0 0x11200000 0 0x1000>, 1052 <0 0x11203e00 0 0x0100>; 1053 reg-names = "mac", "ippc"; 1054 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1055 phys = <&u2port0 PHY_TYPE_USB2>, 1056 <&u3port0 PHY_TYPE_USB3>; 1057 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1058 <&topckgen CLK_TOP_SSUSB_XHCI>; 1059 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1060 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1061 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1062 <&topckgen CLK_TOP_SSUSB_REF>, 1063 <&apmixedsys CLK_APMIXED_USB1PLL>, 1064 <&clk26m>, 1065 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1066 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1067 "xhci_ck"; 1068 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1069 wakeup-source; 1070 status = "disabled"; 1071 }; 1072 1073 mmc0: mmc@11230000 { 1074 compatible = "mediatek,mt8195-mmc", 1075 "mediatek,mt8183-mmc"; 1076 reg = <0 0x11230000 0 0x10000>, 1077 <0 0x11f50000 0 0x1000>; 1078 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1079 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1080 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1081 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1082 clock-names = "source", "hclk", "source_cg"; 1083 status = "disabled"; 1084 }; 1085 1086 mmc1: mmc@11240000 { 1087 compatible = "mediatek,mt8195-mmc", 1088 "mediatek,mt8183-mmc"; 1089 reg = <0 0x11240000 0 0x1000>, 1090 <0 0x11c70000 0 0x1000>; 1091 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1092 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1093 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1094 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1095 clock-names = "source", "hclk", "source_cg"; 1096 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1097 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1098 status = "disabled"; 1099 }; 1100 1101 mmc2: mmc@11250000 { 1102 compatible = "mediatek,mt8195-mmc", 1103 "mediatek,mt8183-mmc"; 1104 reg = <0 0x11250000 0 0x1000>, 1105 <0 0x11e60000 0 0x1000>; 1106 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1107 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1108 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1109 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1110 clock-names = "source", "hclk", "source_cg"; 1111 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1112 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1113 status = "disabled"; 1114 }; 1115 1116 xhci1: usb@11290000 { 1117 compatible = "mediatek,mt8195-xhci", 1118 "mediatek,mtk-xhci"; 1119 reg = <0 0x11290000 0 0x1000>, 1120 <0 0x11293e00 0 0x0100>; 1121 reg-names = "mac", "ippc"; 1122 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1123 phys = <&u2port1 PHY_TYPE_USB2>; 1124 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1125 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1126 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1127 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1128 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1129 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1130 <&apmixedsys CLK_APMIXED_USB1PLL>, 1131 <&clk26m>, 1132 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1133 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1134 "xhci_ck"; 1135 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1136 wakeup-source; 1137 status = "disabled"; 1138 }; 1139 1140 xhci2: usb@112a0000 { 1141 compatible = "mediatek,mt8195-xhci", 1142 "mediatek,mtk-xhci"; 1143 reg = <0 0x112a0000 0 0x1000>, 1144 <0 0x112a3e00 0 0x0100>; 1145 reg-names = "mac", "ippc"; 1146 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1147 phys = <&u2port2 PHY_TYPE_USB2>; 1148 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1149 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1150 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1151 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1152 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1153 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1154 <&clk26m>, 1155 <&clk26m>, 1156 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1157 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1158 "xhci_ck"; 1159 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1160 wakeup-source; 1161 status = "disabled"; 1162 }; 1163 1164 xhci3: usb@112b0000 { 1165 compatible = "mediatek,mt8195-xhci", 1166 "mediatek,mtk-xhci"; 1167 reg = <0 0x112b0000 0 0x1000>, 1168 <0 0x112b3e00 0 0x0100>; 1169 reg-names = "mac", "ippc"; 1170 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1171 phys = <&u2port3 PHY_TYPE_USB2>; 1172 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1173 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1174 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1175 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1176 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1177 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1178 <&clk26m>, 1179 <&clk26m>, 1180 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1181 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1182 "xhci_ck"; 1183 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1184 wakeup-source; 1185 status = "disabled"; 1186 }; 1187 1188 nor_flash: spi@1132c000 { 1189 compatible = "mediatek,mt8195-nor", 1190 "mediatek,mt8173-nor"; 1191 reg = <0 0x1132c000 0 0x1000>; 1192 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1193 clocks = <&topckgen CLK_TOP_SPINOR>, 1194 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1195 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1196 clock-names = "spi", "sf", "axi"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 efuse: efuse@11c10000 { 1203 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1204 reg = <0 0x11c10000 0 0x1000>; 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1208 reg = <0x184 0x1>; 1209 bits = <0 5>; 1210 }; 1211 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1212 reg = <0x184 0x2>; 1213 bits = <5 5>; 1214 }; 1215 u3_intr_p0: usb3-intr@185 { 1216 reg = <0x185 0x1>; 1217 bits = <2 6>; 1218 }; 1219 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1220 reg = <0x186 0x1>; 1221 bits = <0 5>; 1222 }; 1223 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1224 reg = <0x186 0x2>; 1225 bits = <5 5>; 1226 }; 1227 comb_intr_p1: usb3-intr@187 { 1228 reg = <0x187 0x1>; 1229 bits = <2 6>; 1230 }; 1231 u2_intr_p0: usb2-intr-p0@188,1 { 1232 reg = <0x188 0x1>; 1233 bits = <0 5>; 1234 }; 1235 u2_intr_p1: usb2-intr-p1@188,2 { 1236 reg = <0x188 0x2>; 1237 bits = <5 5>; 1238 }; 1239 u2_intr_p2: usb2-intr-p2@189,1 { 1240 reg = <0x189 0x1>; 1241 bits = <2 5>; 1242 }; 1243 u2_intr_p3: usb2-intr-p3@189,2 { 1244 reg = <0x189 0x2>; 1245 bits = <7 5>; 1246 }; 1247 }; 1248 1249 u3phy2: t-phy@11c40000 { 1250 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1251 #address-cells = <1>; 1252 #size-cells = <1>; 1253 ranges = <0 0 0x11c40000 0x700>; 1254 status = "disabled"; 1255 1256 u2port2: usb-phy@0 { 1257 reg = <0x0 0x700>; 1258 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1259 clock-names = "ref"; 1260 #phy-cells = <1>; 1261 }; 1262 }; 1263 1264 u3phy3: t-phy@11c50000 { 1265 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1266 #address-cells = <1>; 1267 #size-cells = <1>; 1268 ranges = <0 0 0x11c50000 0x700>; 1269 status = "disabled"; 1270 1271 u2port3: usb-phy@0 { 1272 reg = <0x0 0x700>; 1273 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1274 clock-names = "ref"; 1275 #phy-cells = <1>; 1276 }; 1277 }; 1278 1279 i2c5: i2c@11d00000 { 1280 compatible = "mediatek,mt8195-i2c", 1281 "mediatek,mt8192-i2c"; 1282 reg = <0 0x11d00000 0 0x1000>, 1283 <0 0x10220580 0 0x80>; 1284 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1285 clock-div = <1>; 1286 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1287 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1288 clock-names = "main", "dma"; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 i2c6: i2c@11d01000 { 1295 compatible = "mediatek,mt8195-i2c", 1296 "mediatek,mt8192-i2c"; 1297 reg = <0 0x11d01000 0 0x1000>, 1298 <0 0x10220600 0 0x80>; 1299 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1300 clock-div = <1>; 1301 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1302 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1303 clock-names = "main", "dma"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 i2c7: i2c@11d02000 { 1310 compatible = "mediatek,mt8195-i2c", 1311 "mediatek,mt8192-i2c"; 1312 reg = <0 0x11d02000 0 0x1000>, 1313 <0 0x10220680 0 0x80>; 1314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1315 clock-div = <1>; 1316 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1317 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1318 clock-names = "main", "dma"; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 imp_iic_wrap_s: clock-controller@11d03000 { 1325 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1326 reg = <0 0x11d03000 0 0x1000>; 1327 #clock-cells = <1>; 1328 }; 1329 1330 i2c0: i2c@11e00000 { 1331 compatible = "mediatek,mt8195-i2c", 1332 "mediatek,mt8192-i2c"; 1333 reg = <0 0x11e00000 0 0x1000>, 1334 <0 0x10220080 0 0x80>; 1335 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1336 clock-div = <1>; 1337 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1338 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1339 clock-names = "main", "dma"; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 status = "disabled"; 1343 }; 1344 1345 i2c1: i2c@11e01000 { 1346 compatible = "mediatek,mt8195-i2c", 1347 "mediatek,mt8192-i2c"; 1348 reg = <0 0x11e01000 0 0x1000>, 1349 <0 0x10220200 0 0x80>; 1350 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1351 clock-div = <1>; 1352 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1353 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1354 clock-names = "main", "dma"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 i2c2: i2c@11e02000 { 1361 compatible = "mediatek,mt8195-i2c", 1362 "mediatek,mt8192-i2c"; 1363 reg = <0 0x11e02000 0 0x1000>, 1364 <0 0x10220380 0 0x80>; 1365 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1366 clock-div = <1>; 1367 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1368 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1369 clock-names = "main", "dma"; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 status = "disabled"; 1373 }; 1374 1375 i2c3: i2c@11e03000 { 1376 compatible = "mediatek,mt8195-i2c", 1377 "mediatek,mt8192-i2c"; 1378 reg = <0 0x11e03000 0 0x1000>, 1379 <0 0x10220480 0 0x80>; 1380 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1381 clock-div = <1>; 1382 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1383 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1384 clock-names = "main", "dma"; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 i2c4: i2c@11e04000 { 1391 compatible = "mediatek,mt8195-i2c", 1392 "mediatek,mt8192-i2c"; 1393 reg = <0 0x11e04000 0 0x1000>, 1394 <0 0x10220500 0 0x80>; 1395 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clock-div = <1>; 1397 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1398 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1399 clock-names = "main", "dma"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 imp_iic_wrap_w: clock-controller@11e05000 { 1406 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1407 reg = <0 0x11e05000 0 0x1000>; 1408 #clock-cells = <1>; 1409 }; 1410 1411 u3phy1: t-phy@11e30000 { 1412 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1413 #address-cells = <1>; 1414 #size-cells = <1>; 1415 ranges = <0 0 0x11e30000 0xe00>; 1416 status = "disabled"; 1417 1418 u2port1: usb-phy@0 { 1419 reg = <0x0 0x700>; 1420 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1421 <&clk26m>; 1422 clock-names = "ref", "da_ref"; 1423 #phy-cells = <1>; 1424 }; 1425 1426 u3port1: usb-phy@700 { 1427 reg = <0x700 0x700>; 1428 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1429 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1430 clock-names = "ref", "da_ref"; 1431 nvmem-cells = <&comb_intr_p1>, 1432 <&comb_rx_imp_p1>, 1433 <&comb_tx_imp_p1>; 1434 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1435 #phy-cells = <1>; 1436 }; 1437 }; 1438 1439 u3phy0: t-phy@11e40000 { 1440 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1441 #address-cells = <1>; 1442 #size-cells = <1>; 1443 ranges = <0 0 0x11e40000 0xe00>; 1444 status = "disabled"; 1445 1446 u2port0: usb-phy@0 { 1447 reg = <0x0 0x700>; 1448 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1449 <&clk26m>; 1450 clock-names = "ref", "da_ref"; 1451 #phy-cells = <1>; 1452 }; 1453 1454 u3port0: usb-phy@700 { 1455 reg = <0x700 0x700>; 1456 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1457 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1458 clock-names = "ref", "da_ref"; 1459 nvmem-cells = <&u3_intr_p0>, 1460 <&u3_rx_imp_p0>, 1461 <&u3_tx_imp_p0>; 1462 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1463 #phy-cells = <1>; 1464 }; 1465 }; 1466 1467 ufsphy: ufs-phy@11fa0000 { 1468 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1469 reg = <0 0x11fa0000 0 0xc000>; 1470 clocks = <&clk26m>, <&clk26m>; 1471 clock-names = "unipro", "mp"; 1472 #phy-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 mfgcfg: clock-controller@13fbf000 { 1477 compatible = "mediatek,mt8195-mfgcfg"; 1478 reg = <0 0x13fbf000 0 0x1000>; 1479 #clock-cells = <1>; 1480 }; 1481 1482 vppsys0: clock-controller@14000000 { 1483 compatible = "mediatek,mt8195-vppsys0"; 1484 reg = <0 0x14000000 0 0x1000>; 1485 #clock-cells = <1>; 1486 }; 1487 1488 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1489 compatible = "mediatek,mt8195-smi-sub-common"; 1490 reg = <0 0x14010000 0 0x1000>; 1491 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1492 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1493 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1494 clock-names = "apb", "smi", "gals0"; 1495 mediatek,smi = <&smi_common_vpp>; 1496 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1497 }; 1498 1499 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1500 compatible = "mediatek,mt8195-smi-sub-common"; 1501 reg = <0 0x14011000 0 0x1000>; 1502 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1503 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1504 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1505 clock-names = "apb", "smi", "gals0"; 1506 mediatek,smi = <&smi_common_vpp>; 1507 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1508 }; 1509 1510 smi_common_vpp: smi@14012000 { 1511 compatible = "mediatek,mt8195-smi-common-vpp"; 1512 reg = <0 0x14012000 0 0x1000>; 1513 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1514 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1515 <&vppsys0 CLK_VPP0_SMI_RSI>, 1516 <&vppsys0 CLK_VPP0_SMI_RSI>; 1517 clock-names = "apb", "smi", "gals0", "gals1"; 1518 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1519 }; 1520 1521 larb4: larb@14013000 { 1522 compatible = "mediatek,mt8195-smi-larb"; 1523 reg = <0 0x14013000 0 0x1000>; 1524 mediatek,larb-id = <4>; 1525 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1526 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1527 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1528 clock-names = "apb", "smi"; 1529 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1530 }; 1531 1532 iommu_vpp: iommu@14018000 { 1533 compatible = "mediatek,mt8195-iommu-vpp"; 1534 reg = <0 0x14018000 0 0x1000>; 1535 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1536 &larb12 &larb14 &larb16 &larb18 1537 &larb20 &larb22 &larb23 &larb26 1538 &larb27>; 1539 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1540 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1541 clock-names = "bclk"; 1542 #iommu-cells = <1>; 1543 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1544 }; 1545 1546 wpesys: clock-controller@14e00000 { 1547 compatible = "mediatek,mt8195-wpesys"; 1548 reg = <0 0x14e00000 0 0x1000>; 1549 #clock-cells = <1>; 1550 }; 1551 1552 wpesys_vpp0: clock-controller@14e02000 { 1553 compatible = "mediatek,mt8195-wpesys_vpp0"; 1554 reg = <0 0x14e02000 0 0x1000>; 1555 #clock-cells = <1>; 1556 }; 1557 1558 wpesys_vpp1: clock-controller@14e03000 { 1559 compatible = "mediatek,mt8195-wpesys_vpp1"; 1560 reg = <0 0x14e03000 0 0x1000>; 1561 #clock-cells = <1>; 1562 }; 1563 1564 larb7: larb@14e04000 { 1565 compatible = "mediatek,mt8195-smi-larb"; 1566 reg = <0 0x14e04000 0 0x1000>; 1567 mediatek,larb-id = <7>; 1568 mediatek,smi = <&smi_common_vdo>; 1569 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1570 <&wpesys CLK_WPE_SMI_LARB7>; 1571 clock-names = "apb", "smi"; 1572 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1573 }; 1574 1575 larb8: larb@14e05000 { 1576 compatible = "mediatek,mt8195-smi-larb"; 1577 reg = <0 0x14e05000 0 0x1000>; 1578 mediatek,larb-id = <8>; 1579 mediatek,smi = <&smi_common_vpp>; 1580 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1581 <&wpesys CLK_WPE_SMI_LARB8>, 1582 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1583 clock-names = "apb", "smi", "gals"; 1584 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1585 }; 1586 1587 vppsys1: clock-controller@14f00000 { 1588 compatible = "mediatek,mt8195-vppsys1"; 1589 reg = <0 0x14f00000 0 0x1000>; 1590 #clock-cells = <1>; 1591 }; 1592 1593 larb5: larb@14f02000 { 1594 compatible = "mediatek,mt8195-smi-larb"; 1595 reg = <0 0x14f02000 0 0x1000>; 1596 mediatek,larb-id = <5>; 1597 mediatek,smi = <&smi_common_vdo>; 1598 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1599 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1600 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1601 clock-names = "apb", "smi", "gals"; 1602 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1603 }; 1604 1605 larb6: larb@14f03000 { 1606 compatible = "mediatek,mt8195-smi-larb"; 1607 reg = <0 0x14f03000 0 0x1000>; 1608 mediatek,larb-id = <6>; 1609 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1610 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1611 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1612 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1613 clock-names = "apb", "smi", "gals"; 1614 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1615 }; 1616 1617 imgsys: clock-controller@15000000 { 1618 compatible = "mediatek,mt8195-imgsys"; 1619 reg = <0 0x15000000 0 0x1000>; 1620 #clock-cells = <1>; 1621 }; 1622 1623 larb9: larb@15001000 { 1624 compatible = "mediatek,mt8195-smi-larb"; 1625 reg = <0 0x15001000 0 0x1000>; 1626 mediatek,larb-id = <9>; 1627 mediatek,smi = <&smi_sub_common_img1_3x1>; 1628 clocks = <&imgsys CLK_IMG_LARB9>, 1629 <&imgsys CLK_IMG_LARB9>, 1630 <&imgsys CLK_IMG_GALS>; 1631 clock-names = "apb", "smi", "gals"; 1632 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1633 }; 1634 1635 smi_sub_common_img0_3x1: smi@15002000 { 1636 compatible = "mediatek,mt8195-smi-sub-common"; 1637 reg = <0 0x15002000 0 0x1000>; 1638 clocks = <&imgsys CLK_IMG_IPE>, 1639 <&imgsys CLK_IMG_IPE>, 1640 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1641 clock-names = "apb", "smi", "gals0"; 1642 mediatek,smi = <&smi_common_vpp>; 1643 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1644 }; 1645 1646 smi_sub_common_img1_3x1: smi@15003000 { 1647 compatible = "mediatek,mt8195-smi-sub-common"; 1648 reg = <0 0x15003000 0 0x1000>; 1649 clocks = <&imgsys CLK_IMG_LARB9>, 1650 <&imgsys CLK_IMG_LARB9>, 1651 <&imgsys CLK_IMG_GALS>; 1652 clock-names = "apb", "smi", "gals0"; 1653 mediatek,smi = <&smi_common_vdo>; 1654 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1655 }; 1656 1657 imgsys1_dip_top: clock-controller@15110000 { 1658 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1659 reg = <0 0x15110000 0 0x1000>; 1660 #clock-cells = <1>; 1661 }; 1662 1663 larb10: larb@15120000 { 1664 compatible = "mediatek,mt8195-smi-larb"; 1665 reg = <0 0x15120000 0 0x1000>; 1666 mediatek,larb-id = <10>; 1667 mediatek,smi = <&smi_sub_common_img1_3x1>; 1668 clocks = <&imgsys CLK_IMG_DIP0>, 1669 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1670 clock-names = "apb", "smi"; 1671 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1672 }; 1673 1674 imgsys1_dip_nr: clock-controller@15130000 { 1675 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1676 reg = <0 0x15130000 0 0x1000>; 1677 #clock-cells = <1>; 1678 }; 1679 1680 imgsys1_wpe: clock-controller@15220000 { 1681 compatible = "mediatek,mt8195-imgsys1_wpe"; 1682 reg = <0 0x15220000 0 0x1000>; 1683 #clock-cells = <1>; 1684 }; 1685 1686 larb11: larb@15230000 { 1687 compatible = "mediatek,mt8195-smi-larb"; 1688 reg = <0 0x15230000 0 0x1000>; 1689 mediatek,larb-id = <11>; 1690 mediatek,smi = <&smi_sub_common_img1_3x1>; 1691 clocks = <&imgsys CLK_IMG_WPE0>, 1692 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 1693 clock-names = "apb", "smi"; 1694 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1695 }; 1696 1697 ipesys: clock-controller@15330000 { 1698 compatible = "mediatek,mt8195-ipesys"; 1699 reg = <0 0x15330000 0 0x1000>; 1700 #clock-cells = <1>; 1701 }; 1702 1703 larb12: larb@15340000 { 1704 compatible = "mediatek,mt8195-smi-larb"; 1705 reg = <0 0x15340000 0 0x1000>; 1706 mediatek,larb-id = <12>; 1707 mediatek,smi = <&smi_sub_common_img0_3x1>; 1708 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 1709 <&ipesys CLK_IPE_SMI_LARB12>; 1710 clock-names = "apb", "smi"; 1711 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 1712 }; 1713 1714 camsys: clock-controller@16000000 { 1715 compatible = "mediatek,mt8195-camsys"; 1716 reg = <0 0x16000000 0 0x1000>; 1717 #clock-cells = <1>; 1718 }; 1719 1720 larb13: larb@16001000 { 1721 compatible = "mediatek,mt8195-smi-larb"; 1722 reg = <0 0x16001000 0 0x1000>; 1723 mediatek,larb-id = <13>; 1724 mediatek,smi = <&smi_sub_common_cam_4x1>; 1725 clocks = <&camsys CLK_CAM_LARB13>, 1726 <&camsys CLK_CAM_LARB13>, 1727 <&camsys CLK_CAM_CAM2MM0_GALS>; 1728 clock-names = "apb", "smi", "gals"; 1729 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1730 }; 1731 1732 larb14: larb@16002000 { 1733 compatible = "mediatek,mt8195-smi-larb"; 1734 reg = <0 0x16002000 0 0x1000>; 1735 mediatek,larb-id = <14>; 1736 mediatek,smi = <&smi_sub_common_cam_7x1>; 1737 clocks = <&camsys CLK_CAM_LARB14>, 1738 <&camsys CLK_CAM_LARB14>; 1739 clock-names = "apb", "smi"; 1740 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1741 }; 1742 1743 smi_sub_common_cam_4x1: smi@16004000 { 1744 compatible = "mediatek,mt8195-smi-sub-common"; 1745 reg = <0 0x16004000 0 0x1000>; 1746 clocks = <&camsys CLK_CAM_LARB13>, 1747 <&camsys CLK_CAM_LARB13>, 1748 <&camsys CLK_CAM_CAM2MM0_GALS>; 1749 clock-names = "apb", "smi", "gals0"; 1750 mediatek,smi = <&smi_common_vdo>; 1751 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1752 }; 1753 1754 smi_sub_common_cam_7x1: smi@16005000 { 1755 compatible = "mediatek,mt8195-smi-sub-common"; 1756 reg = <0 0x16005000 0 0x1000>; 1757 clocks = <&camsys CLK_CAM_LARB14>, 1758 <&camsys CLK_CAM_CAM2MM1_GALS>, 1759 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1760 clock-names = "apb", "smi", "gals0"; 1761 mediatek,smi = <&smi_common_vpp>; 1762 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1763 }; 1764 1765 larb16: larb@16012000 { 1766 compatible = "mediatek,mt8195-smi-larb"; 1767 reg = <0 0x16012000 0 0x1000>; 1768 mediatek,larb-id = <16>; 1769 mediatek,smi = <&smi_sub_common_cam_7x1>; 1770 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1771 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1772 clock-names = "apb", "smi"; 1773 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1774 }; 1775 1776 larb17: larb@16013000 { 1777 compatible = "mediatek,mt8195-smi-larb"; 1778 reg = <0 0x16013000 0 0x1000>; 1779 mediatek,larb-id = <17>; 1780 mediatek,smi = <&smi_sub_common_cam_4x1>; 1781 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 1782 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1783 clock-names = "apb", "smi"; 1784 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1785 }; 1786 1787 larb27: larb@16014000 { 1788 compatible = "mediatek,mt8195-smi-larb"; 1789 reg = <0 0x16014000 0 0x1000>; 1790 mediatek,larb-id = <27>; 1791 mediatek,smi = <&smi_sub_common_cam_7x1>; 1792 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1793 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1794 clock-names = "apb", "smi"; 1795 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1796 }; 1797 1798 larb28: larb@16015000 { 1799 compatible = "mediatek,mt8195-smi-larb"; 1800 reg = <0 0x16015000 0 0x1000>; 1801 mediatek,larb-id = <28>; 1802 mediatek,smi = <&smi_sub_common_cam_4x1>; 1803 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 1804 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1805 clock-names = "apb", "smi"; 1806 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1807 }; 1808 1809 camsys_rawa: clock-controller@1604f000 { 1810 compatible = "mediatek,mt8195-camsys_rawa"; 1811 reg = <0 0x1604f000 0 0x1000>; 1812 #clock-cells = <1>; 1813 }; 1814 1815 camsys_yuva: clock-controller@1606f000 { 1816 compatible = "mediatek,mt8195-camsys_yuva"; 1817 reg = <0 0x1606f000 0 0x1000>; 1818 #clock-cells = <1>; 1819 }; 1820 1821 camsys_rawb: clock-controller@1608f000 { 1822 compatible = "mediatek,mt8195-camsys_rawb"; 1823 reg = <0 0x1608f000 0 0x1000>; 1824 #clock-cells = <1>; 1825 }; 1826 1827 camsys_yuvb: clock-controller@160af000 { 1828 compatible = "mediatek,mt8195-camsys_yuvb"; 1829 reg = <0 0x160af000 0 0x1000>; 1830 #clock-cells = <1>; 1831 }; 1832 1833 camsys_mraw: clock-controller@16140000 { 1834 compatible = "mediatek,mt8195-camsys_mraw"; 1835 reg = <0 0x16140000 0 0x1000>; 1836 #clock-cells = <1>; 1837 }; 1838 1839 larb25: larb@16141000 { 1840 compatible = "mediatek,mt8195-smi-larb"; 1841 reg = <0 0x16141000 0 0x1000>; 1842 mediatek,larb-id = <25>; 1843 mediatek,smi = <&smi_sub_common_cam_4x1>; 1844 clocks = <&camsys CLK_CAM_LARB13>, 1845 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 1846 <&camsys CLK_CAM_CAM2MM0_GALS>; 1847 clock-names = "apb", "smi", "gals"; 1848 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 1849 }; 1850 1851 larb26: larb@16142000 { 1852 compatible = "mediatek,mt8195-smi-larb"; 1853 reg = <0 0x16142000 0 0x1000>; 1854 mediatek,larb-id = <26>; 1855 mediatek,smi = <&smi_sub_common_cam_7x1>; 1856 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 1857 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 1858 clock-names = "apb", "smi"; 1859 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 1860 1861 }; 1862 1863 ccusys: clock-controller@17200000 { 1864 compatible = "mediatek,mt8195-ccusys"; 1865 reg = <0 0x17200000 0 0x1000>; 1866 #clock-cells = <1>; 1867 }; 1868 1869 larb18: larb@17201000 { 1870 compatible = "mediatek,mt8195-smi-larb"; 1871 reg = <0 0x17201000 0 0x1000>; 1872 mediatek,larb-id = <18>; 1873 mediatek,smi = <&smi_sub_common_cam_7x1>; 1874 clocks = <&ccusys CLK_CCU_LARB18>, 1875 <&ccusys CLK_CCU_LARB18>; 1876 clock-names = "apb", "smi"; 1877 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1878 }; 1879 1880 larb24: larb@1800d000 { 1881 compatible = "mediatek,mt8195-smi-larb"; 1882 reg = <0 0x1800d000 0 0x1000>; 1883 mediatek,larb-id = <24>; 1884 mediatek,smi = <&smi_common_vdo>; 1885 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1886 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1887 clock-names = "apb", "smi"; 1888 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 1889 }; 1890 1891 larb23: larb@1800e000 { 1892 compatible = "mediatek,mt8195-smi-larb"; 1893 reg = <0 0x1800e000 0 0x1000>; 1894 mediatek,larb-id = <23>; 1895 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 1896 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1897 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1898 clock-names = "apb", "smi"; 1899 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 1900 }; 1901 1902 vdecsys_soc: clock-controller@1800f000 { 1903 compatible = "mediatek,mt8195-vdecsys_soc"; 1904 reg = <0 0x1800f000 0 0x1000>; 1905 #clock-cells = <1>; 1906 }; 1907 1908 larb21: larb@1802e000 { 1909 compatible = "mediatek,mt8195-smi-larb"; 1910 reg = <0 0x1802e000 0 0x1000>; 1911 mediatek,larb-id = <21>; 1912 mediatek,smi = <&smi_common_vdo>; 1913 clocks = <&vdecsys CLK_VDEC_LARB1>, 1914 <&vdecsys CLK_VDEC_LARB1>; 1915 clock-names = "apb", "smi"; 1916 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 1917 }; 1918 1919 vdecsys: clock-controller@1802f000 { 1920 compatible = "mediatek,mt8195-vdecsys"; 1921 reg = <0 0x1802f000 0 0x1000>; 1922 #clock-cells = <1>; 1923 }; 1924 1925 larb22: larb@1803e000 { 1926 compatible = "mediatek,mt8195-smi-larb"; 1927 reg = <0 0x1803e000 0 0x1000>; 1928 mediatek,larb-id = <22>; 1929 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 1930 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1931 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 1932 clock-names = "apb", "smi"; 1933 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 1934 }; 1935 1936 vdecsys_core1: clock-controller@1803f000 { 1937 compatible = "mediatek,mt8195-vdecsys_core1"; 1938 reg = <0 0x1803f000 0 0x1000>; 1939 #clock-cells = <1>; 1940 }; 1941 1942 apusys_pll: clock-controller@190f3000 { 1943 compatible = "mediatek,mt8195-apusys_pll"; 1944 reg = <0 0x190f3000 0 0x1000>; 1945 #clock-cells = <1>; 1946 }; 1947 1948 vencsys: clock-controller@1a000000 { 1949 compatible = "mediatek,mt8195-vencsys"; 1950 reg = <0 0x1a000000 0 0x1000>; 1951 #clock-cells = <1>; 1952 }; 1953 1954 larb19: larb@1a010000 { 1955 compatible = "mediatek,mt8195-smi-larb"; 1956 reg = <0 0x1a010000 0 0x1000>; 1957 mediatek,larb-id = <19>; 1958 mediatek,smi = <&smi_common_vdo>; 1959 clocks = <&vencsys CLK_VENC_VENC>, 1960 <&vencsys CLK_VENC_GALS>; 1961 clock-names = "apb", "smi"; 1962 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 1963 }; 1964 1965 venc: video-codec@1a020000 { 1966 compatible = "mediatek,mt8195-vcodec-enc"; 1967 reg = <0 0x1a020000 0 0x10000>; 1968 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 1969 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 1970 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 1971 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 1972 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 1973 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 1974 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 1975 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 1976 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 1977 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 1978 mediatek,scp = <&scp>; 1979 clocks = <&vencsys CLK_VENC_VENC>; 1980 clock-names = "venc_sel"; 1981 assigned-clocks = <&topckgen CLK_TOP_VENC>; 1982 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1983 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 1984 #address-cells = <2>; 1985 #size-cells = <2>; 1986 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 1987 }; 1988 1989 vencsys_core1: clock-controller@1b000000 { 1990 compatible = "mediatek,mt8195-vencsys_core1"; 1991 reg = <0 0x1b000000 0 0x1000>; 1992 #clock-cells = <1>; 1993 }; 1994 1995 vdosys0: syscon@1c01a000 { 1996 compatible = "mediatek,mt8195-mmsys", "syscon"; 1997 reg = <0 0x1c01a000 0 0x1000>; 1998 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 1999 #clock-cells = <1>; 2000 }; 2001 2002 larb20: larb@1b010000 { 2003 compatible = "mediatek,mt8195-smi-larb"; 2004 reg = <0 0x1b010000 0 0x1000>; 2005 mediatek,larb-id = <20>; 2006 mediatek,smi = <&smi_common_vpp>; 2007 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2008 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2009 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2010 clock-names = "apb", "smi", "gals"; 2011 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2012 }; 2013 2014 ovl0: ovl@1c000000 { 2015 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2016 reg = <0 0x1c000000 0 0x1000>; 2017 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2018 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2019 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2020 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2021 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2022 }; 2023 2024 rdma0: rdma@1c002000 { 2025 compatible = "mediatek,mt8195-disp-rdma"; 2026 reg = <0 0x1c002000 0 0x1000>; 2027 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2028 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2029 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2030 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2031 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2032 }; 2033 2034 color0: color@1c003000 { 2035 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2036 reg = <0 0x1c003000 0 0x1000>; 2037 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2038 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2039 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2040 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2041 }; 2042 2043 ccorr0: ccorr@1c004000 { 2044 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2045 reg = <0 0x1c004000 0 0x1000>; 2046 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2047 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2048 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2049 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2050 }; 2051 2052 aal0: aal@1c005000 { 2053 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2054 reg = <0 0x1c005000 0 0x1000>; 2055 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2056 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2057 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2058 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2059 }; 2060 2061 gamma0: gamma@1c006000 { 2062 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2063 reg = <0 0x1c006000 0 0x1000>; 2064 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2065 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2066 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2067 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2068 }; 2069 2070 dither0: dither@1c007000 { 2071 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2072 reg = <0 0x1c007000 0 0x1000>; 2073 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2074 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2075 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2076 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2077 }; 2078 2079 dsc0: dsc@1c009000 { 2080 compatible = "mediatek,mt8195-disp-dsc"; 2081 reg = <0 0x1c009000 0 0x1000>; 2082 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2083 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2084 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2085 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2086 }; 2087 2088 merge0: merge@1c014000 { 2089 compatible = "mediatek,mt8195-disp-merge"; 2090 reg = <0 0x1c014000 0 0x1000>; 2091 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2092 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2093 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2094 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2095 }; 2096 2097 mutex: mutex@1c016000 { 2098 compatible = "mediatek,mt8195-disp-mutex"; 2099 reg = <0 0x1c016000 0 0x1000>; 2100 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2101 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2102 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2103 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2104 }; 2105 2106 larb0: larb@1c018000 { 2107 compatible = "mediatek,mt8195-smi-larb"; 2108 reg = <0 0x1c018000 0 0x1000>; 2109 mediatek,larb-id = <0>; 2110 mediatek,smi = <&smi_common_vdo>; 2111 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2112 <&vdosys0 CLK_VDO0_SMI_LARB>, 2113 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2114 clock-names = "apb", "smi", "gals"; 2115 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2116 }; 2117 2118 larb1: larb@1c019000 { 2119 compatible = "mediatek,mt8195-smi-larb"; 2120 reg = <0 0x1c019000 0 0x1000>; 2121 mediatek,larb-id = <1>; 2122 mediatek,smi = <&smi_common_vpp>; 2123 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2124 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2125 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2126 clock-names = "apb", "smi", "gals"; 2127 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2128 }; 2129 2130 vdosys1: syscon@1c100000 { 2131 compatible = "mediatek,mt8195-mmsys", "syscon"; 2132 reg = <0 0x1c100000 0 0x1000>; 2133 #clock-cells = <1>; 2134 }; 2135 2136 smi_common_vdo: smi@1c01b000 { 2137 compatible = "mediatek,mt8195-smi-common-vdo"; 2138 reg = <0 0x1c01b000 0 0x1000>; 2139 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2140 <&vdosys0 CLK_VDO0_SMI_EMI>, 2141 <&vdosys0 CLK_VDO0_SMI_RSI>, 2142 <&vdosys0 CLK_VDO0_SMI_GALS>; 2143 clock-names = "apb", "smi", "gals0", "gals1"; 2144 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2145 2146 }; 2147 2148 iommu_vdo: iommu@1c01f000 { 2149 compatible = "mediatek,mt8195-iommu-vdo"; 2150 reg = <0 0x1c01f000 0 0x1000>; 2151 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2152 &larb10 &larb11 &larb13 &larb17 2153 &larb19 &larb21 &larb24 &larb25 2154 &larb28>; 2155 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2156 #iommu-cells = <1>; 2157 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2158 clock-names = "bclk"; 2159 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2160 }; 2161 2162 larb2: larb@1c102000 { 2163 compatible = "mediatek,mt8195-smi-larb"; 2164 reg = <0 0x1c102000 0 0x1000>; 2165 mediatek,larb-id = <2>; 2166 mediatek,smi = <&smi_common_vdo>; 2167 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2168 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2169 <&vdosys1 CLK_VDO1_GALS>; 2170 clock-names = "apb", "smi", "gals"; 2171 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2172 }; 2173 2174 larb3: larb@1c103000 { 2175 compatible = "mediatek,mt8195-smi-larb"; 2176 reg = <0 0x1c103000 0 0x1000>; 2177 mediatek,larb-id = <3>; 2178 mediatek,smi = <&smi_common_vpp>; 2179 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2180 <&vdosys1 CLK_VDO1_GALS>, 2181 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2182 clock-names = "apb", "smi", "gals"; 2183 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2184 }; 2185 }; 2186}; 2187