1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17 18/ { 19 compatible = "mediatek,mt8195"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 gce0 = &gce0; 26 gce1 = &gce1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x000>; 37 enable-method = "psci"; 38 performance-domains = <&performance 0>; 39 clock-frequency = <1701000000>; 40 capacity-dmips-mhz = <578>; 41 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 42 next-level-cache = <&l2_0>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@100 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x100>; 50 enable-method = "psci"; 51 performance-domains = <&performance 0>; 52 clock-frequency = <1701000000>; 53 capacity-dmips-mhz = <578>; 54 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 55 next-level-cache = <&l2_0>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@200 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x200>; 63 enable-method = "psci"; 64 performance-domains = <&performance 0>; 65 clock-frequency = <1701000000>; 66 capacity-dmips-mhz = <578>; 67 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu3: cpu@300 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x300>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <578>; 80 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 81 next-level-cache = <&l2_0>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu4: cpu@400 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a78"; 88 reg = <0x400>; 89 enable-method = "psci"; 90 performance-domains = <&performance 1>; 91 clock-frequency = <2171000000>; 92 capacity-dmips-mhz = <1024>; 93 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 94 next-level-cache = <&l2_1>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu5: cpu@500 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78"; 101 reg = <0x500>; 102 enable-method = "psci"; 103 performance-domains = <&performance 1>; 104 clock-frequency = <2171000000>; 105 capacity-dmips-mhz = <1024>; 106 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 107 next-level-cache = <&l2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu6: cpu@600 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a78"; 114 reg = <0x600>; 115 enable-method = "psci"; 116 performance-domains = <&performance 1>; 117 clock-frequency = <2171000000>; 118 capacity-dmips-mhz = <1024>; 119 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 120 next-level-cache = <&l2_1>; 121 #cooling-cells = <2>; 122 }; 123 124 cpu7: cpu@700 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a78"; 127 reg = <0x700>; 128 enable-method = "psci"; 129 performance-domains = <&performance 1>; 130 clock-frequency = <2171000000>; 131 capacity-dmips-mhz = <1024>; 132 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 133 next-level-cache = <&l2_1>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu-map { 138 cluster0 { 139 core0 { 140 cpu = <&cpu0>; 141 }; 142 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 147 core2 { 148 cpu = <&cpu2>; 149 }; 150 151 core3 { 152 cpu = <&cpu3>; 153 }; 154 }; 155 156 cluster1 { 157 core0 { 158 cpu = <&cpu4>; 159 }; 160 161 core1 { 162 cpu = <&cpu5>; 163 }; 164 165 core2 { 166 cpu = <&cpu6>; 167 }; 168 169 core3 { 170 cpu = <&cpu7>; 171 }; 172 }; 173 }; 174 175 idle-states { 176 entry-method = "psci"; 177 178 cpu_off_l: cpu-off-l { 179 compatible = "arm,idle-state"; 180 arm,psci-suspend-param = <0x00010001>; 181 local-timer-stop; 182 entry-latency-us = <50>; 183 exit-latency-us = <95>; 184 min-residency-us = <580>; 185 }; 186 187 cpu_off_b: cpu-off-b { 188 compatible = "arm,idle-state"; 189 arm,psci-suspend-param = <0x00010001>; 190 local-timer-stop; 191 entry-latency-us = <45>; 192 exit-latency-us = <140>; 193 min-residency-us = <740>; 194 }; 195 196 cluster_off_l: cluster-off-l { 197 compatible = "arm,idle-state"; 198 arm,psci-suspend-param = <0x01010002>; 199 local-timer-stop; 200 entry-latency-us = <55>; 201 exit-latency-us = <155>; 202 min-residency-us = <840>; 203 }; 204 205 cluster_off_b: cluster-off-b { 206 compatible = "arm,idle-state"; 207 arm,psci-suspend-param = <0x01010002>; 208 local-timer-stop; 209 entry-latency-us = <50>; 210 exit-latency-us = <200>; 211 min-residency-us = <1000>; 212 }; 213 }; 214 215 l2_0: l2-cache0 { 216 compatible = "cache"; 217 cache-level = <2>; 218 next-level-cache = <&l3_0>; 219 }; 220 221 l2_1: l2-cache1 { 222 compatible = "cache"; 223 cache-level = <2>; 224 next-level-cache = <&l3_0>; 225 }; 226 227 l3_0: l3-cache { 228 compatible = "cache"; 229 cache-level = <3>; 230 }; 231 }; 232 233 dsu-pmu { 234 compatible = "arm,dsu-pmu"; 235 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 236 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 237 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 238 }; 239 240 dmic_codec: dmic-codec { 241 compatible = "dmic-codec"; 242 num-channels = <2>; 243 wakeup-delay-ms = <50>; 244 }; 245 246 sound: mt8195-sound { 247 mediatek,platform = <&afe>; 248 status = "disabled"; 249 }; 250 251 clk26m: oscillator-26m { 252 compatible = "fixed-clock"; 253 #clock-cells = <0>; 254 clock-frequency = <26000000>; 255 clock-output-names = "clk26m"; 256 }; 257 258 clk32k: oscillator-32k { 259 compatible = "fixed-clock"; 260 #clock-cells = <0>; 261 clock-frequency = <32768>; 262 clock-output-names = "clk32k"; 263 }; 264 265 performance: performance-controller@11bc10 { 266 compatible = "mediatek,cpufreq-hw"; 267 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 268 #performance-domain-cells = <1>; 269 }; 270 271 pmu-a55 { 272 compatible = "arm,cortex-a55-pmu"; 273 interrupt-parent = <&gic>; 274 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 275 }; 276 277 pmu-a78 { 278 compatible = "arm,cortex-a78-pmu"; 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 281 }; 282 283 psci { 284 compatible = "arm,psci-1.0"; 285 method = "smc"; 286 }; 287 288 timer: timer { 289 compatible = "arm,armv8-timer"; 290 interrupt-parent = <&gic>; 291 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 292 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 293 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 294 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 295 }; 296 297 soc { 298 #address-cells = <2>; 299 #size-cells = <2>; 300 compatible = "simple-bus"; 301 ranges; 302 303 gic: interrupt-controller@c000000 { 304 compatible = "arm,gic-v3"; 305 #interrupt-cells = <4>; 306 #redistributor-regions = <1>; 307 interrupt-parent = <&gic>; 308 interrupt-controller; 309 reg = <0 0x0c000000 0 0x40000>, 310 <0 0x0c040000 0 0x200000>; 311 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 312 313 ppi-partitions { 314 ppi_cluster0: interrupt-partition-0 { 315 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 316 }; 317 318 ppi_cluster1: interrupt-partition-1 { 319 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 320 }; 321 }; 322 }; 323 324 topckgen: syscon@10000000 { 325 compatible = "mediatek,mt8195-topckgen", "syscon"; 326 reg = <0 0x10000000 0 0x1000>; 327 #clock-cells = <1>; 328 }; 329 330 infracfg_ao: syscon@10001000 { 331 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 332 reg = <0 0x10001000 0 0x1000>; 333 #clock-cells = <1>; 334 #reset-cells = <1>; 335 }; 336 337 pericfg: syscon@10003000 { 338 compatible = "mediatek,mt8195-pericfg", "syscon"; 339 reg = <0 0x10003000 0 0x1000>; 340 #clock-cells = <1>; 341 }; 342 343 pio: pinctrl@10005000 { 344 compatible = "mediatek,mt8195-pinctrl"; 345 reg = <0 0x10005000 0 0x1000>, 346 <0 0x11d10000 0 0x1000>, 347 <0 0x11d30000 0 0x1000>, 348 <0 0x11d40000 0 0x1000>, 349 <0 0x11e20000 0 0x1000>, 350 <0 0x11eb0000 0 0x1000>, 351 <0 0x11f40000 0 0x1000>, 352 <0 0x1000b000 0 0x1000>; 353 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 354 "iocfg_br", "iocfg_lm", "iocfg_rb", 355 "iocfg_tl", "eint"; 356 gpio-controller; 357 #gpio-cells = <2>; 358 gpio-ranges = <&pio 0 0 144>; 359 interrupt-controller; 360 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 361 #interrupt-cells = <2>; 362 }; 363 364 scpsys: syscon@10006000 { 365 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 366 reg = <0 0x10006000 0 0x1000>; 367 368 /* System Power Manager */ 369 spm: power-controller { 370 compatible = "mediatek,mt8195-power-controller"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 #power-domain-cells = <1>; 374 375 /* power domain of the SoC */ 376 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 377 reg = <MT8195_POWER_DOMAIN_MFG0>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 #power-domain-cells = <1>; 381 382 power-domain@MT8195_POWER_DOMAIN_MFG1 { 383 reg = <MT8195_POWER_DOMAIN_MFG1>; 384 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 385 clock-names = "mfg"; 386 mediatek,infracfg = <&infracfg_ao>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 #power-domain-cells = <1>; 390 391 power-domain@MT8195_POWER_DOMAIN_MFG2 { 392 reg = <MT8195_POWER_DOMAIN_MFG2>; 393 #power-domain-cells = <0>; 394 }; 395 396 power-domain@MT8195_POWER_DOMAIN_MFG3 { 397 reg = <MT8195_POWER_DOMAIN_MFG3>; 398 #power-domain-cells = <0>; 399 }; 400 401 power-domain@MT8195_POWER_DOMAIN_MFG4 { 402 reg = <MT8195_POWER_DOMAIN_MFG4>; 403 #power-domain-cells = <0>; 404 }; 405 406 power-domain@MT8195_POWER_DOMAIN_MFG5 { 407 reg = <MT8195_POWER_DOMAIN_MFG5>; 408 #power-domain-cells = <0>; 409 }; 410 411 power-domain@MT8195_POWER_DOMAIN_MFG6 { 412 reg = <MT8195_POWER_DOMAIN_MFG6>; 413 #power-domain-cells = <0>; 414 }; 415 }; 416 }; 417 418 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 419 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 420 clocks = <&topckgen CLK_TOP_VPP>, 421 <&topckgen CLK_TOP_CAM>, 422 <&topckgen CLK_TOP_CCU>, 423 <&topckgen CLK_TOP_IMG>, 424 <&topckgen CLK_TOP_VENC>, 425 <&topckgen CLK_TOP_VDEC>, 426 <&topckgen CLK_TOP_WPE_VPP>, 427 <&topckgen CLK_TOP_CFG_VPP0>, 428 <&vppsys0 CLK_VPP0_SMI_COMMON>, 429 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 430 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 431 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 432 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 433 <&vppsys0 CLK_VPP0_GALS_INFRA>, 434 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 435 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 436 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 437 <&vppsys0 CLK_VPP0_SMI_REORDER>, 438 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 439 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 440 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 441 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 442 <&vppsys0 CLK_VPP0_SMI_RSI>, 443 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 444 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 445 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 446 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 447 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 448 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 449 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 450 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 451 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 452 "vppsys0-12", "vppsys0-13", "vppsys0-14", 453 "vppsys0-15", "vppsys0-16", "vppsys0-17", 454 "vppsys0-18"; 455 mediatek,infracfg = <&infracfg_ao>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 #power-domain-cells = <1>; 459 460 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 461 reg = <MT8195_POWER_DOMAIN_VDEC1>; 462 clocks = <&vdecsys CLK_VDEC_LARB1>; 463 clock-names = "vdec1-0"; 464 mediatek,infracfg = <&infracfg_ao>; 465 #power-domain-cells = <0>; 466 }; 467 468 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 469 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 470 mediatek,infracfg = <&infracfg_ao>; 471 #power-domain-cells = <0>; 472 }; 473 474 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 475 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 476 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 477 <&vdosys0 CLK_VDO0_SMI_GALS>, 478 <&vdosys0 CLK_VDO0_SMI_COMMON>, 479 <&vdosys0 CLK_VDO0_SMI_EMI>, 480 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 481 <&vdosys0 CLK_VDO0_SMI_LARB>, 482 <&vdosys0 CLK_VDO0_SMI_RSI>; 483 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 484 "vdosys0-2", "vdosys0-3", 485 "vdosys0-4", "vdosys0-5"; 486 mediatek,infracfg = <&infracfg_ao>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 #power-domain-cells = <1>; 490 491 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 492 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 493 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 494 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 495 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 496 clock-names = "vppsys1", "vppsys1-0", 497 "vppsys1-1"; 498 mediatek,infracfg = <&infracfg_ao>; 499 #power-domain-cells = <0>; 500 }; 501 502 power-domain@MT8195_POWER_DOMAIN_WPESYS { 503 reg = <MT8195_POWER_DOMAIN_WPESYS>; 504 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 505 <&wpesys CLK_WPE_SMI_LARB8>, 506 <&wpesys CLK_WPE_SMI_LARB7_P>, 507 <&wpesys CLK_WPE_SMI_LARB8_P>; 508 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 509 "wepsys-3"; 510 mediatek,infracfg = <&infracfg_ao>; 511 #power-domain-cells = <0>; 512 }; 513 514 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 515 reg = <MT8195_POWER_DOMAIN_VDEC0>; 516 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 517 clock-names = "vdec0-0"; 518 mediatek,infracfg = <&infracfg_ao>; 519 #power-domain-cells = <0>; 520 }; 521 522 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 523 reg = <MT8195_POWER_DOMAIN_VDEC2>; 524 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 525 clock-names = "vdec2-0"; 526 mediatek,infracfg = <&infracfg_ao>; 527 #power-domain-cells = <0>; 528 }; 529 530 power-domain@MT8195_POWER_DOMAIN_VENC { 531 reg = <MT8195_POWER_DOMAIN_VENC>; 532 mediatek,infracfg = <&infracfg_ao>; 533 #power-domain-cells = <0>; 534 }; 535 536 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 537 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 538 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 539 <&vdosys1 CLK_VDO1_SMI_LARB2>, 540 <&vdosys1 CLK_VDO1_SMI_LARB3>, 541 <&vdosys1 CLK_VDO1_GALS>; 542 clock-names = "vdosys1", "vdosys1-0", 543 "vdosys1-1", "vdosys1-2"; 544 mediatek,infracfg = <&infracfg_ao>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 #power-domain-cells = <1>; 548 549 power-domain@MT8195_POWER_DOMAIN_DP_TX { 550 reg = <MT8195_POWER_DOMAIN_DP_TX>; 551 mediatek,infracfg = <&infracfg_ao>; 552 #power-domain-cells = <0>; 553 }; 554 555 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 556 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 557 mediatek,infracfg = <&infracfg_ao>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 562 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 563 clocks = <&topckgen CLK_TOP_HDMI_APB>; 564 clock-names = "hdmi_tx"; 565 #power-domain-cells = <0>; 566 }; 567 }; 568 569 power-domain@MT8195_POWER_DOMAIN_IMG { 570 reg = <MT8195_POWER_DOMAIN_IMG>; 571 clocks = <&imgsys CLK_IMG_LARB9>, 572 <&imgsys CLK_IMG_GALS>; 573 clock-names = "img-0", "img-1"; 574 mediatek,infracfg = <&infracfg_ao>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 #power-domain-cells = <1>; 578 579 power-domain@MT8195_POWER_DOMAIN_DIP { 580 reg = <MT8195_POWER_DOMAIN_DIP>; 581 #power-domain-cells = <0>; 582 }; 583 584 power-domain@MT8195_POWER_DOMAIN_IPE { 585 reg = <MT8195_POWER_DOMAIN_IPE>; 586 clocks = <&topckgen CLK_TOP_IPE>, 587 <&imgsys CLK_IMG_IPE>, 588 <&ipesys CLK_IPE_SMI_LARB12>; 589 clock-names = "ipe", "ipe-0", "ipe-1"; 590 mediatek,infracfg = <&infracfg_ao>; 591 #power-domain-cells = <0>; 592 }; 593 }; 594 595 power-domain@MT8195_POWER_DOMAIN_CAM { 596 reg = <MT8195_POWER_DOMAIN_CAM>; 597 clocks = <&camsys CLK_CAM_LARB13>, 598 <&camsys CLK_CAM_LARB14>, 599 <&camsys CLK_CAM_CAM2MM0_GALS>, 600 <&camsys CLK_CAM_CAM2MM1_GALS>, 601 <&camsys CLK_CAM_CAM2SYS_GALS>; 602 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 603 "cam-4"; 604 mediatek,infracfg = <&infracfg_ao>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 #power-domain-cells = <1>; 608 609 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 610 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 611 #power-domain-cells = <0>; 612 }; 613 614 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 615 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 616 #power-domain-cells = <0>; 617 }; 618 619 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 620 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 621 #power-domain-cells = <0>; 622 }; 623 }; 624 }; 625 }; 626 627 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 628 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 629 mediatek,infracfg = <&infracfg_ao>; 630 #power-domain-cells = <0>; 631 }; 632 633 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 634 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 635 mediatek,infracfg = <&infracfg_ao>; 636 #power-domain-cells = <0>; 637 }; 638 639 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 640 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 641 #power-domain-cells = <0>; 642 }; 643 644 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 645 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 646 #power-domain-cells = <0>; 647 }; 648 649 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 650 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 651 clocks = <&topckgen CLK_TOP_SENINF>, 652 <&topckgen CLK_TOP_SENINF2>; 653 clock-names = "csi_rx_top", "csi_rx_top1"; 654 #power-domain-cells = <0>; 655 }; 656 657 power-domain@MT8195_POWER_DOMAIN_ETHER { 658 reg = <MT8195_POWER_DOMAIN_ETHER>; 659 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 660 clock-names = "ether"; 661 #power-domain-cells = <0>; 662 }; 663 664 power-domain@MT8195_POWER_DOMAIN_ADSP { 665 reg = <MT8195_POWER_DOMAIN_ADSP>; 666 clocks = <&topckgen CLK_TOP_ADSP>, 667 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 668 clock-names = "adsp", "adsp1"; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 mediatek,infracfg = <&infracfg_ao>; 672 #power-domain-cells = <1>; 673 674 power-domain@MT8195_POWER_DOMAIN_AUDIO { 675 reg = <MT8195_POWER_DOMAIN_AUDIO>; 676 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 677 <&topckgen CLK_TOP_AUD_INTBUS>, 678 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 679 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 680 clock-names = "audio", "audio1", "audio2", 681 "audio3"; 682 mediatek,infracfg = <&infracfg_ao>; 683 #power-domain-cells = <0>; 684 }; 685 }; 686 }; 687 }; 688 689 watchdog: watchdog@10007000 { 690 compatible = "mediatek,mt8195-wdt", 691 "mediatek,mt6589-wdt"; 692 mediatek,disable-extrst; 693 reg = <0 0x10007000 0 0x100>; 694 #reset-cells = <1>; 695 }; 696 697 apmixedsys: syscon@1000c000 { 698 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 699 reg = <0 0x1000c000 0 0x1000>; 700 #clock-cells = <1>; 701 }; 702 703 systimer: timer@10017000 { 704 compatible = "mediatek,mt8195-timer", 705 "mediatek,mt6765-timer"; 706 reg = <0 0x10017000 0 0x1000>; 707 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 708 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 709 }; 710 711 pwrap: pwrap@10024000 { 712 compatible = "mediatek,mt8195-pwrap", "syscon"; 713 reg = <0 0x10024000 0 0x1000>; 714 reg-names = "pwrap"; 715 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 716 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 717 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 718 clock-names = "spi", "wrap"; 719 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 720 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 721 }; 722 723 spmi: spmi@10027000 { 724 compatible = "mediatek,mt8195-spmi"; 725 reg = <0 0x10027000 0 0x000e00>, 726 <0 0x10029000 0 0x000100>; 727 reg-names = "pmif", "spmimst"; 728 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 729 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 730 <&topckgen CLK_TOP_SPMI_M_MST>; 731 clock-names = "pmif_sys_ck", 732 "pmif_tmr_ck", 733 "spmimst_clk_mux"; 734 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 735 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 736 }; 737 738 iommu_infra: infra-iommu@10315000 { 739 compatible = "mediatek,mt8195-iommu-infra"; 740 reg = <0 0x10315000 0 0x5000>; 741 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 742 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 743 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 744 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 745 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 746 #iommu-cells = <1>; 747 }; 748 749 gce0: mailbox@10320000 { 750 compatible = "mediatek,mt8195-gce"; 751 reg = <0 0x10320000 0 0x4000>; 752 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 753 #mbox-cells = <2>; 754 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 755 }; 756 757 gce1: mailbox@10330000 { 758 compatible = "mediatek,mt8195-gce"; 759 reg = <0 0x10330000 0 0x4000>; 760 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 761 #mbox-cells = <2>; 762 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 763 }; 764 765 scp: scp@10500000 { 766 compatible = "mediatek,mt8195-scp"; 767 reg = <0 0x10500000 0 0x100000>, 768 <0 0x10720000 0 0xe0000>, 769 <0 0x10700000 0 0x8000>; 770 reg-names = "sram", "cfg", "l1tcm"; 771 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 772 status = "disabled"; 773 }; 774 775 scp_adsp: clock-controller@10720000 { 776 compatible = "mediatek,mt8195-scp_adsp"; 777 reg = <0 0x10720000 0 0x1000>; 778 #clock-cells = <1>; 779 }; 780 781 adsp: dsp@10803000 { 782 compatible = "mediatek,mt8195-dsp"; 783 reg = <0 0x10803000 0 0x1000>, 784 <0 0x10840000 0 0x40000>; 785 reg-names = "cfg", "sram"; 786 clocks = <&topckgen CLK_TOP_ADSP>, 787 <&clk26m>, 788 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 789 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 790 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 791 <&topckgen CLK_TOP_AUDIO_H>; 792 clock-names = "adsp_sel", 793 "clk26m_ck", 794 "audio_local_bus", 795 "mainpll_d7_d2", 796 "scp_adsp_audiodsp", 797 "audio_h"; 798 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 799 mbox-names = "rx", "tx"; 800 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 801 status = "disabled"; 802 }; 803 804 adsp_mailbox0: mailbox@10816000 { 805 compatible = "mediatek,mt8195-adsp-mbox"; 806 #mbox-cells = <0>; 807 reg = <0 0x10816000 0 0x1000>; 808 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 809 }; 810 811 adsp_mailbox1: mailbox@10817000 { 812 compatible = "mediatek,mt8195-adsp-mbox"; 813 #mbox-cells = <0>; 814 reg = <0 0x10817000 0 0x1000>; 815 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 816 }; 817 818 afe: mt8195-afe-pcm@10890000 { 819 compatible = "mediatek,mt8195-audio"; 820 reg = <0 0x10890000 0 0x10000>; 821 mediatek,topckgen = <&topckgen>; 822 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 823 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 824 resets = <&watchdog 14>; 825 reset-names = "audiosys"; 826 clocks = <&clk26m>, 827 <&apmixedsys CLK_APMIXED_APLL1>, 828 <&apmixedsys CLK_APMIXED_APLL2>, 829 <&topckgen CLK_TOP_APLL12_DIV0>, 830 <&topckgen CLK_TOP_APLL12_DIV1>, 831 <&topckgen CLK_TOP_APLL12_DIV2>, 832 <&topckgen CLK_TOP_APLL12_DIV3>, 833 <&topckgen CLK_TOP_APLL12_DIV9>, 834 <&topckgen CLK_TOP_A1SYS_HP>, 835 <&topckgen CLK_TOP_AUD_INTBUS>, 836 <&topckgen CLK_TOP_AUDIO_H>, 837 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 838 <&topckgen CLK_TOP_DPTX_MCK>, 839 <&topckgen CLK_TOP_I2SO1_MCK>, 840 <&topckgen CLK_TOP_I2SO2_MCK>, 841 <&topckgen CLK_TOP_I2SI1_MCK>, 842 <&topckgen CLK_TOP_I2SI2_MCK>, 843 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 844 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 845 clock-names = "clk26m", 846 "apll1_ck", 847 "apll2_ck", 848 "apll12_div0", 849 "apll12_div1", 850 "apll12_div2", 851 "apll12_div3", 852 "apll12_div9", 853 "a1sys_hp_sel", 854 "aud_intbus_sel", 855 "audio_h_sel", 856 "audio_local_bus_sel", 857 "dptx_m_sel", 858 "i2so1_m_sel", 859 "i2so2_m_sel", 860 "i2si1_m_sel", 861 "i2si2_m_sel", 862 "infra_ao_audio_26m_b", 863 "scp_adsp_audiodsp"; 864 status = "disabled"; 865 }; 866 867 uart0: serial@11001100 { 868 compatible = "mediatek,mt8195-uart", 869 "mediatek,mt6577-uart"; 870 reg = <0 0x11001100 0 0x100>; 871 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 872 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 873 clock-names = "baud", "bus"; 874 status = "disabled"; 875 }; 876 877 uart1: serial@11001200 { 878 compatible = "mediatek,mt8195-uart", 879 "mediatek,mt6577-uart"; 880 reg = <0 0x11001200 0 0x100>; 881 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 882 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 883 clock-names = "baud", "bus"; 884 status = "disabled"; 885 }; 886 887 uart2: serial@11001300 { 888 compatible = "mediatek,mt8195-uart", 889 "mediatek,mt6577-uart"; 890 reg = <0 0x11001300 0 0x100>; 891 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 892 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 893 clock-names = "baud", "bus"; 894 status = "disabled"; 895 }; 896 897 uart3: serial@11001400 { 898 compatible = "mediatek,mt8195-uart", 899 "mediatek,mt6577-uart"; 900 reg = <0 0x11001400 0 0x100>; 901 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 902 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 903 clock-names = "baud", "bus"; 904 status = "disabled"; 905 }; 906 907 uart4: serial@11001500 { 908 compatible = "mediatek,mt8195-uart", 909 "mediatek,mt6577-uart"; 910 reg = <0 0x11001500 0 0x100>; 911 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 912 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 913 clock-names = "baud", "bus"; 914 status = "disabled"; 915 }; 916 917 uart5: serial@11001600 { 918 compatible = "mediatek,mt8195-uart", 919 "mediatek,mt6577-uart"; 920 reg = <0 0x11001600 0 0x100>; 921 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 922 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 923 clock-names = "baud", "bus"; 924 status = "disabled"; 925 }; 926 927 auxadc: auxadc@11002000 { 928 compatible = "mediatek,mt8195-auxadc", 929 "mediatek,mt8173-auxadc"; 930 reg = <0 0x11002000 0 0x1000>; 931 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 932 clock-names = "main"; 933 #io-channel-cells = <1>; 934 status = "disabled"; 935 }; 936 937 pericfg_ao: syscon@11003000 { 938 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 939 reg = <0 0x11003000 0 0x1000>; 940 #clock-cells = <1>; 941 }; 942 943 spi0: spi@1100a000 { 944 compatible = "mediatek,mt8195-spi", 945 "mediatek,mt6765-spi"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 reg = <0 0x1100a000 0 0x1000>; 949 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 950 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 951 <&topckgen CLK_TOP_SPI>, 952 <&infracfg_ao CLK_INFRA_AO_SPI0>; 953 clock-names = "parent-clk", "sel-clk", "spi-clk"; 954 status = "disabled"; 955 }; 956 957 spi1: spi@11010000 { 958 compatible = "mediatek,mt8195-spi", 959 "mediatek,mt6765-spi"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 reg = <0 0x11010000 0 0x1000>; 963 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 964 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 965 <&topckgen CLK_TOP_SPI>, 966 <&infracfg_ao CLK_INFRA_AO_SPI1>; 967 clock-names = "parent-clk", "sel-clk", "spi-clk"; 968 status = "disabled"; 969 }; 970 971 spi2: spi@11012000 { 972 compatible = "mediatek,mt8195-spi", 973 "mediatek,mt6765-spi"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 reg = <0 0x11012000 0 0x1000>; 977 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 978 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 979 <&topckgen CLK_TOP_SPI>, 980 <&infracfg_ao CLK_INFRA_AO_SPI2>; 981 clock-names = "parent-clk", "sel-clk", "spi-clk"; 982 status = "disabled"; 983 }; 984 985 spi3: spi@11013000 { 986 compatible = "mediatek,mt8195-spi", 987 "mediatek,mt6765-spi"; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 reg = <0 0x11013000 0 0x1000>; 991 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 992 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 993 <&topckgen CLK_TOP_SPI>, 994 <&infracfg_ao CLK_INFRA_AO_SPI3>; 995 clock-names = "parent-clk", "sel-clk", "spi-clk"; 996 status = "disabled"; 997 }; 998 999 spi4: spi@11018000 { 1000 compatible = "mediatek,mt8195-spi", 1001 "mediatek,mt6765-spi"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 reg = <0 0x11018000 0 0x1000>; 1005 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1006 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1007 <&topckgen CLK_TOP_SPI>, 1008 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1009 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1010 status = "disabled"; 1011 }; 1012 1013 spi5: spi@11019000 { 1014 compatible = "mediatek,mt8195-spi", 1015 "mediatek,mt6765-spi"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 reg = <0 0x11019000 0 0x1000>; 1019 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1020 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1021 <&topckgen CLK_TOP_SPI>, 1022 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1023 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1024 status = "disabled"; 1025 }; 1026 1027 spis0: spi@1101d000 { 1028 compatible = "mediatek,mt8195-spi-slave"; 1029 reg = <0 0x1101d000 0 0x1000>; 1030 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1032 clock-names = "spi"; 1033 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1034 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1035 status = "disabled"; 1036 }; 1037 1038 spis1: spi@1101e000 { 1039 compatible = "mediatek,mt8195-spi-slave"; 1040 reg = <0 0x1101e000 0 0x1000>; 1041 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1042 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1043 clock-names = "spi"; 1044 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1045 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1046 status = "disabled"; 1047 }; 1048 1049 xhci0: usb@11200000 { 1050 compatible = "mediatek,mt8195-xhci", 1051 "mediatek,mtk-xhci"; 1052 reg = <0 0x11200000 0 0x1000>, 1053 <0 0x11203e00 0 0x0100>; 1054 reg-names = "mac", "ippc"; 1055 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1056 phys = <&u2port0 PHY_TYPE_USB2>, 1057 <&u3port0 PHY_TYPE_USB3>; 1058 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1059 <&topckgen CLK_TOP_SSUSB_XHCI>; 1060 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1061 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1062 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1063 <&topckgen CLK_TOP_SSUSB_REF>, 1064 <&apmixedsys CLK_APMIXED_USB1PLL>, 1065 <&clk26m>, 1066 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1067 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1068 "xhci_ck"; 1069 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1070 wakeup-source; 1071 status = "disabled"; 1072 }; 1073 1074 mmc0: mmc@11230000 { 1075 compatible = "mediatek,mt8195-mmc", 1076 "mediatek,mt8183-mmc"; 1077 reg = <0 0x11230000 0 0x10000>, 1078 <0 0x11f50000 0 0x1000>; 1079 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1080 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1081 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1082 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1083 clock-names = "source", "hclk", "source_cg"; 1084 status = "disabled"; 1085 }; 1086 1087 mmc1: mmc@11240000 { 1088 compatible = "mediatek,mt8195-mmc", 1089 "mediatek,mt8183-mmc"; 1090 reg = <0 0x11240000 0 0x1000>, 1091 <0 0x11c70000 0 0x1000>; 1092 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1093 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1094 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1095 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1096 clock-names = "source", "hclk", "source_cg"; 1097 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1098 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1099 status = "disabled"; 1100 }; 1101 1102 mmc2: mmc@11250000 { 1103 compatible = "mediatek,mt8195-mmc", 1104 "mediatek,mt8183-mmc"; 1105 reg = <0 0x11250000 0 0x1000>, 1106 <0 0x11e60000 0 0x1000>; 1107 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1108 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1109 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1110 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1111 clock-names = "source", "hclk", "source_cg"; 1112 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1113 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1114 status = "disabled"; 1115 }; 1116 1117 xhci1: usb@11290000 { 1118 compatible = "mediatek,mt8195-xhci", 1119 "mediatek,mtk-xhci"; 1120 reg = <0 0x11290000 0 0x1000>, 1121 <0 0x11293e00 0 0x0100>; 1122 reg-names = "mac", "ippc"; 1123 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1124 phys = <&u2port1 PHY_TYPE_USB2>; 1125 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1126 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1127 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1128 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1129 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1130 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1131 <&apmixedsys CLK_APMIXED_USB1PLL>, 1132 <&clk26m>, 1133 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1134 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1135 "xhci_ck"; 1136 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1137 wakeup-source; 1138 status = "disabled"; 1139 }; 1140 1141 xhci2: usb@112a0000 { 1142 compatible = "mediatek,mt8195-xhci", 1143 "mediatek,mtk-xhci"; 1144 reg = <0 0x112a0000 0 0x1000>, 1145 <0 0x112a3e00 0 0x0100>; 1146 reg-names = "mac", "ippc"; 1147 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1148 phys = <&u2port2 PHY_TYPE_USB2>; 1149 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1150 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1151 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1152 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1153 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1154 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1155 <&clk26m>, 1156 <&clk26m>, 1157 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1158 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1159 "xhci_ck"; 1160 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1161 wakeup-source; 1162 status = "disabled"; 1163 }; 1164 1165 xhci3: usb@112b0000 { 1166 compatible = "mediatek,mt8195-xhci", 1167 "mediatek,mtk-xhci"; 1168 reg = <0 0x112b0000 0 0x1000>, 1169 <0 0x112b3e00 0 0x0100>; 1170 reg-names = "mac", "ippc"; 1171 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1172 phys = <&u2port3 PHY_TYPE_USB2>; 1173 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1174 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1175 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1176 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1177 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1178 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1179 <&clk26m>, 1180 <&clk26m>, 1181 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1182 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1183 "xhci_ck"; 1184 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1185 wakeup-source; 1186 status = "disabled"; 1187 }; 1188 1189 pcie0: pcie@112f0000 { 1190 compatible = "mediatek,mt8195-pcie", 1191 "mediatek,mt8192-pcie"; 1192 device_type = "pci"; 1193 #address-cells = <3>; 1194 #size-cells = <2>; 1195 reg = <0 0x112f0000 0 0x4000>; 1196 reg-names = "pcie-mac"; 1197 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1198 bus-range = <0x00 0xff>; 1199 ranges = <0x81000000 0 0x20000000 1200 0x0 0x20000000 0 0x200000>, 1201 <0x82000000 0 0x20200000 1202 0x0 0x20200000 0 0x3e00000>; 1203 1204 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1205 iommu-map-mask = <0x0>; 1206 1207 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1208 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1209 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1210 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1211 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1212 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1213 clock-names = "pl_250m", "tl_26m", "tl_96m", 1214 "tl_32k", "peri_26m", "peri_mem"; 1215 assigned-clocks = <&topckgen CLK_TOP_TL>; 1216 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1217 1218 phys = <&pciephy>; 1219 phy-names = "pcie-phy"; 1220 1221 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1222 1223 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1224 reset-names = "mac"; 1225 1226 #interrupt-cells = <1>; 1227 interrupt-map-mask = <0 0 0 7>; 1228 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1229 <0 0 0 2 &pcie_intc0 1>, 1230 <0 0 0 3 &pcie_intc0 2>, 1231 <0 0 0 4 &pcie_intc0 3>; 1232 status = "disabled"; 1233 1234 pcie_intc0: interrupt-controller { 1235 interrupt-controller; 1236 #address-cells = <0>; 1237 #interrupt-cells = <1>; 1238 }; 1239 }; 1240 1241 pcie1: pcie@112f8000 { 1242 compatible = "mediatek,mt8195-pcie", 1243 "mediatek,mt8192-pcie"; 1244 device_type = "pci"; 1245 #address-cells = <3>; 1246 #size-cells = <2>; 1247 reg = <0 0x112f8000 0 0x4000>; 1248 reg-names = "pcie-mac"; 1249 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1250 bus-range = <0x00 0xff>; 1251 ranges = <0x81000000 0 0x24000000 1252 0x0 0x24000000 0 0x200000>, 1253 <0x82000000 0 0x24200000 1254 0x0 0x24200000 0 0x3e00000>; 1255 1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1257 iommu-map-mask = <0x0>; 1258 1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1260 <&clk26m>, 1261 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1262 <&clk26m>, 1263 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1264 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1266 clock-names = "pl_250m", "tl_26m", "tl_96m", 1267 "tl_32k", "peri_26m", "peri_mem"; 1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1270 1271 phys = <&u3port1 PHY_TYPE_PCIE>; 1272 phy-names = "pcie-phy"; 1273 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1274 1275 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1276 reset-names = "mac"; 1277 1278 #interrupt-cells = <1>; 1279 interrupt-map-mask = <0 0 0 7>; 1280 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1281 <0 0 0 2 &pcie_intc1 1>, 1282 <0 0 0 3 &pcie_intc1 2>, 1283 <0 0 0 4 &pcie_intc1 3>; 1284 status = "disabled"; 1285 1286 pcie_intc1: interrupt-controller { 1287 interrupt-controller; 1288 #address-cells = <0>; 1289 #interrupt-cells = <1>; 1290 }; 1291 }; 1292 1293 nor_flash: spi@1132c000 { 1294 compatible = "mediatek,mt8195-nor", 1295 "mediatek,mt8173-nor"; 1296 reg = <0 0x1132c000 0 0x1000>; 1297 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1298 clocks = <&topckgen CLK_TOP_SPINOR>, 1299 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1300 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1301 clock-names = "spi", "sf", "axi"; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 status = "disabled"; 1305 }; 1306 1307 efuse: efuse@11c10000 { 1308 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1309 reg = <0 0x11c10000 0 0x1000>; 1310 #address-cells = <1>; 1311 #size-cells = <1>; 1312 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1313 reg = <0x184 0x1>; 1314 bits = <0 5>; 1315 }; 1316 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1317 reg = <0x184 0x2>; 1318 bits = <5 5>; 1319 }; 1320 u3_intr_p0: usb3-intr@185 { 1321 reg = <0x185 0x1>; 1322 bits = <2 6>; 1323 }; 1324 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1325 reg = <0x186 0x1>; 1326 bits = <0 5>; 1327 }; 1328 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1329 reg = <0x186 0x2>; 1330 bits = <5 5>; 1331 }; 1332 comb_intr_p1: usb3-intr@187 { 1333 reg = <0x187 0x1>; 1334 bits = <2 6>; 1335 }; 1336 u2_intr_p0: usb2-intr-p0@188,1 { 1337 reg = <0x188 0x1>; 1338 bits = <0 5>; 1339 }; 1340 u2_intr_p1: usb2-intr-p1@188,2 { 1341 reg = <0x188 0x2>; 1342 bits = <5 5>; 1343 }; 1344 u2_intr_p2: usb2-intr-p2@189,1 { 1345 reg = <0x189 0x1>; 1346 bits = <2 5>; 1347 }; 1348 u2_intr_p3: usb2-intr-p3@189,2 { 1349 reg = <0x189 0x2>; 1350 bits = <7 5>; 1351 }; 1352 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1353 reg = <0x190 0x1>; 1354 bits = <0 4>; 1355 }; 1356 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1357 reg = <0x190 0x1>; 1358 bits = <4 4>; 1359 }; 1360 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1361 reg = <0x191 0x1>; 1362 bits = <0 4>; 1363 }; 1364 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1365 reg = <0x191 0x1>; 1366 bits = <4 4>; 1367 }; 1368 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1369 reg = <0x192 0x1>; 1370 bits = <0 4>; 1371 }; 1372 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1373 reg = <0x192 0x1>; 1374 bits = <4 4>; 1375 }; 1376 pciephy_glb_intr: pciephy-glb-intr@193 { 1377 reg = <0x193 0x1>; 1378 bits = <0 4>; 1379 }; 1380 }; 1381 1382 u3phy2: t-phy@11c40000 { 1383 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1384 #address-cells = <1>; 1385 #size-cells = <1>; 1386 ranges = <0 0 0x11c40000 0x700>; 1387 status = "disabled"; 1388 1389 u2port2: usb-phy@0 { 1390 reg = <0x0 0x700>; 1391 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1392 clock-names = "ref"; 1393 #phy-cells = <1>; 1394 }; 1395 }; 1396 1397 u3phy3: t-phy@11c50000 { 1398 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1399 #address-cells = <1>; 1400 #size-cells = <1>; 1401 ranges = <0 0 0x11c50000 0x700>; 1402 status = "disabled"; 1403 1404 u2port3: usb-phy@0 { 1405 reg = <0x0 0x700>; 1406 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1407 clock-names = "ref"; 1408 #phy-cells = <1>; 1409 }; 1410 }; 1411 1412 i2c5: i2c@11d00000 { 1413 compatible = "mediatek,mt8195-i2c", 1414 "mediatek,mt8192-i2c"; 1415 reg = <0 0x11d00000 0 0x1000>, 1416 <0 0x10220580 0 0x80>; 1417 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1418 clock-div = <1>; 1419 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1420 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1421 clock-names = "main", "dma"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 i2c6: i2c@11d01000 { 1428 compatible = "mediatek,mt8195-i2c", 1429 "mediatek,mt8192-i2c"; 1430 reg = <0 0x11d01000 0 0x1000>, 1431 <0 0x10220600 0 0x80>; 1432 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1433 clock-div = <1>; 1434 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1435 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1436 clock-names = "main", "dma"; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 i2c7: i2c@11d02000 { 1443 compatible = "mediatek,mt8195-i2c", 1444 "mediatek,mt8192-i2c"; 1445 reg = <0 0x11d02000 0 0x1000>, 1446 <0 0x10220680 0 0x80>; 1447 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1448 clock-div = <1>; 1449 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1450 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1451 clock-names = "main", "dma"; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 imp_iic_wrap_s: clock-controller@11d03000 { 1458 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1459 reg = <0 0x11d03000 0 0x1000>; 1460 #clock-cells = <1>; 1461 }; 1462 1463 i2c0: i2c@11e00000 { 1464 compatible = "mediatek,mt8195-i2c", 1465 "mediatek,mt8192-i2c"; 1466 reg = <0 0x11e00000 0 0x1000>, 1467 <0 0x10220080 0 0x80>; 1468 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1469 clock-div = <1>; 1470 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1471 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1472 clock-names = "main", "dma"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 i2c1: i2c@11e01000 { 1479 compatible = "mediatek,mt8195-i2c", 1480 "mediatek,mt8192-i2c"; 1481 reg = <0 0x11e01000 0 0x1000>, 1482 <0 0x10220200 0 0x80>; 1483 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1484 clock-div = <1>; 1485 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1486 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1487 clock-names = "main", "dma"; 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 status = "disabled"; 1491 }; 1492 1493 i2c2: i2c@11e02000 { 1494 compatible = "mediatek,mt8195-i2c", 1495 "mediatek,mt8192-i2c"; 1496 reg = <0 0x11e02000 0 0x1000>, 1497 <0 0x10220380 0 0x80>; 1498 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1499 clock-div = <1>; 1500 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1501 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1502 clock-names = "main", "dma"; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 status = "disabled"; 1506 }; 1507 1508 i2c3: i2c@11e03000 { 1509 compatible = "mediatek,mt8195-i2c", 1510 "mediatek,mt8192-i2c"; 1511 reg = <0 0x11e03000 0 0x1000>, 1512 <0 0x10220480 0 0x80>; 1513 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1514 clock-div = <1>; 1515 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1516 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1517 clock-names = "main", "dma"; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 i2c4: i2c@11e04000 { 1524 compatible = "mediatek,mt8195-i2c", 1525 "mediatek,mt8192-i2c"; 1526 reg = <0 0x11e04000 0 0x1000>, 1527 <0 0x10220500 0 0x80>; 1528 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1529 clock-div = <1>; 1530 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1531 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1532 clock-names = "main", "dma"; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 status = "disabled"; 1536 }; 1537 1538 imp_iic_wrap_w: clock-controller@11e05000 { 1539 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1540 reg = <0 0x11e05000 0 0x1000>; 1541 #clock-cells = <1>; 1542 }; 1543 1544 u3phy1: t-phy@11e30000 { 1545 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1546 #address-cells = <1>; 1547 #size-cells = <1>; 1548 ranges = <0 0 0x11e30000 0xe00>; 1549 status = "disabled"; 1550 1551 u2port1: usb-phy@0 { 1552 reg = <0x0 0x700>; 1553 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1554 <&clk26m>; 1555 clock-names = "ref", "da_ref"; 1556 #phy-cells = <1>; 1557 }; 1558 1559 u3port1: usb-phy@700 { 1560 reg = <0x700 0x700>; 1561 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1562 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1563 clock-names = "ref", "da_ref"; 1564 nvmem-cells = <&comb_intr_p1>, 1565 <&comb_rx_imp_p1>, 1566 <&comb_tx_imp_p1>; 1567 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1568 #phy-cells = <1>; 1569 }; 1570 }; 1571 1572 u3phy0: t-phy@11e40000 { 1573 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1574 #address-cells = <1>; 1575 #size-cells = <1>; 1576 ranges = <0 0 0x11e40000 0xe00>; 1577 status = "disabled"; 1578 1579 u2port0: usb-phy@0 { 1580 reg = <0x0 0x700>; 1581 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1582 <&clk26m>; 1583 clock-names = "ref", "da_ref"; 1584 #phy-cells = <1>; 1585 }; 1586 1587 u3port0: usb-phy@700 { 1588 reg = <0x700 0x700>; 1589 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1590 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1591 clock-names = "ref", "da_ref"; 1592 nvmem-cells = <&u3_intr_p0>, 1593 <&u3_rx_imp_p0>, 1594 <&u3_tx_imp_p0>; 1595 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1596 #phy-cells = <1>; 1597 }; 1598 }; 1599 1600 pciephy: phy@11e80000 { 1601 compatible = "mediatek,mt8195-pcie-phy"; 1602 reg = <0 0x11e80000 0 0x10000>; 1603 reg-names = "sif"; 1604 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1605 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1606 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1607 <&pciephy_rx_ln1>; 1608 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1609 "tx_ln0_nmos", "rx_ln0", 1610 "tx_ln1_pmos", "tx_ln1_nmos", 1611 "rx_ln1"; 1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1613 #phy-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 ufsphy: ufs-phy@11fa0000 { 1618 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1619 reg = <0 0x11fa0000 0 0xc000>; 1620 clocks = <&clk26m>, <&clk26m>; 1621 clock-names = "unipro", "mp"; 1622 #phy-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 mfgcfg: clock-controller@13fbf000 { 1627 compatible = "mediatek,mt8195-mfgcfg"; 1628 reg = <0 0x13fbf000 0 0x1000>; 1629 #clock-cells = <1>; 1630 }; 1631 1632 vppsys0: clock-controller@14000000 { 1633 compatible = "mediatek,mt8195-vppsys0"; 1634 reg = <0 0x14000000 0 0x1000>; 1635 #clock-cells = <1>; 1636 }; 1637 1638 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1639 compatible = "mediatek,mt8195-smi-sub-common"; 1640 reg = <0 0x14010000 0 0x1000>; 1641 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1642 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1643 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1644 clock-names = "apb", "smi", "gals0"; 1645 mediatek,smi = <&smi_common_vpp>; 1646 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1647 }; 1648 1649 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1650 compatible = "mediatek,mt8195-smi-sub-common"; 1651 reg = <0 0x14011000 0 0x1000>; 1652 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1653 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1654 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1655 clock-names = "apb", "smi", "gals0"; 1656 mediatek,smi = <&smi_common_vpp>; 1657 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1658 }; 1659 1660 smi_common_vpp: smi@14012000 { 1661 compatible = "mediatek,mt8195-smi-common-vpp"; 1662 reg = <0 0x14012000 0 0x1000>; 1663 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1664 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1665 <&vppsys0 CLK_VPP0_SMI_RSI>, 1666 <&vppsys0 CLK_VPP0_SMI_RSI>; 1667 clock-names = "apb", "smi", "gals0", "gals1"; 1668 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1669 }; 1670 1671 larb4: larb@14013000 { 1672 compatible = "mediatek,mt8195-smi-larb"; 1673 reg = <0 0x14013000 0 0x1000>; 1674 mediatek,larb-id = <4>; 1675 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1676 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1677 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1678 clock-names = "apb", "smi"; 1679 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1680 }; 1681 1682 iommu_vpp: iommu@14018000 { 1683 compatible = "mediatek,mt8195-iommu-vpp"; 1684 reg = <0 0x14018000 0 0x1000>; 1685 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1686 &larb12 &larb14 &larb16 &larb18 1687 &larb20 &larb22 &larb23 &larb26 1688 &larb27>; 1689 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1690 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1691 clock-names = "bclk"; 1692 #iommu-cells = <1>; 1693 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1694 }; 1695 1696 wpesys: clock-controller@14e00000 { 1697 compatible = "mediatek,mt8195-wpesys"; 1698 reg = <0 0x14e00000 0 0x1000>; 1699 #clock-cells = <1>; 1700 }; 1701 1702 wpesys_vpp0: clock-controller@14e02000 { 1703 compatible = "mediatek,mt8195-wpesys_vpp0"; 1704 reg = <0 0x14e02000 0 0x1000>; 1705 #clock-cells = <1>; 1706 }; 1707 1708 wpesys_vpp1: clock-controller@14e03000 { 1709 compatible = "mediatek,mt8195-wpesys_vpp1"; 1710 reg = <0 0x14e03000 0 0x1000>; 1711 #clock-cells = <1>; 1712 }; 1713 1714 larb7: larb@14e04000 { 1715 compatible = "mediatek,mt8195-smi-larb"; 1716 reg = <0 0x14e04000 0 0x1000>; 1717 mediatek,larb-id = <7>; 1718 mediatek,smi = <&smi_common_vdo>; 1719 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1720 <&wpesys CLK_WPE_SMI_LARB7>; 1721 clock-names = "apb", "smi"; 1722 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1723 }; 1724 1725 larb8: larb@14e05000 { 1726 compatible = "mediatek,mt8195-smi-larb"; 1727 reg = <0 0x14e05000 0 0x1000>; 1728 mediatek,larb-id = <8>; 1729 mediatek,smi = <&smi_common_vpp>; 1730 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1731 <&wpesys CLK_WPE_SMI_LARB8>, 1732 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1733 clock-names = "apb", "smi", "gals"; 1734 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1735 }; 1736 1737 vppsys1: clock-controller@14f00000 { 1738 compatible = "mediatek,mt8195-vppsys1"; 1739 reg = <0 0x14f00000 0 0x1000>; 1740 #clock-cells = <1>; 1741 }; 1742 1743 larb5: larb@14f02000 { 1744 compatible = "mediatek,mt8195-smi-larb"; 1745 reg = <0 0x14f02000 0 0x1000>; 1746 mediatek,larb-id = <5>; 1747 mediatek,smi = <&smi_common_vdo>; 1748 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1749 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1750 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1751 clock-names = "apb", "smi", "gals"; 1752 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1753 }; 1754 1755 larb6: larb@14f03000 { 1756 compatible = "mediatek,mt8195-smi-larb"; 1757 reg = <0 0x14f03000 0 0x1000>; 1758 mediatek,larb-id = <6>; 1759 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1760 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1761 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1762 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1763 clock-names = "apb", "smi", "gals"; 1764 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1765 }; 1766 1767 imgsys: clock-controller@15000000 { 1768 compatible = "mediatek,mt8195-imgsys"; 1769 reg = <0 0x15000000 0 0x1000>; 1770 #clock-cells = <1>; 1771 }; 1772 1773 larb9: larb@15001000 { 1774 compatible = "mediatek,mt8195-smi-larb"; 1775 reg = <0 0x15001000 0 0x1000>; 1776 mediatek,larb-id = <9>; 1777 mediatek,smi = <&smi_sub_common_img1_3x1>; 1778 clocks = <&imgsys CLK_IMG_LARB9>, 1779 <&imgsys CLK_IMG_LARB9>, 1780 <&imgsys CLK_IMG_GALS>; 1781 clock-names = "apb", "smi", "gals"; 1782 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1783 }; 1784 1785 smi_sub_common_img0_3x1: smi@15002000 { 1786 compatible = "mediatek,mt8195-smi-sub-common"; 1787 reg = <0 0x15002000 0 0x1000>; 1788 clocks = <&imgsys CLK_IMG_IPE>, 1789 <&imgsys CLK_IMG_IPE>, 1790 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1791 clock-names = "apb", "smi", "gals0"; 1792 mediatek,smi = <&smi_common_vpp>; 1793 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1794 }; 1795 1796 smi_sub_common_img1_3x1: smi@15003000 { 1797 compatible = "mediatek,mt8195-smi-sub-common"; 1798 reg = <0 0x15003000 0 0x1000>; 1799 clocks = <&imgsys CLK_IMG_LARB9>, 1800 <&imgsys CLK_IMG_LARB9>, 1801 <&imgsys CLK_IMG_GALS>; 1802 clock-names = "apb", "smi", "gals0"; 1803 mediatek,smi = <&smi_common_vdo>; 1804 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1805 }; 1806 1807 imgsys1_dip_top: clock-controller@15110000 { 1808 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1809 reg = <0 0x15110000 0 0x1000>; 1810 #clock-cells = <1>; 1811 }; 1812 1813 larb10: larb@15120000 { 1814 compatible = "mediatek,mt8195-smi-larb"; 1815 reg = <0 0x15120000 0 0x1000>; 1816 mediatek,larb-id = <10>; 1817 mediatek,smi = <&smi_sub_common_img1_3x1>; 1818 clocks = <&imgsys CLK_IMG_DIP0>, 1819 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1820 clock-names = "apb", "smi"; 1821 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1822 }; 1823 1824 imgsys1_dip_nr: clock-controller@15130000 { 1825 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1826 reg = <0 0x15130000 0 0x1000>; 1827 #clock-cells = <1>; 1828 }; 1829 1830 imgsys1_wpe: clock-controller@15220000 { 1831 compatible = "mediatek,mt8195-imgsys1_wpe"; 1832 reg = <0 0x15220000 0 0x1000>; 1833 #clock-cells = <1>; 1834 }; 1835 1836 larb11: larb@15230000 { 1837 compatible = "mediatek,mt8195-smi-larb"; 1838 reg = <0 0x15230000 0 0x1000>; 1839 mediatek,larb-id = <11>; 1840 mediatek,smi = <&smi_sub_common_img1_3x1>; 1841 clocks = <&imgsys CLK_IMG_WPE0>, 1842 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 1843 clock-names = "apb", "smi"; 1844 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1845 }; 1846 1847 ipesys: clock-controller@15330000 { 1848 compatible = "mediatek,mt8195-ipesys"; 1849 reg = <0 0x15330000 0 0x1000>; 1850 #clock-cells = <1>; 1851 }; 1852 1853 larb12: larb@15340000 { 1854 compatible = "mediatek,mt8195-smi-larb"; 1855 reg = <0 0x15340000 0 0x1000>; 1856 mediatek,larb-id = <12>; 1857 mediatek,smi = <&smi_sub_common_img0_3x1>; 1858 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 1859 <&ipesys CLK_IPE_SMI_LARB12>; 1860 clock-names = "apb", "smi"; 1861 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 1862 }; 1863 1864 camsys: clock-controller@16000000 { 1865 compatible = "mediatek,mt8195-camsys"; 1866 reg = <0 0x16000000 0 0x1000>; 1867 #clock-cells = <1>; 1868 }; 1869 1870 larb13: larb@16001000 { 1871 compatible = "mediatek,mt8195-smi-larb"; 1872 reg = <0 0x16001000 0 0x1000>; 1873 mediatek,larb-id = <13>; 1874 mediatek,smi = <&smi_sub_common_cam_4x1>; 1875 clocks = <&camsys CLK_CAM_LARB13>, 1876 <&camsys CLK_CAM_LARB13>, 1877 <&camsys CLK_CAM_CAM2MM0_GALS>; 1878 clock-names = "apb", "smi", "gals"; 1879 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1880 }; 1881 1882 larb14: larb@16002000 { 1883 compatible = "mediatek,mt8195-smi-larb"; 1884 reg = <0 0x16002000 0 0x1000>; 1885 mediatek,larb-id = <14>; 1886 mediatek,smi = <&smi_sub_common_cam_7x1>; 1887 clocks = <&camsys CLK_CAM_LARB14>, 1888 <&camsys CLK_CAM_LARB14>; 1889 clock-names = "apb", "smi"; 1890 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1891 }; 1892 1893 smi_sub_common_cam_4x1: smi@16004000 { 1894 compatible = "mediatek,mt8195-smi-sub-common"; 1895 reg = <0 0x16004000 0 0x1000>; 1896 clocks = <&camsys CLK_CAM_LARB13>, 1897 <&camsys CLK_CAM_LARB13>, 1898 <&camsys CLK_CAM_CAM2MM0_GALS>; 1899 clock-names = "apb", "smi", "gals0"; 1900 mediatek,smi = <&smi_common_vdo>; 1901 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1902 }; 1903 1904 smi_sub_common_cam_7x1: smi@16005000 { 1905 compatible = "mediatek,mt8195-smi-sub-common"; 1906 reg = <0 0x16005000 0 0x1000>; 1907 clocks = <&camsys CLK_CAM_LARB14>, 1908 <&camsys CLK_CAM_CAM2MM1_GALS>, 1909 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1910 clock-names = "apb", "smi", "gals0"; 1911 mediatek,smi = <&smi_common_vpp>; 1912 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1913 }; 1914 1915 larb16: larb@16012000 { 1916 compatible = "mediatek,mt8195-smi-larb"; 1917 reg = <0 0x16012000 0 0x1000>; 1918 mediatek,larb-id = <16>; 1919 mediatek,smi = <&smi_sub_common_cam_7x1>; 1920 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1921 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1922 clock-names = "apb", "smi"; 1923 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1924 }; 1925 1926 larb17: larb@16013000 { 1927 compatible = "mediatek,mt8195-smi-larb"; 1928 reg = <0 0x16013000 0 0x1000>; 1929 mediatek,larb-id = <17>; 1930 mediatek,smi = <&smi_sub_common_cam_4x1>; 1931 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 1932 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1933 clock-names = "apb", "smi"; 1934 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1935 }; 1936 1937 larb27: larb@16014000 { 1938 compatible = "mediatek,mt8195-smi-larb"; 1939 reg = <0 0x16014000 0 0x1000>; 1940 mediatek,larb-id = <27>; 1941 mediatek,smi = <&smi_sub_common_cam_7x1>; 1942 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1943 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1944 clock-names = "apb", "smi"; 1945 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1946 }; 1947 1948 larb28: larb@16015000 { 1949 compatible = "mediatek,mt8195-smi-larb"; 1950 reg = <0 0x16015000 0 0x1000>; 1951 mediatek,larb-id = <28>; 1952 mediatek,smi = <&smi_sub_common_cam_4x1>; 1953 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 1954 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1955 clock-names = "apb", "smi"; 1956 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 1957 }; 1958 1959 camsys_rawa: clock-controller@1604f000 { 1960 compatible = "mediatek,mt8195-camsys_rawa"; 1961 reg = <0 0x1604f000 0 0x1000>; 1962 #clock-cells = <1>; 1963 }; 1964 1965 camsys_yuva: clock-controller@1606f000 { 1966 compatible = "mediatek,mt8195-camsys_yuva"; 1967 reg = <0 0x1606f000 0 0x1000>; 1968 #clock-cells = <1>; 1969 }; 1970 1971 camsys_rawb: clock-controller@1608f000 { 1972 compatible = "mediatek,mt8195-camsys_rawb"; 1973 reg = <0 0x1608f000 0 0x1000>; 1974 #clock-cells = <1>; 1975 }; 1976 1977 camsys_yuvb: clock-controller@160af000 { 1978 compatible = "mediatek,mt8195-camsys_yuvb"; 1979 reg = <0 0x160af000 0 0x1000>; 1980 #clock-cells = <1>; 1981 }; 1982 1983 camsys_mraw: clock-controller@16140000 { 1984 compatible = "mediatek,mt8195-camsys_mraw"; 1985 reg = <0 0x16140000 0 0x1000>; 1986 #clock-cells = <1>; 1987 }; 1988 1989 larb25: larb@16141000 { 1990 compatible = "mediatek,mt8195-smi-larb"; 1991 reg = <0 0x16141000 0 0x1000>; 1992 mediatek,larb-id = <25>; 1993 mediatek,smi = <&smi_sub_common_cam_4x1>; 1994 clocks = <&camsys CLK_CAM_LARB13>, 1995 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 1996 <&camsys CLK_CAM_CAM2MM0_GALS>; 1997 clock-names = "apb", "smi", "gals"; 1998 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 1999 }; 2000 2001 larb26: larb@16142000 { 2002 compatible = "mediatek,mt8195-smi-larb"; 2003 reg = <0 0x16142000 0 0x1000>; 2004 mediatek,larb-id = <26>; 2005 mediatek,smi = <&smi_sub_common_cam_7x1>; 2006 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2007 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2008 clock-names = "apb", "smi"; 2009 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2010 2011 }; 2012 2013 ccusys: clock-controller@17200000 { 2014 compatible = "mediatek,mt8195-ccusys"; 2015 reg = <0 0x17200000 0 0x1000>; 2016 #clock-cells = <1>; 2017 }; 2018 2019 larb18: larb@17201000 { 2020 compatible = "mediatek,mt8195-smi-larb"; 2021 reg = <0 0x17201000 0 0x1000>; 2022 mediatek,larb-id = <18>; 2023 mediatek,smi = <&smi_sub_common_cam_7x1>; 2024 clocks = <&ccusys CLK_CCU_LARB18>, 2025 <&ccusys CLK_CCU_LARB18>; 2026 clock-names = "apb", "smi"; 2027 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2028 }; 2029 2030 larb24: larb@1800d000 { 2031 compatible = "mediatek,mt8195-smi-larb"; 2032 reg = <0 0x1800d000 0 0x1000>; 2033 mediatek,larb-id = <24>; 2034 mediatek,smi = <&smi_common_vdo>; 2035 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2036 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2037 clock-names = "apb", "smi"; 2038 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2039 }; 2040 2041 larb23: larb@1800e000 { 2042 compatible = "mediatek,mt8195-smi-larb"; 2043 reg = <0 0x1800e000 0 0x1000>; 2044 mediatek,larb-id = <23>; 2045 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2046 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2047 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2048 clock-names = "apb", "smi"; 2049 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2050 }; 2051 2052 vdecsys_soc: clock-controller@1800f000 { 2053 compatible = "mediatek,mt8195-vdecsys_soc"; 2054 reg = <0 0x1800f000 0 0x1000>; 2055 #clock-cells = <1>; 2056 }; 2057 2058 larb21: larb@1802e000 { 2059 compatible = "mediatek,mt8195-smi-larb"; 2060 reg = <0 0x1802e000 0 0x1000>; 2061 mediatek,larb-id = <21>; 2062 mediatek,smi = <&smi_common_vdo>; 2063 clocks = <&vdecsys CLK_VDEC_LARB1>, 2064 <&vdecsys CLK_VDEC_LARB1>; 2065 clock-names = "apb", "smi"; 2066 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2067 }; 2068 2069 vdecsys: clock-controller@1802f000 { 2070 compatible = "mediatek,mt8195-vdecsys"; 2071 reg = <0 0x1802f000 0 0x1000>; 2072 #clock-cells = <1>; 2073 }; 2074 2075 larb22: larb@1803e000 { 2076 compatible = "mediatek,mt8195-smi-larb"; 2077 reg = <0 0x1803e000 0 0x1000>; 2078 mediatek,larb-id = <22>; 2079 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2080 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2081 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2082 clock-names = "apb", "smi"; 2083 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2084 }; 2085 2086 vdecsys_core1: clock-controller@1803f000 { 2087 compatible = "mediatek,mt8195-vdecsys_core1"; 2088 reg = <0 0x1803f000 0 0x1000>; 2089 #clock-cells = <1>; 2090 }; 2091 2092 apusys_pll: clock-controller@190f3000 { 2093 compatible = "mediatek,mt8195-apusys_pll"; 2094 reg = <0 0x190f3000 0 0x1000>; 2095 #clock-cells = <1>; 2096 }; 2097 2098 vencsys: clock-controller@1a000000 { 2099 compatible = "mediatek,mt8195-vencsys"; 2100 reg = <0 0x1a000000 0 0x1000>; 2101 #clock-cells = <1>; 2102 }; 2103 2104 larb19: larb@1a010000 { 2105 compatible = "mediatek,mt8195-smi-larb"; 2106 reg = <0 0x1a010000 0 0x1000>; 2107 mediatek,larb-id = <19>; 2108 mediatek,smi = <&smi_common_vdo>; 2109 clocks = <&vencsys CLK_VENC_VENC>, 2110 <&vencsys CLK_VENC_GALS>; 2111 clock-names = "apb", "smi"; 2112 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2113 }; 2114 2115 venc: video-codec@1a020000 { 2116 compatible = "mediatek,mt8195-vcodec-enc"; 2117 reg = <0 0x1a020000 0 0x10000>; 2118 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2119 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2120 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2121 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2122 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2123 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2124 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2125 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2126 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2127 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2128 mediatek,scp = <&scp>; 2129 clocks = <&vencsys CLK_VENC_VENC>; 2130 clock-names = "venc_sel"; 2131 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2132 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2133 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2134 #address-cells = <2>; 2135 #size-cells = <2>; 2136 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2137 }; 2138 2139 vencsys_core1: clock-controller@1b000000 { 2140 compatible = "mediatek,mt8195-vencsys_core1"; 2141 reg = <0 0x1b000000 0 0x1000>; 2142 #clock-cells = <1>; 2143 }; 2144 2145 vdosys0: syscon@1c01a000 { 2146 compatible = "mediatek,mt8195-mmsys", "syscon"; 2147 reg = <0 0x1c01a000 0 0x1000>; 2148 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2149 #clock-cells = <1>; 2150 }; 2151 2152 larb20: larb@1b010000 { 2153 compatible = "mediatek,mt8195-smi-larb"; 2154 reg = <0 0x1b010000 0 0x1000>; 2155 mediatek,larb-id = <20>; 2156 mediatek,smi = <&smi_common_vpp>; 2157 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2158 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2159 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2160 clock-names = "apb", "smi", "gals"; 2161 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2162 }; 2163 2164 ovl0: ovl@1c000000 { 2165 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2166 reg = <0 0x1c000000 0 0x1000>; 2167 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2168 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2169 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2170 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2171 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2172 }; 2173 2174 rdma0: rdma@1c002000 { 2175 compatible = "mediatek,mt8195-disp-rdma"; 2176 reg = <0 0x1c002000 0 0x1000>; 2177 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2178 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2179 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2180 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2181 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2182 }; 2183 2184 color0: color@1c003000 { 2185 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2186 reg = <0 0x1c003000 0 0x1000>; 2187 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2188 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2189 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2190 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2191 }; 2192 2193 ccorr0: ccorr@1c004000 { 2194 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2195 reg = <0 0x1c004000 0 0x1000>; 2196 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2197 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2198 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2199 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2200 }; 2201 2202 aal0: aal@1c005000 { 2203 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2204 reg = <0 0x1c005000 0 0x1000>; 2205 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2206 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2207 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2208 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2209 }; 2210 2211 gamma0: gamma@1c006000 { 2212 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2213 reg = <0 0x1c006000 0 0x1000>; 2214 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2215 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2216 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2217 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2218 }; 2219 2220 dither0: dither@1c007000 { 2221 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2222 reg = <0 0x1c007000 0 0x1000>; 2223 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2224 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2225 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2226 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2227 }; 2228 2229 dsc0: dsc@1c009000 { 2230 compatible = "mediatek,mt8195-disp-dsc"; 2231 reg = <0 0x1c009000 0 0x1000>; 2232 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2233 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2234 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2235 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2236 }; 2237 2238 merge0: merge@1c014000 { 2239 compatible = "mediatek,mt8195-disp-merge"; 2240 reg = <0 0x1c014000 0 0x1000>; 2241 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2242 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2243 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2244 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2245 }; 2246 2247 mutex: mutex@1c016000 { 2248 compatible = "mediatek,mt8195-disp-mutex"; 2249 reg = <0 0x1c016000 0 0x1000>; 2250 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2251 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2252 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2253 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2254 }; 2255 2256 larb0: larb@1c018000 { 2257 compatible = "mediatek,mt8195-smi-larb"; 2258 reg = <0 0x1c018000 0 0x1000>; 2259 mediatek,larb-id = <0>; 2260 mediatek,smi = <&smi_common_vdo>; 2261 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2262 <&vdosys0 CLK_VDO0_SMI_LARB>, 2263 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2264 clock-names = "apb", "smi", "gals"; 2265 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2266 }; 2267 2268 larb1: larb@1c019000 { 2269 compatible = "mediatek,mt8195-smi-larb"; 2270 reg = <0 0x1c019000 0 0x1000>; 2271 mediatek,larb-id = <1>; 2272 mediatek,smi = <&smi_common_vpp>; 2273 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2274 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2275 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2276 clock-names = "apb", "smi", "gals"; 2277 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2278 }; 2279 2280 vdosys1: syscon@1c100000 { 2281 compatible = "mediatek,mt8195-mmsys", "syscon"; 2282 reg = <0 0x1c100000 0 0x1000>; 2283 #clock-cells = <1>; 2284 }; 2285 2286 smi_common_vdo: smi@1c01b000 { 2287 compatible = "mediatek,mt8195-smi-common-vdo"; 2288 reg = <0 0x1c01b000 0 0x1000>; 2289 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2290 <&vdosys0 CLK_VDO0_SMI_EMI>, 2291 <&vdosys0 CLK_VDO0_SMI_RSI>, 2292 <&vdosys0 CLK_VDO0_SMI_GALS>; 2293 clock-names = "apb", "smi", "gals0", "gals1"; 2294 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2295 2296 }; 2297 2298 iommu_vdo: iommu@1c01f000 { 2299 compatible = "mediatek,mt8195-iommu-vdo"; 2300 reg = <0 0x1c01f000 0 0x1000>; 2301 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2302 &larb10 &larb11 &larb13 &larb17 2303 &larb19 &larb21 &larb24 &larb25 2304 &larb28>; 2305 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2306 #iommu-cells = <1>; 2307 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2308 clock-names = "bclk"; 2309 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2310 }; 2311 2312 larb2: larb@1c102000 { 2313 compatible = "mediatek,mt8195-smi-larb"; 2314 reg = <0 0x1c102000 0 0x1000>; 2315 mediatek,larb-id = <2>; 2316 mediatek,smi = <&smi_common_vdo>; 2317 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2318 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2319 <&vdosys1 CLK_VDO1_GALS>; 2320 clock-names = "apb", "smi", "gals"; 2321 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2322 }; 2323 2324 larb3: larb@1c103000 { 2325 compatible = "mediatek,mt8195-smi-larb"; 2326 reg = <0 0x1c103000 0 0x1000>; 2327 mediatek,larb-id = <3>; 2328 mediatek,smi = <&smi_common_vpp>; 2329 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2330 <&vdosys1 CLK_VDO1_GALS>, 2331 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2332 clock-names = "apb", "smi", "gals"; 2333 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2334 }; 2335 }; 2336}; 2337