mt8195.dtsi (b7f638d6bab947cf19ba33a453070077c5fb6c49) mt8195.dtsi (f4747b91dbc6a388240e4bfd929b7e17f2598f99)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1110 <&topckgen CLK_TOP_SPI>,
1111 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1112 clock-names = "parent-clk", "sel-clk", "spi-clk";
1113 status = "disabled";
1114 };
1115
1116 lvts_ap: thermal-sensor@1100b000 {
1117 compatible = "mediatek,mt8195-lvts-ap";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1110 <&topckgen CLK_TOP_SPI>,
1111 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1112 clock-names = "parent-clk", "sel-clk", "spi-clk";
1113 status = "disabled";
1114 };
1115
1116 lvts_ap: thermal-sensor@1100b000 {
1117 compatible = "mediatek,mt8195-lvts-ap";
1118 reg = <0 0x1100b000 0 0x1000>;
1118 reg = <0 0x1100b000 0 0xc00>;
1119 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1120 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1121 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1122 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1123 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1124 #thermal-sensor-cells = <1>;
1125 };
1126
1119 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1120 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1121 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1122 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1123 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1124 #thermal-sensor-cells = <1>;
1125 };
1126
1127 svs: svs@1100bc00 {
1128 compatible = "mediatek,mt8195-svs";
1129 reg = <0 0x1100bc00 0 0x400>;
1130 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
1131 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1132 clock-names = "main";
1133 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1134 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1135 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1136 reset-names = "svs_rst";
1137 };
1138
1127 disp_pwm0: pwm@1100e000 {
1128 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1129 reg = <0 0x1100e000 0 0x1000>;
1130 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1131 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1132 #pwm-cells = <2>;
1133 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1134 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;

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1677 reg = <0x1ac 0x10>;
1678 };
1679 lvts_efuse_data1: lvts1-calib@1bc {
1680 reg = <0x1bc 0x14>;
1681 };
1682 lvts_efuse_data2: lvts2-calib@1d0 {
1683 reg = <0x1d0 0x38>;
1684 };
1139 disp_pwm0: pwm@1100e000 {
1140 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1141 reg = <0 0x1100e000 0 0x1000>;
1142 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1143 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1144 #pwm-cells = <2>;
1145 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1146 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;

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1689 reg = <0x1ac 0x10>;
1690 };
1691 lvts_efuse_data1: lvts1-calib@1bc {
1692 reg = <0x1bc 0x14>;
1693 };
1694 lvts_efuse_data2: lvts2-calib@1d0 {
1695 reg = <0x1d0 0x38>;
1696 };
1697 svs_calib_data: svs-calib@580 {
1698 reg = <0x580 0x64>;
1699 };
1685 };
1686
1687 u3phy2: t-phy@11c40000 {
1688 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1689 #address-cells = <1>;
1690 #size-cells = <1>;
1691 ranges = <0 0 0x11c40000 0x700>;
1692 status = "disabled";

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1701
1702 u3phy2: t-phy@11c40000 {
1703 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1704 #address-cells = <1>;
1705 #size-cells = <1>;
1706 ranges = <0 0 0x11c40000 0x700>;
1707 status = "disabled";

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