1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 621 reg = <MT8195_POWER_DOMAIN_VDEC1>; 622 clocks = <&vdecsys CLK_VDEC_LARB1>; 623 clock-names = "vdec1-0"; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 630 mediatek,infracfg = <&infracfg_ao>; 631 #power-domain-cells = <0>; 632 }; 633 634 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 635 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 636 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 637 <&vdosys0 CLK_VDO0_SMI_GALS>, 638 <&vdosys0 CLK_VDO0_SMI_COMMON>, 639 <&vdosys0 CLK_VDO0_SMI_EMI>, 640 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 641 <&vdosys0 CLK_VDO0_SMI_LARB>, 642 <&vdosys0 CLK_VDO0_SMI_RSI>; 643 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 644 "vdosys0-2", "vdosys0-3", 645 "vdosys0-4", "vdosys0-5"; 646 mediatek,infracfg = <&infracfg_ao>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 #power-domain-cells = <1>; 650 651 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 652 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 653 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 654 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 655 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 656 clock-names = "vppsys1", "vppsys1-0", 657 "vppsys1-1"; 658 mediatek,infracfg = <&infracfg_ao>; 659 #power-domain-cells = <0>; 660 }; 661 662 power-domain@MT8195_POWER_DOMAIN_WPESYS { 663 reg = <MT8195_POWER_DOMAIN_WPESYS>; 664 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 665 <&wpesys CLK_WPE_SMI_LARB8>, 666 <&wpesys CLK_WPE_SMI_LARB7_P>, 667 <&wpesys CLK_WPE_SMI_LARB8_P>; 668 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 669 "wepsys-3"; 670 mediatek,infracfg = <&infracfg_ao>; 671 #power-domain-cells = <0>; 672 }; 673 674 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 675 reg = <MT8195_POWER_DOMAIN_VDEC0>; 676 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 677 clock-names = "vdec0-0"; 678 mediatek,infracfg = <&infracfg_ao>; 679 #power-domain-cells = <0>; 680 }; 681 682 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 683 reg = <MT8195_POWER_DOMAIN_VDEC2>; 684 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 685 clock-names = "vdec2-0"; 686 mediatek,infracfg = <&infracfg_ao>; 687 #power-domain-cells = <0>; 688 }; 689 690 power-domain@MT8195_POWER_DOMAIN_VENC { 691 reg = <MT8195_POWER_DOMAIN_VENC>; 692 mediatek,infracfg = <&infracfg_ao>; 693 #power-domain-cells = <0>; 694 }; 695 696 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 697 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 698 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 699 <&vdosys1 CLK_VDO1_SMI_LARB2>, 700 <&vdosys1 CLK_VDO1_SMI_LARB3>, 701 <&vdosys1 CLK_VDO1_GALS>; 702 clock-names = "vdosys1", "vdosys1-0", 703 "vdosys1-1", "vdosys1-2"; 704 mediatek,infracfg = <&infracfg_ao>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 #power-domain-cells = <1>; 708 709 power-domain@MT8195_POWER_DOMAIN_DP_TX { 710 reg = <MT8195_POWER_DOMAIN_DP_TX>; 711 mediatek,infracfg = <&infracfg_ao>; 712 #power-domain-cells = <0>; 713 }; 714 715 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 716 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 717 mediatek,infracfg = <&infracfg_ao>; 718 #power-domain-cells = <0>; 719 }; 720 721 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 722 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 723 clocks = <&topckgen CLK_TOP_HDMI_APB>; 724 clock-names = "hdmi_tx"; 725 #power-domain-cells = <0>; 726 }; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_IMG { 730 reg = <MT8195_POWER_DOMAIN_IMG>; 731 clocks = <&imgsys CLK_IMG_LARB9>, 732 <&imgsys CLK_IMG_GALS>; 733 clock-names = "img-0", "img-1"; 734 mediatek,infracfg = <&infracfg_ao>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 #power-domain-cells = <1>; 738 739 power-domain@MT8195_POWER_DOMAIN_DIP { 740 reg = <MT8195_POWER_DOMAIN_DIP>; 741 #power-domain-cells = <0>; 742 }; 743 744 power-domain@MT8195_POWER_DOMAIN_IPE { 745 reg = <MT8195_POWER_DOMAIN_IPE>; 746 clocks = <&topckgen CLK_TOP_IPE>, 747 <&imgsys CLK_IMG_IPE>, 748 <&ipesys CLK_IPE_SMI_LARB12>; 749 clock-names = "ipe", "ipe-0", "ipe-1"; 750 mediatek,infracfg = <&infracfg_ao>; 751 #power-domain-cells = <0>; 752 }; 753 }; 754 755 power-domain@MT8195_POWER_DOMAIN_CAM { 756 reg = <MT8195_POWER_DOMAIN_CAM>; 757 clocks = <&camsys CLK_CAM_LARB13>, 758 <&camsys CLK_CAM_LARB14>, 759 <&camsys CLK_CAM_CAM2MM0_GALS>, 760 <&camsys CLK_CAM_CAM2MM1_GALS>, 761 <&camsys CLK_CAM_CAM2SYS_GALS>; 762 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 763 "cam-4"; 764 mediatek,infracfg = <&infracfg_ao>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 #power-domain-cells = <1>; 768 769 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 770 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 771 #power-domain-cells = <0>; 772 }; 773 774 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 775 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 776 #power-domain-cells = <0>; 777 }; 778 779 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 780 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 781 #power-domain-cells = <0>; 782 }; 783 }; 784 }; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 788 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 789 mediatek,infracfg = <&infracfg_ao>; 790 #power-domain-cells = <0>; 791 }; 792 793 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 794 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 795 mediatek,infracfg = <&infracfg_ao>; 796 #power-domain-cells = <0>; 797 }; 798 799 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 800 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 801 #power-domain-cells = <0>; 802 }; 803 804 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 805 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 806 #power-domain-cells = <0>; 807 }; 808 809 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 810 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 811 clocks = <&topckgen CLK_TOP_SENINF>, 812 <&topckgen CLK_TOP_SENINF2>; 813 clock-names = "csi_rx_top", "csi_rx_top1"; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_ETHER { 818 reg = <MT8195_POWER_DOMAIN_ETHER>; 819 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 820 clock-names = "ether"; 821 #power-domain-cells = <0>; 822 }; 823 824 power-domain@MT8195_POWER_DOMAIN_ADSP { 825 reg = <MT8195_POWER_DOMAIN_ADSP>; 826 clocks = <&topckgen CLK_TOP_ADSP>, 827 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 828 clock-names = "adsp", "adsp1"; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 mediatek,infracfg = <&infracfg_ao>; 832 #power-domain-cells = <1>; 833 834 power-domain@MT8195_POWER_DOMAIN_AUDIO { 835 reg = <MT8195_POWER_DOMAIN_AUDIO>; 836 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 837 <&topckgen CLK_TOP_AUD_INTBUS>, 838 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 839 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 840 clock-names = "audio", "audio1", "audio2", 841 "audio3"; 842 mediatek,infracfg = <&infracfg_ao>; 843 #power-domain-cells = <0>; 844 }; 845 }; 846 }; 847 }; 848 849 watchdog: watchdog@10007000 { 850 compatible = "mediatek,mt8195-wdt"; 851 mediatek,disable-extrst; 852 reg = <0 0x10007000 0 0x100>; 853 #reset-cells = <1>; 854 }; 855 856 apmixedsys: syscon@1000c000 { 857 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 858 reg = <0 0x1000c000 0 0x1000>; 859 #clock-cells = <1>; 860 }; 861 862 systimer: timer@10017000 { 863 compatible = "mediatek,mt8195-timer", 864 "mediatek,mt6765-timer"; 865 reg = <0 0x10017000 0 0x1000>; 866 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 867 clocks = <&clk13m>; 868 }; 869 870 pwrap: pwrap@10024000 { 871 compatible = "mediatek,mt8195-pwrap", "syscon"; 872 reg = <0 0x10024000 0 0x1000>; 873 reg-names = "pwrap"; 874 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 876 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 877 clock-names = "spi", "wrap"; 878 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 879 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 880 }; 881 882 spmi: spmi@10027000 { 883 compatible = "mediatek,mt8195-spmi"; 884 reg = <0 0x10027000 0 0x000e00>, 885 <0 0x10029000 0 0x000100>; 886 reg-names = "pmif", "spmimst"; 887 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 888 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 889 <&topckgen CLK_TOP_SPMI_M_MST>; 890 clock-names = "pmif_sys_ck", 891 "pmif_tmr_ck", 892 "spmimst_clk_mux"; 893 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 894 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 895 }; 896 897 iommu_infra: infra-iommu@10315000 { 898 compatible = "mediatek,mt8195-iommu-infra"; 899 reg = <0 0x10315000 0 0x5000>; 900 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 901 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 902 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 903 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 904 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 905 #iommu-cells = <1>; 906 }; 907 908 gce0: mailbox@10320000 { 909 compatible = "mediatek,mt8195-gce"; 910 reg = <0 0x10320000 0 0x4000>; 911 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 912 #mbox-cells = <2>; 913 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 914 }; 915 916 gce1: mailbox@10330000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10330000 0 0x4000>; 919 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 922 }; 923 924 scp: scp@10500000 { 925 compatible = "mediatek,mt8195-scp"; 926 reg = <0 0x10500000 0 0x100000>, 927 <0 0x10720000 0 0xe0000>, 928 <0 0x10700000 0 0x8000>; 929 reg-names = "sram", "cfg", "l1tcm"; 930 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 931 status = "disabled"; 932 }; 933 934 scp_adsp: clock-controller@10720000 { 935 compatible = "mediatek,mt8195-scp_adsp"; 936 reg = <0 0x10720000 0 0x1000>; 937 #clock-cells = <1>; 938 }; 939 940 adsp: dsp@10803000 { 941 compatible = "mediatek,mt8195-dsp"; 942 reg = <0 0x10803000 0 0x1000>, 943 <0 0x10840000 0 0x40000>; 944 reg-names = "cfg", "sram"; 945 clocks = <&topckgen CLK_TOP_ADSP>, 946 <&clk26m>, 947 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 948 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 949 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 950 <&topckgen CLK_TOP_AUDIO_H>; 951 clock-names = "adsp_sel", 952 "clk26m_ck", 953 "audio_local_bus", 954 "mainpll_d7_d2", 955 "scp_adsp_audiodsp", 956 "audio_h"; 957 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 958 mbox-names = "rx", "tx"; 959 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 960 status = "disabled"; 961 }; 962 963 adsp_mailbox0: mailbox@10816000 { 964 compatible = "mediatek,mt8195-adsp-mbox"; 965 #mbox-cells = <0>; 966 reg = <0 0x10816000 0 0x1000>; 967 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 968 }; 969 970 adsp_mailbox1: mailbox@10817000 { 971 compatible = "mediatek,mt8195-adsp-mbox"; 972 #mbox-cells = <0>; 973 reg = <0 0x10817000 0 0x1000>; 974 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 975 }; 976 977 afe: mt8195-afe-pcm@10890000 { 978 compatible = "mediatek,mt8195-audio"; 979 reg = <0 0x10890000 0 0x10000>; 980 mediatek,topckgen = <&topckgen>; 981 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 982 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 983 resets = <&watchdog 14>; 984 reset-names = "audiosys"; 985 clocks = <&clk26m>, 986 <&apmixedsys CLK_APMIXED_APLL1>, 987 <&apmixedsys CLK_APMIXED_APLL2>, 988 <&topckgen CLK_TOP_APLL12_DIV0>, 989 <&topckgen CLK_TOP_APLL12_DIV1>, 990 <&topckgen CLK_TOP_APLL12_DIV2>, 991 <&topckgen CLK_TOP_APLL12_DIV3>, 992 <&topckgen CLK_TOP_APLL12_DIV9>, 993 <&topckgen CLK_TOP_A1SYS_HP>, 994 <&topckgen CLK_TOP_AUD_INTBUS>, 995 <&topckgen CLK_TOP_AUDIO_H>, 996 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 997 <&topckgen CLK_TOP_DPTX_MCK>, 998 <&topckgen CLK_TOP_I2SO1_MCK>, 999 <&topckgen CLK_TOP_I2SO2_MCK>, 1000 <&topckgen CLK_TOP_I2SI1_MCK>, 1001 <&topckgen CLK_TOP_I2SI2_MCK>, 1002 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1003 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1004 clock-names = "clk26m", 1005 "apll1_ck", 1006 "apll2_ck", 1007 "apll12_div0", 1008 "apll12_div1", 1009 "apll12_div2", 1010 "apll12_div3", 1011 "apll12_div9", 1012 "a1sys_hp_sel", 1013 "aud_intbus_sel", 1014 "audio_h_sel", 1015 "audio_local_bus_sel", 1016 "dptx_m_sel", 1017 "i2so1_m_sel", 1018 "i2so2_m_sel", 1019 "i2si1_m_sel", 1020 "i2si2_m_sel", 1021 "infra_ao_audio_26m_b", 1022 "scp_adsp_audiodsp"; 1023 status = "disabled"; 1024 }; 1025 1026 uart0: serial@11001100 { 1027 compatible = "mediatek,mt8195-uart", 1028 "mediatek,mt6577-uart"; 1029 reg = <0 0x11001100 0 0x100>; 1030 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1032 clock-names = "baud", "bus"; 1033 status = "disabled"; 1034 }; 1035 1036 uart1: serial@11001200 { 1037 compatible = "mediatek,mt8195-uart", 1038 "mediatek,mt6577-uart"; 1039 reg = <0 0x11001200 0 0x100>; 1040 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1041 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1042 clock-names = "baud", "bus"; 1043 status = "disabled"; 1044 }; 1045 1046 uart2: serial@11001300 { 1047 compatible = "mediatek,mt8195-uart", 1048 "mediatek,mt6577-uart"; 1049 reg = <0 0x11001300 0 0x100>; 1050 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1051 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1052 clock-names = "baud", "bus"; 1053 status = "disabled"; 1054 }; 1055 1056 uart3: serial@11001400 { 1057 compatible = "mediatek,mt8195-uart", 1058 "mediatek,mt6577-uart"; 1059 reg = <0 0x11001400 0 0x100>; 1060 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1061 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1062 clock-names = "baud", "bus"; 1063 status = "disabled"; 1064 }; 1065 1066 uart4: serial@11001500 { 1067 compatible = "mediatek,mt8195-uart", 1068 "mediatek,mt6577-uart"; 1069 reg = <0 0x11001500 0 0x100>; 1070 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1071 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1072 clock-names = "baud", "bus"; 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@11001600 { 1077 compatible = "mediatek,mt8195-uart", 1078 "mediatek,mt6577-uart"; 1079 reg = <0 0x11001600 0 0x100>; 1080 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1081 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1082 clock-names = "baud", "bus"; 1083 status = "disabled"; 1084 }; 1085 1086 auxadc: auxadc@11002000 { 1087 compatible = "mediatek,mt8195-auxadc", 1088 "mediatek,mt8173-auxadc"; 1089 reg = <0 0x11002000 0 0x1000>; 1090 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1091 clock-names = "main"; 1092 #io-channel-cells = <1>; 1093 status = "disabled"; 1094 }; 1095 1096 pericfg_ao: syscon@11003000 { 1097 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1098 reg = <0 0x11003000 0 0x1000>; 1099 #clock-cells = <1>; 1100 }; 1101 1102 spi0: spi@1100a000 { 1103 compatible = "mediatek,mt8195-spi", 1104 "mediatek,mt6765-spi"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 reg = <0 0x1100a000 0 0x1000>; 1108 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1109 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1110 <&topckgen CLK_TOP_SPI>, 1111 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1112 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1113 status = "disabled"; 1114 }; 1115 1116 lvts_ap: thermal-sensor@1100b000 { 1117 compatible = "mediatek,mt8195-lvts-ap"; 1118 reg = <0 0x1100b000 0 0x1000>; 1119 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1120 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1121 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1122 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1123 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1124 #thermal-sensor-cells = <1>; 1125 }; 1126 1127 disp_pwm0: pwm@1100e000 { 1128 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1129 reg = <0 0x1100e000 0 0x1000>; 1130 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1131 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1132 #pwm-cells = <2>; 1133 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1134 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1135 clock-names = "main", "mm"; 1136 status = "disabled"; 1137 }; 1138 1139 disp_pwm1: pwm@1100f000 { 1140 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1141 reg = <0 0x1100f000 0 0x1000>; 1142 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1143 #pwm-cells = <2>; 1144 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1145 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1146 clock-names = "main", "mm"; 1147 status = "disabled"; 1148 }; 1149 1150 spi1: spi@11010000 { 1151 compatible = "mediatek,mt8195-spi", 1152 "mediatek,mt6765-spi"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 reg = <0 0x11010000 0 0x1000>; 1156 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1157 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1158 <&topckgen CLK_TOP_SPI>, 1159 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1160 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1161 status = "disabled"; 1162 }; 1163 1164 spi2: spi@11012000 { 1165 compatible = "mediatek,mt8195-spi", 1166 "mediatek,mt6765-spi"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 reg = <0 0x11012000 0 0x1000>; 1170 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1171 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1172 <&topckgen CLK_TOP_SPI>, 1173 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1174 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1175 status = "disabled"; 1176 }; 1177 1178 spi3: spi@11013000 { 1179 compatible = "mediatek,mt8195-spi", 1180 "mediatek,mt6765-spi"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 reg = <0 0x11013000 0 0x1000>; 1184 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1185 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1186 <&topckgen CLK_TOP_SPI>, 1187 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1188 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1189 status = "disabled"; 1190 }; 1191 1192 spi4: spi@11018000 { 1193 compatible = "mediatek,mt8195-spi", 1194 "mediatek,mt6765-spi"; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 reg = <0 0x11018000 0 0x1000>; 1198 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1199 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1200 <&topckgen CLK_TOP_SPI>, 1201 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1202 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1203 status = "disabled"; 1204 }; 1205 1206 spi5: spi@11019000 { 1207 compatible = "mediatek,mt8195-spi", 1208 "mediatek,mt6765-spi"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 reg = <0 0x11019000 0 0x1000>; 1212 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1213 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1214 <&topckgen CLK_TOP_SPI>, 1215 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1216 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1217 status = "disabled"; 1218 }; 1219 1220 spis0: spi@1101d000 { 1221 compatible = "mediatek,mt8195-spi-slave"; 1222 reg = <0 0x1101d000 0 0x1000>; 1223 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1224 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1225 clock-names = "spi"; 1226 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1227 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1228 status = "disabled"; 1229 }; 1230 1231 spis1: spi@1101e000 { 1232 compatible = "mediatek,mt8195-spi-slave"; 1233 reg = <0 0x1101e000 0 0x1000>; 1234 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1236 clock-names = "spi"; 1237 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1238 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1239 status = "disabled"; 1240 }; 1241 1242 eth: ethernet@11021000 { 1243 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1244 reg = <0 0x11021000 0 0x4000>; 1245 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1246 interrupt-names = "macirq"; 1247 clock-names = "axi", 1248 "apb", 1249 "mac_main", 1250 "ptp_ref", 1251 "rmii_internal", 1252 "mac_cg"; 1253 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1254 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1255 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1256 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1257 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1258 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1259 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1260 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1261 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1262 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1263 <&topckgen CLK_TOP_ETHPLL_D8>, 1264 <&topckgen CLK_TOP_ETHPLL_D10>; 1265 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1266 mediatek,pericfg = <&infracfg_ao>; 1267 snps,axi-config = <&stmmac_axi_setup>; 1268 snps,mtl-rx-config = <&mtl_rx_setup>; 1269 snps,mtl-tx-config = <&mtl_tx_setup>; 1270 snps,txpbl = <16>; 1271 snps,rxpbl = <16>; 1272 snps,clk-csr = <0>; 1273 status = "disabled"; 1274 1275 mdio { 1276 compatible = "snps,dwmac-mdio"; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 }; 1280 1281 stmmac_axi_setup: stmmac-axi-config { 1282 snps,wr_osr_lmt = <0x7>; 1283 snps,rd_osr_lmt = <0x7>; 1284 snps,blen = <0 0 0 0 16 8 4>; 1285 }; 1286 1287 mtl_rx_setup: rx-queues-config { 1288 snps,rx-queues-to-use = <4>; 1289 snps,rx-sched-sp; 1290 queue0 { 1291 snps,dcb-algorithm; 1292 snps,map-to-dma-channel = <0x0>; 1293 }; 1294 queue1 { 1295 snps,dcb-algorithm; 1296 snps,map-to-dma-channel = <0x0>; 1297 }; 1298 queue2 { 1299 snps,dcb-algorithm; 1300 snps,map-to-dma-channel = <0x0>; 1301 }; 1302 queue3 { 1303 snps,dcb-algorithm; 1304 snps,map-to-dma-channel = <0x0>; 1305 }; 1306 }; 1307 1308 mtl_tx_setup: tx-queues-config { 1309 snps,tx-queues-to-use = <4>; 1310 snps,tx-sched-wrr; 1311 queue0 { 1312 snps,weight = <0x10>; 1313 snps,dcb-algorithm; 1314 snps,priority = <0x0>; 1315 }; 1316 queue1 { 1317 snps,weight = <0x11>; 1318 snps,dcb-algorithm; 1319 snps,priority = <0x1>; 1320 }; 1321 queue2 { 1322 snps,weight = <0x12>; 1323 snps,dcb-algorithm; 1324 snps,priority = <0x2>; 1325 }; 1326 queue3 { 1327 snps,weight = <0x13>; 1328 snps,dcb-algorithm; 1329 snps,priority = <0x3>; 1330 }; 1331 }; 1332 }; 1333 1334 xhci0: usb@11200000 { 1335 compatible = "mediatek,mt8195-xhci", 1336 "mediatek,mtk-xhci"; 1337 reg = <0 0x11200000 0 0x1000>, 1338 <0 0x11203e00 0 0x0100>; 1339 reg-names = "mac", "ippc"; 1340 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1341 phys = <&u2port0 PHY_TYPE_USB2>, 1342 <&u3port0 PHY_TYPE_USB3>; 1343 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1344 <&topckgen CLK_TOP_SSUSB_XHCI>; 1345 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1346 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1347 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1348 <&topckgen CLK_TOP_SSUSB_REF>, 1349 <&apmixedsys CLK_APMIXED_USB1PLL>, 1350 <&clk26m>, 1351 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1352 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1353 "xhci_ck"; 1354 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1355 wakeup-source; 1356 status = "disabled"; 1357 }; 1358 1359 mmc0: mmc@11230000 { 1360 compatible = "mediatek,mt8195-mmc", 1361 "mediatek,mt8183-mmc"; 1362 reg = <0 0x11230000 0 0x10000>, 1363 <0 0x11f50000 0 0x1000>; 1364 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1365 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1366 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1367 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1368 clock-names = "source", "hclk", "source_cg"; 1369 status = "disabled"; 1370 }; 1371 1372 mmc1: mmc@11240000 { 1373 compatible = "mediatek,mt8195-mmc", 1374 "mediatek,mt8183-mmc"; 1375 reg = <0 0x11240000 0 0x1000>, 1376 <0 0x11c70000 0 0x1000>; 1377 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1378 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1379 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1380 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1381 clock-names = "source", "hclk", "source_cg"; 1382 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1383 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1384 status = "disabled"; 1385 }; 1386 1387 mmc2: mmc@11250000 { 1388 compatible = "mediatek,mt8195-mmc", 1389 "mediatek,mt8183-mmc"; 1390 reg = <0 0x11250000 0 0x1000>, 1391 <0 0x11e60000 0 0x1000>; 1392 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1393 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1394 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1395 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1396 clock-names = "source", "hclk", "source_cg"; 1397 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1398 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1399 status = "disabled"; 1400 }; 1401 1402 lvts_mcu: thermal-sensor@11278000 { 1403 compatible = "mediatek,mt8195-lvts-mcu"; 1404 reg = <0 0x11278000 0 0x1000>; 1405 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1406 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1407 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1408 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1409 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1410 #thermal-sensor-cells = <1>; 1411 }; 1412 1413 xhci1: usb@11290000 { 1414 compatible = "mediatek,mt8195-xhci", 1415 "mediatek,mtk-xhci"; 1416 reg = <0 0x11290000 0 0x1000>, 1417 <0 0x11293e00 0 0x0100>; 1418 reg-names = "mac", "ippc"; 1419 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1420 phys = <&u2port1 PHY_TYPE_USB2>; 1421 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1422 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1423 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1424 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1425 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1426 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1427 <&apmixedsys CLK_APMIXED_USB1PLL>, 1428 <&clk26m>, 1429 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1430 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1431 "xhci_ck"; 1432 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1433 wakeup-source; 1434 status = "disabled"; 1435 }; 1436 1437 xhci2: usb@112a0000 { 1438 compatible = "mediatek,mt8195-xhci", 1439 "mediatek,mtk-xhci"; 1440 reg = <0 0x112a0000 0 0x1000>, 1441 <0 0x112a3e00 0 0x0100>; 1442 reg-names = "mac", "ippc"; 1443 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1444 phys = <&u2port2 PHY_TYPE_USB2>; 1445 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1446 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1447 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1448 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1449 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1450 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1451 <&clk26m>, 1452 <&clk26m>, 1453 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1454 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1455 "xhci_ck"; 1456 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1457 wakeup-source; 1458 status = "disabled"; 1459 }; 1460 1461 xhci3: usb@112b0000 { 1462 compatible = "mediatek,mt8195-xhci", 1463 "mediatek,mtk-xhci"; 1464 reg = <0 0x112b0000 0 0x1000>, 1465 <0 0x112b3e00 0 0x0100>; 1466 reg-names = "mac", "ippc"; 1467 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1468 phys = <&u2port3 PHY_TYPE_USB2>; 1469 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1470 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1471 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1472 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1473 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1474 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1475 <&clk26m>, 1476 <&clk26m>, 1477 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1478 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1479 "xhci_ck"; 1480 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1481 wakeup-source; 1482 status = "disabled"; 1483 }; 1484 1485 pcie0: pcie@112f0000 { 1486 compatible = "mediatek,mt8195-pcie", 1487 "mediatek,mt8192-pcie"; 1488 device_type = "pci"; 1489 #address-cells = <3>; 1490 #size-cells = <2>; 1491 reg = <0 0x112f0000 0 0x4000>; 1492 reg-names = "pcie-mac"; 1493 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1494 bus-range = <0x00 0xff>; 1495 ranges = <0x81000000 0 0x20000000 1496 0x0 0x20000000 0 0x200000>, 1497 <0x82000000 0 0x20200000 1498 0x0 0x20200000 0 0x3e00000>; 1499 1500 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1501 iommu-map-mask = <0x0>; 1502 1503 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1504 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1505 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1506 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1507 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1508 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1509 clock-names = "pl_250m", "tl_26m", "tl_96m", 1510 "tl_32k", "peri_26m", "peri_mem"; 1511 assigned-clocks = <&topckgen CLK_TOP_TL>; 1512 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1513 1514 phys = <&pciephy>; 1515 phy-names = "pcie-phy"; 1516 1517 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1518 1519 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1520 reset-names = "mac"; 1521 1522 #interrupt-cells = <1>; 1523 interrupt-map-mask = <0 0 0 7>; 1524 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1525 <0 0 0 2 &pcie_intc0 1>, 1526 <0 0 0 3 &pcie_intc0 2>, 1527 <0 0 0 4 &pcie_intc0 3>; 1528 status = "disabled"; 1529 1530 pcie_intc0: interrupt-controller { 1531 interrupt-controller; 1532 #address-cells = <0>; 1533 #interrupt-cells = <1>; 1534 }; 1535 }; 1536 1537 pcie1: pcie@112f8000 { 1538 compatible = "mediatek,mt8195-pcie", 1539 "mediatek,mt8192-pcie"; 1540 device_type = "pci"; 1541 #address-cells = <3>; 1542 #size-cells = <2>; 1543 reg = <0 0x112f8000 0 0x4000>; 1544 reg-names = "pcie-mac"; 1545 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1546 bus-range = <0x00 0xff>; 1547 ranges = <0x81000000 0 0x24000000 1548 0x0 0x24000000 0 0x200000>, 1549 <0x82000000 0 0x24200000 1550 0x0 0x24200000 0 0x3e00000>; 1551 1552 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1553 iommu-map-mask = <0x0>; 1554 1555 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1556 <&clk26m>, 1557 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1558 <&clk26m>, 1559 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1560 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1561 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1562 clock-names = "pl_250m", "tl_26m", "tl_96m", 1563 "tl_32k", "peri_26m", "peri_mem"; 1564 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1565 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1566 1567 phys = <&u3port1 PHY_TYPE_PCIE>; 1568 phy-names = "pcie-phy"; 1569 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1570 1571 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1572 reset-names = "mac"; 1573 1574 #interrupt-cells = <1>; 1575 interrupt-map-mask = <0 0 0 7>; 1576 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1577 <0 0 0 2 &pcie_intc1 1>, 1578 <0 0 0 3 &pcie_intc1 2>, 1579 <0 0 0 4 &pcie_intc1 3>; 1580 status = "disabled"; 1581 1582 pcie_intc1: interrupt-controller { 1583 interrupt-controller; 1584 #address-cells = <0>; 1585 #interrupt-cells = <1>; 1586 }; 1587 }; 1588 1589 nor_flash: spi@1132c000 { 1590 compatible = "mediatek,mt8195-nor", 1591 "mediatek,mt8173-nor"; 1592 reg = <0 0x1132c000 0 0x1000>; 1593 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1594 clocks = <&topckgen CLK_TOP_SPINOR>, 1595 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1596 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1597 clock-names = "spi", "sf", "axi"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 efuse: efuse@11c10000 { 1604 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1605 reg = <0 0x11c10000 0 0x1000>; 1606 #address-cells = <1>; 1607 #size-cells = <1>; 1608 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1609 reg = <0x184 0x1>; 1610 bits = <0 5>; 1611 }; 1612 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1613 reg = <0x184 0x2>; 1614 bits = <5 5>; 1615 }; 1616 u3_intr_p0: usb3-intr@185 { 1617 reg = <0x185 0x1>; 1618 bits = <2 6>; 1619 }; 1620 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1621 reg = <0x186 0x1>; 1622 bits = <0 5>; 1623 }; 1624 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1625 reg = <0x186 0x2>; 1626 bits = <5 5>; 1627 }; 1628 comb_intr_p1: usb3-intr@187 { 1629 reg = <0x187 0x1>; 1630 bits = <2 6>; 1631 }; 1632 u2_intr_p0: usb2-intr-p0@188,1 { 1633 reg = <0x188 0x1>; 1634 bits = <0 5>; 1635 }; 1636 u2_intr_p1: usb2-intr-p1@188,2 { 1637 reg = <0x188 0x2>; 1638 bits = <5 5>; 1639 }; 1640 u2_intr_p2: usb2-intr-p2@189,1 { 1641 reg = <0x189 0x1>; 1642 bits = <2 5>; 1643 }; 1644 u2_intr_p3: usb2-intr-p3@189,2 { 1645 reg = <0x189 0x2>; 1646 bits = <7 5>; 1647 }; 1648 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1649 reg = <0x190 0x1>; 1650 bits = <0 4>; 1651 }; 1652 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1653 reg = <0x190 0x1>; 1654 bits = <4 4>; 1655 }; 1656 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1657 reg = <0x191 0x1>; 1658 bits = <0 4>; 1659 }; 1660 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1661 reg = <0x191 0x1>; 1662 bits = <4 4>; 1663 }; 1664 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1665 reg = <0x192 0x1>; 1666 bits = <0 4>; 1667 }; 1668 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1669 reg = <0x192 0x1>; 1670 bits = <4 4>; 1671 }; 1672 pciephy_glb_intr: pciephy-glb-intr@193 { 1673 reg = <0x193 0x1>; 1674 bits = <0 4>; 1675 }; 1676 dp_calibration: dp-data@1ac { 1677 reg = <0x1ac 0x10>; 1678 }; 1679 lvts_efuse_data1: lvts1-calib@1bc { 1680 reg = <0x1bc 0x14>; 1681 }; 1682 lvts_efuse_data2: lvts2-calib@1d0 { 1683 reg = <0x1d0 0x38>; 1684 }; 1685 }; 1686 1687 u3phy2: t-phy@11c40000 { 1688 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1689 #address-cells = <1>; 1690 #size-cells = <1>; 1691 ranges = <0 0 0x11c40000 0x700>; 1692 status = "disabled"; 1693 1694 u2port2: usb-phy@0 { 1695 reg = <0x0 0x700>; 1696 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1697 clock-names = "ref"; 1698 #phy-cells = <1>; 1699 }; 1700 }; 1701 1702 u3phy3: t-phy@11c50000 { 1703 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1704 #address-cells = <1>; 1705 #size-cells = <1>; 1706 ranges = <0 0 0x11c50000 0x700>; 1707 status = "disabled"; 1708 1709 u2port3: usb-phy@0 { 1710 reg = <0x0 0x700>; 1711 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1712 clock-names = "ref"; 1713 #phy-cells = <1>; 1714 }; 1715 }; 1716 1717 mipi_tx0: dsi-phy@11c80000 { 1718 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1719 reg = <0 0x11c80000 0 0x1000>; 1720 clocks = <&clk26m>; 1721 clock-output-names = "mipi_tx0_pll"; 1722 #clock-cells = <0>; 1723 #phy-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 mipi_tx1: dsi-phy@11c90000 { 1728 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1729 reg = <0 0x11c90000 0 0x1000>; 1730 clocks = <&clk26m>; 1731 clock-output-names = "mipi_tx1_pll"; 1732 #clock-cells = <0>; 1733 #phy-cells = <0>; 1734 status = "disabled"; 1735 }; 1736 1737 i2c5: i2c@11d00000 { 1738 compatible = "mediatek,mt8195-i2c", 1739 "mediatek,mt8192-i2c"; 1740 reg = <0 0x11d00000 0 0x1000>, 1741 <0 0x10220580 0 0x80>; 1742 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1743 clock-div = <1>; 1744 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1745 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1746 clock-names = "main", "dma"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 i2c6: i2c@11d01000 { 1753 compatible = "mediatek,mt8195-i2c", 1754 "mediatek,mt8192-i2c"; 1755 reg = <0 0x11d01000 0 0x1000>, 1756 <0 0x10220600 0 0x80>; 1757 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1758 clock-div = <1>; 1759 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1760 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1761 clock-names = "main", "dma"; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 status = "disabled"; 1765 }; 1766 1767 i2c7: i2c@11d02000 { 1768 compatible = "mediatek,mt8195-i2c", 1769 "mediatek,mt8192-i2c"; 1770 reg = <0 0x11d02000 0 0x1000>, 1771 <0 0x10220680 0 0x80>; 1772 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1773 clock-div = <1>; 1774 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1775 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1776 clock-names = "main", "dma"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 imp_iic_wrap_s: clock-controller@11d03000 { 1783 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1784 reg = <0 0x11d03000 0 0x1000>; 1785 #clock-cells = <1>; 1786 }; 1787 1788 i2c0: i2c@11e00000 { 1789 compatible = "mediatek,mt8195-i2c", 1790 "mediatek,mt8192-i2c"; 1791 reg = <0 0x11e00000 0 0x1000>, 1792 <0 0x10220080 0 0x80>; 1793 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1794 clock-div = <1>; 1795 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1796 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1797 clock-names = "main", "dma"; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 status = "disabled"; 1801 }; 1802 1803 i2c1: i2c@11e01000 { 1804 compatible = "mediatek,mt8195-i2c", 1805 "mediatek,mt8192-i2c"; 1806 reg = <0 0x11e01000 0 0x1000>, 1807 <0 0x10220200 0 0x80>; 1808 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1809 clock-div = <1>; 1810 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1811 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1812 clock-names = "main", "dma"; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 status = "disabled"; 1816 }; 1817 1818 i2c2: i2c@11e02000 { 1819 compatible = "mediatek,mt8195-i2c", 1820 "mediatek,mt8192-i2c"; 1821 reg = <0 0x11e02000 0 0x1000>, 1822 <0 0x10220380 0 0x80>; 1823 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1824 clock-div = <1>; 1825 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1826 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1827 clock-names = "main", "dma"; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 i2c3: i2c@11e03000 { 1834 compatible = "mediatek,mt8195-i2c", 1835 "mediatek,mt8192-i2c"; 1836 reg = <0 0x11e03000 0 0x1000>, 1837 <0 0x10220480 0 0x80>; 1838 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1839 clock-div = <1>; 1840 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1841 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1842 clock-names = "main", "dma"; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 }; 1847 1848 i2c4: i2c@11e04000 { 1849 compatible = "mediatek,mt8195-i2c", 1850 "mediatek,mt8192-i2c"; 1851 reg = <0 0x11e04000 0 0x1000>, 1852 <0 0x10220500 0 0x80>; 1853 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1854 clock-div = <1>; 1855 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1856 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1857 clock-names = "main", "dma"; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 status = "disabled"; 1861 }; 1862 1863 imp_iic_wrap_w: clock-controller@11e05000 { 1864 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1865 reg = <0 0x11e05000 0 0x1000>; 1866 #clock-cells = <1>; 1867 }; 1868 1869 u3phy1: t-phy@11e30000 { 1870 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1871 #address-cells = <1>; 1872 #size-cells = <1>; 1873 ranges = <0 0 0x11e30000 0xe00>; 1874 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1875 status = "disabled"; 1876 1877 u2port1: usb-phy@0 { 1878 reg = <0x0 0x700>; 1879 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1880 <&clk26m>; 1881 clock-names = "ref", "da_ref"; 1882 #phy-cells = <1>; 1883 }; 1884 1885 u3port1: usb-phy@700 { 1886 reg = <0x700 0x700>; 1887 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1888 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1889 clock-names = "ref", "da_ref"; 1890 nvmem-cells = <&comb_intr_p1>, 1891 <&comb_rx_imp_p1>, 1892 <&comb_tx_imp_p1>; 1893 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1894 #phy-cells = <1>; 1895 }; 1896 }; 1897 1898 u3phy0: t-phy@11e40000 { 1899 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1900 #address-cells = <1>; 1901 #size-cells = <1>; 1902 ranges = <0 0 0x11e40000 0xe00>; 1903 status = "disabled"; 1904 1905 u2port0: usb-phy@0 { 1906 reg = <0x0 0x700>; 1907 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1908 <&clk26m>; 1909 clock-names = "ref", "da_ref"; 1910 #phy-cells = <1>; 1911 }; 1912 1913 u3port0: usb-phy@700 { 1914 reg = <0x700 0x700>; 1915 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1916 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1917 clock-names = "ref", "da_ref"; 1918 nvmem-cells = <&u3_intr_p0>, 1919 <&u3_rx_imp_p0>, 1920 <&u3_tx_imp_p0>; 1921 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1922 #phy-cells = <1>; 1923 }; 1924 }; 1925 1926 pciephy: phy@11e80000 { 1927 compatible = "mediatek,mt8195-pcie-phy"; 1928 reg = <0 0x11e80000 0 0x10000>; 1929 reg-names = "sif"; 1930 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1931 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1932 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1933 <&pciephy_rx_ln1>; 1934 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1935 "tx_ln0_nmos", "rx_ln0", 1936 "tx_ln1_pmos", "tx_ln1_nmos", 1937 "rx_ln1"; 1938 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1939 #phy-cells = <0>; 1940 status = "disabled"; 1941 }; 1942 1943 ufsphy: ufs-phy@11fa0000 { 1944 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1945 reg = <0 0x11fa0000 0 0xc000>; 1946 clocks = <&clk26m>, <&clk26m>; 1947 clock-names = "unipro", "mp"; 1948 #phy-cells = <0>; 1949 status = "disabled"; 1950 }; 1951 1952 gpu: gpu@13000000 { 1953 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1954 "arm,mali-valhall-jm"; 1955 reg = <0 0x13000000 0 0x4000>; 1956 1957 clocks = <&mfgcfg CLK_MFG_BG3D>; 1958 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1959 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1960 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1961 interrupt-names = "job", "mmu", "gpu"; 1962 operating-points-v2 = <&gpu_opp_table>; 1963 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1964 <&spm MT8195_POWER_DOMAIN_MFG3>, 1965 <&spm MT8195_POWER_DOMAIN_MFG4>, 1966 <&spm MT8195_POWER_DOMAIN_MFG5>, 1967 <&spm MT8195_POWER_DOMAIN_MFG6>; 1968 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1969 status = "disabled"; 1970 }; 1971 1972 mfgcfg: clock-controller@13fbf000 { 1973 compatible = "mediatek,mt8195-mfgcfg"; 1974 reg = <0 0x13fbf000 0 0x1000>; 1975 #clock-cells = <1>; 1976 }; 1977 1978 vppsys0: syscon@14000000 { 1979 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1980 reg = <0 0x14000000 0 0x1000>; 1981 #clock-cells = <1>; 1982 }; 1983 1984 dma-controller@14001000 { 1985 compatible = "mediatek,mt8195-mdp3-rdma"; 1986 reg = <0 0x14001000 0 0x1000>; 1987 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 1988 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 1989 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 1990 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1991 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 1992 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 1993 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 1994 <&gce1 13 CMDQ_THR_PRIO_1>, 1995 <&gce1 14 CMDQ_THR_PRIO_1>, 1996 <&gce1 21 CMDQ_THR_PRIO_1>, 1997 <&gce1 22 CMDQ_THR_PRIO_1>; 1998 #dma-cells = <1>; 1999 }; 2000 2001 display@14002000 { 2002 compatible = "mediatek,mt8195-mdp3-fg"; 2003 reg = <0 0x14002000 0 0x1000>; 2004 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2005 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2006 }; 2007 2008 display@14003000 { 2009 compatible = "mediatek,mt8195-mdp3-stitch"; 2010 reg = <0 0x14003000 0 0x1000>; 2011 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2012 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2013 }; 2014 2015 display@14004000 { 2016 compatible = "mediatek,mt8195-mdp3-hdr"; 2017 reg = <0 0x14004000 0 0x1000>; 2018 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2019 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2020 }; 2021 2022 display@14005000 { 2023 compatible = "mediatek,mt8195-mdp3-aal"; 2024 reg = <0 0x14005000 0 0x1000>; 2025 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2026 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2027 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2028 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2029 }; 2030 2031 display@14006000 { 2032 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2033 reg = <0 0x14006000 0 0x1000>; 2034 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2035 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2036 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2037 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2038 }; 2039 2040 display@14007000 { 2041 compatible = "mediatek,mt8195-mdp3-tdshp"; 2042 reg = <0 0x14007000 0 0x1000>; 2043 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2044 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2045 }; 2046 2047 display@14008000 { 2048 compatible = "mediatek,mt8195-mdp3-color"; 2049 reg = <0 0x14008000 0 0x1000>; 2050 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2051 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2052 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2053 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2054 }; 2055 2056 display@14009000 { 2057 compatible = "mediatek,mt8195-mdp3-ovl"; 2058 reg = <0 0x14009000 0 0x1000>; 2059 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2060 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2061 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2062 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2063 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2064 }; 2065 2066 display@1400a000 { 2067 compatible = "mediatek,mt8195-mdp3-padding"; 2068 reg = <0 0x1400a000 0 0x1000>; 2069 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2070 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2071 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2072 }; 2073 2074 display@1400b000 { 2075 compatible = "mediatek,mt8195-mdp3-tcc"; 2076 reg = <0 0x1400b000 0 0x1000>; 2077 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2078 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2079 }; 2080 2081 dma-controller@1400c000 { 2082 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2083 reg = <0 0x1400c000 0 0x1000>; 2084 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2085 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2086 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2087 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2088 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2089 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2090 #dma-cells = <1>; 2091 }; 2092 2093 mutex@1400f000 { 2094 compatible = "mediatek,mt8195-vpp-mutex"; 2095 reg = <0 0x1400f000 0 0x1000>; 2096 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2097 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2098 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2099 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2100 }; 2101 2102 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2103 compatible = "mediatek,mt8195-smi-sub-common"; 2104 reg = <0 0x14010000 0 0x1000>; 2105 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2106 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2107 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2108 clock-names = "apb", "smi", "gals0"; 2109 mediatek,smi = <&smi_common_vpp>; 2110 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2111 }; 2112 2113 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2114 compatible = "mediatek,mt8195-smi-sub-common"; 2115 reg = <0 0x14011000 0 0x1000>; 2116 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2117 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2118 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2119 clock-names = "apb", "smi", "gals0"; 2120 mediatek,smi = <&smi_common_vpp>; 2121 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2122 }; 2123 2124 smi_common_vpp: smi@14012000 { 2125 compatible = "mediatek,mt8195-smi-common-vpp"; 2126 reg = <0 0x14012000 0 0x1000>; 2127 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2128 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2129 <&vppsys0 CLK_VPP0_SMI_RSI>, 2130 <&vppsys0 CLK_VPP0_SMI_RSI>; 2131 clock-names = "apb", "smi", "gals0", "gals1"; 2132 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2133 }; 2134 2135 larb4: larb@14013000 { 2136 compatible = "mediatek,mt8195-smi-larb"; 2137 reg = <0 0x14013000 0 0x1000>; 2138 mediatek,larb-id = <4>; 2139 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2140 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2141 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2142 clock-names = "apb", "smi"; 2143 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2144 }; 2145 2146 iommu_vpp: iommu@14018000 { 2147 compatible = "mediatek,mt8195-iommu-vpp"; 2148 reg = <0 0x14018000 0 0x1000>; 2149 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2150 &larb12 &larb14 &larb16 &larb18 2151 &larb20 &larb22 &larb23 &larb26 2152 &larb27>; 2153 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2154 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2155 clock-names = "bclk"; 2156 #iommu-cells = <1>; 2157 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2158 }; 2159 2160 wpesys: clock-controller@14e00000 { 2161 compatible = "mediatek,mt8195-wpesys"; 2162 reg = <0 0x14e00000 0 0x1000>; 2163 #clock-cells = <1>; 2164 }; 2165 2166 wpesys_vpp0: clock-controller@14e02000 { 2167 compatible = "mediatek,mt8195-wpesys_vpp0"; 2168 reg = <0 0x14e02000 0 0x1000>; 2169 #clock-cells = <1>; 2170 }; 2171 2172 wpesys_vpp1: clock-controller@14e03000 { 2173 compatible = "mediatek,mt8195-wpesys_vpp1"; 2174 reg = <0 0x14e03000 0 0x1000>; 2175 #clock-cells = <1>; 2176 }; 2177 2178 larb7: larb@14e04000 { 2179 compatible = "mediatek,mt8195-smi-larb"; 2180 reg = <0 0x14e04000 0 0x1000>; 2181 mediatek,larb-id = <7>; 2182 mediatek,smi = <&smi_common_vdo>; 2183 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2184 <&wpesys CLK_WPE_SMI_LARB7>; 2185 clock-names = "apb", "smi"; 2186 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2187 }; 2188 2189 larb8: larb@14e05000 { 2190 compatible = "mediatek,mt8195-smi-larb"; 2191 reg = <0 0x14e05000 0 0x1000>; 2192 mediatek,larb-id = <8>; 2193 mediatek,smi = <&smi_common_vpp>; 2194 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2195 <&wpesys CLK_WPE_SMI_LARB8>, 2196 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2197 clock-names = "apb", "smi", "gals"; 2198 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2199 }; 2200 2201 vppsys1: syscon@14f00000 { 2202 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2203 reg = <0 0x14f00000 0 0x1000>; 2204 #clock-cells = <1>; 2205 }; 2206 2207 mutex@14f01000 { 2208 compatible = "mediatek,mt8195-vpp-mutex"; 2209 reg = <0 0x14f01000 0 0x1000>; 2210 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2211 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2212 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2213 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2214 }; 2215 2216 larb5: larb@14f02000 { 2217 compatible = "mediatek,mt8195-smi-larb"; 2218 reg = <0 0x14f02000 0 0x1000>; 2219 mediatek,larb-id = <5>; 2220 mediatek,smi = <&smi_common_vdo>; 2221 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2222 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2223 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2224 clock-names = "apb", "smi", "gals"; 2225 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2226 }; 2227 2228 larb6: larb@14f03000 { 2229 compatible = "mediatek,mt8195-smi-larb"; 2230 reg = <0 0x14f03000 0 0x1000>; 2231 mediatek,larb-id = <6>; 2232 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2233 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2234 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2235 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2236 clock-names = "apb", "smi", "gals"; 2237 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2238 }; 2239 2240 display@14f06000 { 2241 compatible = "mediatek,mt8195-mdp3-split"; 2242 reg = <0 0x14f06000 0 0x1000>; 2243 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2244 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2245 <&vppsys1 CLK_VPP1_HDMI_META>, 2246 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2247 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2248 }; 2249 2250 display@14f07000 { 2251 compatible = "mediatek,mt8195-mdp3-tcc"; 2252 reg = <0 0x14f07000 0 0x1000>; 2253 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2254 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2255 }; 2256 2257 dma-controller@14f08000 { 2258 compatible = "mediatek,mt8195-mdp3-rdma"; 2259 reg = <0 0x14f08000 0 0x1000>; 2260 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2261 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2262 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2263 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2264 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2265 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2266 #dma-cells = <1>; 2267 }; 2268 2269 dma-controller@14f09000 { 2270 compatible = "mediatek,mt8195-mdp3-rdma"; 2271 reg = <0 0x14f09000 0 0x1000>; 2272 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2273 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2274 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2275 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2276 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2277 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2278 #dma-cells = <1>; 2279 }; 2280 2281 dma-controller@14f0a000 { 2282 compatible = "mediatek,mt8195-mdp3-rdma"; 2283 reg = <0 0x14f0a000 0 0x1000>; 2284 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2285 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2286 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2287 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2288 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2289 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2290 #dma-cells = <1>; 2291 }; 2292 2293 display@14f0b000 { 2294 compatible = "mediatek,mt8195-mdp3-fg"; 2295 reg = <0 0x14f0b000 0 0x1000>; 2296 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2297 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2298 }; 2299 2300 display@14f0c000 { 2301 compatible = "mediatek,mt8195-mdp3-fg"; 2302 reg = <0 0x14f0c000 0 0x1000>; 2303 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2304 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2305 }; 2306 2307 display@14f0d000 { 2308 compatible = "mediatek,mt8195-mdp3-fg"; 2309 reg = <0 0x14f0d000 0 0x1000>; 2310 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2311 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2312 }; 2313 2314 display@14f0e000 { 2315 compatible = "mediatek,mt8195-mdp3-hdr"; 2316 reg = <0 0x14f0e000 0 0x1000>; 2317 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2318 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2319 }; 2320 2321 display@14f0f000 { 2322 compatible = "mediatek,mt8195-mdp3-hdr"; 2323 reg = <0 0x14f0f000 0 0x1000>; 2324 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2325 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2326 }; 2327 2328 display@14f10000 { 2329 compatible = "mediatek,mt8195-mdp3-hdr"; 2330 reg = <0 0x14f10000 0 0x1000>; 2331 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2332 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2333 }; 2334 2335 display@14f11000 { 2336 compatible = "mediatek,mt8195-mdp3-aal"; 2337 reg = <0 0x14f11000 0 0x1000>; 2338 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2339 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2340 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2341 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2342 }; 2343 2344 display@14f12000 { 2345 compatible = "mediatek,mt8195-mdp3-aal"; 2346 reg = <0 0x14f12000 0 0x1000>; 2347 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2348 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2349 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2350 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2351 }; 2352 2353 display@14f13000 { 2354 compatible = "mediatek,mt8195-mdp3-aal"; 2355 reg = <0 0x14f13000 0 0x1000>; 2356 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2357 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2358 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2359 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2360 }; 2361 2362 display@14f14000 { 2363 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2364 reg = <0 0x14f14000 0 0x1000>; 2365 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2366 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2367 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2368 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2369 }; 2370 2371 display@14f15000 { 2372 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2373 reg = <0 0x14f15000 0 0x1000>; 2374 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2375 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2376 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2377 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2378 }; 2379 2380 display@14f16000 { 2381 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2382 reg = <0 0x14f16000 0 0x1000>; 2383 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2384 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2385 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2386 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2387 }; 2388 2389 display@14f17000 { 2390 compatible = "mediatek,mt8195-mdp3-tdshp"; 2391 reg = <0 0x14f17000 0 0x1000>; 2392 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2393 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2394 }; 2395 2396 display@14f18000 { 2397 compatible = "mediatek,mt8195-mdp3-tdshp"; 2398 reg = <0 0x14f18000 0 0x1000>; 2399 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2400 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2401 }; 2402 2403 display@14f19000 { 2404 compatible = "mediatek,mt8195-mdp3-tdshp"; 2405 reg = <0 0x14f19000 0 0x1000>; 2406 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2407 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2408 }; 2409 2410 display@14f1a000 { 2411 compatible = "mediatek,mt8195-mdp3-merge"; 2412 reg = <0 0x14f1a000 0 0x1000>; 2413 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2414 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2415 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2416 }; 2417 2418 display@14f1b000 { 2419 compatible = "mediatek,mt8195-mdp3-merge"; 2420 reg = <0 0x14f1b000 0 0x1000>; 2421 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2422 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2423 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2424 }; 2425 2426 display@14f1c000 { 2427 compatible = "mediatek,mt8195-mdp3-color"; 2428 reg = <0 0x14f1c000 0 0x1000>; 2429 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2430 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2431 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2432 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2433 }; 2434 2435 display@14f1d000 { 2436 compatible = "mediatek,mt8195-mdp3-color"; 2437 reg = <0 0x14f1d000 0 0x1000>; 2438 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2439 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2440 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2441 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2442 }; 2443 2444 display@14f1e000 { 2445 compatible = "mediatek,mt8195-mdp3-color"; 2446 reg = <0 0x14f1e000 0 0x1000>; 2447 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2448 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2449 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2450 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2451 }; 2452 2453 display@14f1f000 { 2454 compatible = "mediatek,mt8195-mdp3-ovl"; 2455 reg = <0 0x14f1f000 0 0x1000>; 2456 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2457 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2458 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2459 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2460 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2461 }; 2462 2463 display@14f20000 { 2464 compatible = "mediatek,mt8195-mdp3-padding"; 2465 reg = <0 0x14f20000 0 0x1000>; 2466 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2467 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2468 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2469 }; 2470 2471 display@14f21000 { 2472 compatible = "mediatek,mt8195-mdp3-padding"; 2473 reg = <0 0x14f21000 0 0x1000>; 2474 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2475 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2476 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2477 }; 2478 2479 display@14f22000 { 2480 compatible = "mediatek,mt8195-mdp3-padding"; 2481 reg = <0 0x14f22000 0 0x1000>; 2482 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2483 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2484 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2485 }; 2486 2487 dma-controller@14f23000 { 2488 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2489 reg = <0 0x14f23000 0 0x1000>; 2490 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2491 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2492 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2493 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2494 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2495 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2496 #dma-cells = <1>; 2497 }; 2498 2499 dma-controller@14f24000 { 2500 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2501 reg = <0 0x14f24000 0 0x1000>; 2502 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2503 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2504 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2505 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2506 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2507 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2508 #dma-cells = <1>; 2509 }; 2510 2511 dma-controller@14f25000 { 2512 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2513 reg = <0 0x14f25000 0 0x1000>; 2514 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2515 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2516 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2517 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2518 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2519 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2520 #dma-cells = <1>; 2521 }; 2522 2523 imgsys: clock-controller@15000000 { 2524 compatible = "mediatek,mt8195-imgsys"; 2525 reg = <0 0x15000000 0 0x1000>; 2526 #clock-cells = <1>; 2527 }; 2528 2529 larb9: larb@15001000 { 2530 compatible = "mediatek,mt8195-smi-larb"; 2531 reg = <0 0x15001000 0 0x1000>; 2532 mediatek,larb-id = <9>; 2533 mediatek,smi = <&smi_sub_common_img1_3x1>; 2534 clocks = <&imgsys CLK_IMG_LARB9>, 2535 <&imgsys CLK_IMG_LARB9>, 2536 <&imgsys CLK_IMG_GALS>; 2537 clock-names = "apb", "smi", "gals"; 2538 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2539 }; 2540 2541 smi_sub_common_img0_3x1: smi@15002000 { 2542 compatible = "mediatek,mt8195-smi-sub-common"; 2543 reg = <0 0x15002000 0 0x1000>; 2544 clocks = <&imgsys CLK_IMG_IPE>, 2545 <&imgsys CLK_IMG_IPE>, 2546 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2547 clock-names = "apb", "smi", "gals0"; 2548 mediatek,smi = <&smi_common_vpp>; 2549 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2550 }; 2551 2552 smi_sub_common_img1_3x1: smi@15003000 { 2553 compatible = "mediatek,mt8195-smi-sub-common"; 2554 reg = <0 0x15003000 0 0x1000>; 2555 clocks = <&imgsys CLK_IMG_LARB9>, 2556 <&imgsys CLK_IMG_LARB9>, 2557 <&imgsys CLK_IMG_GALS>; 2558 clock-names = "apb", "smi", "gals0"; 2559 mediatek,smi = <&smi_common_vdo>; 2560 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2561 }; 2562 2563 imgsys1_dip_top: clock-controller@15110000 { 2564 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2565 reg = <0 0x15110000 0 0x1000>; 2566 #clock-cells = <1>; 2567 }; 2568 2569 larb10: larb@15120000 { 2570 compatible = "mediatek,mt8195-smi-larb"; 2571 reg = <0 0x15120000 0 0x1000>; 2572 mediatek,larb-id = <10>; 2573 mediatek,smi = <&smi_sub_common_img1_3x1>; 2574 clocks = <&imgsys CLK_IMG_DIP0>, 2575 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2576 clock-names = "apb", "smi"; 2577 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2578 }; 2579 2580 imgsys1_dip_nr: clock-controller@15130000 { 2581 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2582 reg = <0 0x15130000 0 0x1000>; 2583 #clock-cells = <1>; 2584 }; 2585 2586 imgsys1_wpe: clock-controller@15220000 { 2587 compatible = "mediatek,mt8195-imgsys1_wpe"; 2588 reg = <0 0x15220000 0 0x1000>; 2589 #clock-cells = <1>; 2590 }; 2591 2592 larb11: larb@15230000 { 2593 compatible = "mediatek,mt8195-smi-larb"; 2594 reg = <0 0x15230000 0 0x1000>; 2595 mediatek,larb-id = <11>; 2596 mediatek,smi = <&smi_sub_common_img1_3x1>; 2597 clocks = <&imgsys CLK_IMG_WPE0>, 2598 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2599 clock-names = "apb", "smi"; 2600 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2601 }; 2602 2603 ipesys: clock-controller@15330000 { 2604 compatible = "mediatek,mt8195-ipesys"; 2605 reg = <0 0x15330000 0 0x1000>; 2606 #clock-cells = <1>; 2607 }; 2608 2609 larb12: larb@15340000 { 2610 compatible = "mediatek,mt8195-smi-larb"; 2611 reg = <0 0x15340000 0 0x1000>; 2612 mediatek,larb-id = <12>; 2613 mediatek,smi = <&smi_sub_common_img0_3x1>; 2614 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2615 <&ipesys CLK_IPE_SMI_LARB12>; 2616 clock-names = "apb", "smi"; 2617 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2618 }; 2619 2620 camsys: clock-controller@16000000 { 2621 compatible = "mediatek,mt8195-camsys"; 2622 reg = <0 0x16000000 0 0x1000>; 2623 #clock-cells = <1>; 2624 }; 2625 2626 larb13: larb@16001000 { 2627 compatible = "mediatek,mt8195-smi-larb"; 2628 reg = <0 0x16001000 0 0x1000>; 2629 mediatek,larb-id = <13>; 2630 mediatek,smi = <&smi_sub_common_cam_4x1>; 2631 clocks = <&camsys CLK_CAM_LARB13>, 2632 <&camsys CLK_CAM_LARB13>, 2633 <&camsys CLK_CAM_CAM2MM0_GALS>; 2634 clock-names = "apb", "smi", "gals"; 2635 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2636 }; 2637 2638 larb14: larb@16002000 { 2639 compatible = "mediatek,mt8195-smi-larb"; 2640 reg = <0 0x16002000 0 0x1000>; 2641 mediatek,larb-id = <14>; 2642 mediatek,smi = <&smi_sub_common_cam_7x1>; 2643 clocks = <&camsys CLK_CAM_LARB14>, 2644 <&camsys CLK_CAM_LARB14>; 2645 clock-names = "apb", "smi"; 2646 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2647 }; 2648 2649 smi_sub_common_cam_4x1: smi@16004000 { 2650 compatible = "mediatek,mt8195-smi-sub-common"; 2651 reg = <0 0x16004000 0 0x1000>; 2652 clocks = <&camsys CLK_CAM_LARB13>, 2653 <&camsys CLK_CAM_LARB13>, 2654 <&camsys CLK_CAM_CAM2MM0_GALS>; 2655 clock-names = "apb", "smi", "gals0"; 2656 mediatek,smi = <&smi_common_vdo>; 2657 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2658 }; 2659 2660 smi_sub_common_cam_7x1: smi@16005000 { 2661 compatible = "mediatek,mt8195-smi-sub-common"; 2662 reg = <0 0x16005000 0 0x1000>; 2663 clocks = <&camsys CLK_CAM_LARB14>, 2664 <&camsys CLK_CAM_CAM2MM1_GALS>, 2665 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2666 clock-names = "apb", "smi", "gals0"; 2667 mediatek,smi = <&smi_common_vpp>; 2668 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2669 }; 2670 2671 larb16: larb@16012000 { 2672 compatible = "mediatek,mt8195-smi-larb"; 2673 reg = <0 0x16012000 0 0x1000>; 2674 mediatek,larb-id = <16>; 2675 mediatek,smi = <&smi_sub_common_cam_7x1>; 2676 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2677 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2678 clock-names = "apb", "smi"; 2679 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2680 }; 2681 2682 larb17: larb@16013000 { 2683 compatible = "mediatek,mt8195-smi-larb"; 2684 reg = <0 0x16013000 0 0x1000>; 2685 mediatek,larb-id = <17>; 2686 mediatek,smi = <&smi_sub_common_cam_4x1>; 2687 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2688 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2689 clock-names = "apb", "smi"; 2690 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2691 }; 2692 2693 larb27: larb@16014000 { 2694 compatible = "mediatek,mt8195-smi-larb"; 2695 reg = <0 0x16014000 0 0x1000>; 2696 mediatek,larb-id = <27>; 2697 mediatek,smi = <&smi_sub_common_cam_7x1>; 2698 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2699 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2700 clock-names = "apb", "smi"; 2701 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2702 }; 2703 2704 larb28: larb@16015000 { 2705 compatible = "mediatek,mt8195-smi-larb"; 2706 reg = <0 0x16015000 0 0x1000>; 2707 mediatek,larb-id = <28>; 2708 mediatek,smi = <&smi_sub_common_cam_4x1>; 2709 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2710 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2711 clock-names = "apb", "smi"; 2712 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2713 }; 2714 2715 camsys_rawa: clock-controller@1604f000 { 2716 compatible = "mediatek,mt8195-camsys_rawa"; 2717 reg = <0 0x1604f000 0 0x1000>; 2718 #clock-cells = <1>; 2719 }; 2720 2721 camsys_yuva: clock-controller@1606f000 { 2722 compatible = "mediatek,mt8195-camsys_yuva"; 2723 reg = <0 0x1606f000 0 0x1000>; 2724 #clock-cells = <1>; 2725 }; 2726 2727 camsys_rawb: clock-controller@1608f000 { 2728 compatible = "mediatek,mt8195-camsys_rawb"; 2729 reg = <0 0x1608f000 0 0x1000>; 2730 #clock-cells = <1>; 2731 }; 2732 2733 camsys_yuvb: clock-controller@160af000 { 2734 compatible = "mediatek,mt8195-camsys_yuvb"; 2735 reg = <0 0x160af000 0 0x1000>; 2736 #clock-cells = <1>; 2737 }; 2738 2739 camsys_mraw: clock-controller@16140000 { 2740 compatible = "mediatek,mt8195-camsys_mraw"; 2741 reg = <0 0x16140000 0 0x1000>; 2742 #clock-cells = <1>; 2743 }; 2744 2745 larb25: larb@16141000 { 2746 compatible = "mediatek,mt8195-smi-larb"; 2747 reg = <0 0x16141000 0 0x1000>; 2748 mediatek,larb-id = <25>; 2749 mediatek,smi = <&smi_sub_common_cam_4x1>; 2750 clocks = <&camsys CLK_CAM_LARB13>, 2751 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2752 <&camsys CLK_CAM_CAM2MM0_GALS>; 2753 clock-names = "apb", "smi", "gals"; 2754 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2755 }; 2756 2757 larb26: larb@16142000 { 2758 compatible = "mediatek,mt8195-smi-larb"; 2759 reg = <0 0x16142000 0 0x1000>; 2760 mediatek,larb-id = <26>; 2761 mediatek,smi = <&smi_sub_common_cam_7x1>; 2762 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2763 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2764 clock-names = "apb", "smi"; 2765 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2766 2767 }; 2768 2769 ccusys: clock-controller@17200000 { 2770 compatible = "mediatek,mt8195-ccusys"; 2771 reg = <0 0x17200000 0 0x1000>; 2772 #clock-cells = <1>; 2773 }; 2774 2775 larb18: larb@17201000 { 2776 compatible = "mediatek,mt8195-smi-larb"; 2777 reg = <0 0x17201000 0 0x1000>; 2778 mediatek,larb-id = <18>; 2779 mediatek,smi = <&smi_sub_common_cam_7x1>; 2780 clocks = <&ccusys CLK_CCU_LARB18>, 2781 <&ccusys CLK_CCU_LARB18>; 2782 clock-names = "apb", "smi"; 2783 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2784 }; 2785 2786 video-codec@18000000 { 2787 compatible = "mediatek,mt8195-vcodec-dec"; 2788 mediatek,scp = <&scp>; 2789 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2790 #address-cells = <2>; 2791 #size-cells = <2>; 2792 reg = <0 0x18000000 0 0x1000>, 2793 <0 0x18004000 0 0x1000>; 2794 ranges = <0 0 0 0x18000000 0 0x26000>; 2795 2796 video-codec@2000 { 2797 compatible = "mediatek,mtk-vcodec-lat-soc"; 2798 reg = <0 0x2000 0 0x800>; 2799 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2800 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2801 clocks = <&topckgen CLK_TOP_VDEC>, 2802 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2803 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2804 <&topckgen CLK_TOP_UNIVPLL_D4>; 2805 clock-names = "sel", "vdec", "lat", "top"; 2806 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2807 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2808 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2809 }; 2810 2811 video-codec@10000 { 2812 compatible = "mediatek,mtk-vcodec-lat"; 2813 reg = <0 0x10000 0 0x800>; 2814 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2815 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2816 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2817 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2818 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2819 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2820 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2821 clocks = <&topckgen CLK_TOP_VDEC>, 2822 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2823 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2824 <&topckgen CLK_TOP_UNIVPLL_D4>; 2825 clock-names = "sel", "vdec", "lat", "top"; 2826 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2827 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2828 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2829 }; 2830 2831 video-codec@25000 { 2832 compatible = "mediatek,mtk-vcodec-core"; 2833 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2834 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2835 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2836 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2837 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2838 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2839 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2840 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2841 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2842 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2843 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2844 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2845 clocks = <&topckgen CLK_TOP_VDEC>, 2846 <&vdecsys CLK_VDEC_VDEC>, 2847 <&vdecsys CLK_VDEC_LAT>, 2848 <&topckgen CLK_TOP_UNIVPLL_D4>; 2849 clock-names = "sel", "vdec", "lat", "top"; 2850 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2851 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2852 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2853 }; 2854 }; 2855 2856 larb24: larb@1800d000 { 2857 compatible = "mediatek,mt8195-smi-larb"; 2858 reg = <0 0x1800d000 0 0x1000>; 2859 mediatek,larb-id = <24>; 2860 mediatek,smi = <&smi_common_vdo>; 2861 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2862 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2863 clock-names = "apb", "smi"; 2864 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2865 }; 2866 2867 larb23: larb@1800e000 { 2868 compatible = "mediatek,mt8195-smi-larb"; 2869 reg = <0 0x1800e000 0 0x1000>; 2870 mediatek,larb-id = <23>; 2871 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2872 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2873 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2874 clock-names = "apb", "smi"; 2875 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2876 }; 2877 2878 vdecsys_soc: clock-controller@1800f000 { 2879 compatible = "mediatek,mt8195-vdecsys_soc"; 2880 reg = <0 0x1800f000 0 0x1000>; 2881 #clock-cells = <1>; 2882 }; 2883 2884 larb21: larb@1802e000 { 2885 compatible = "mediatek,mt8195-smi-larb"; 2886 reg = <0 0x1802e000 0 0x1000>; 2887 mediatek,larb-id = <21>; 2888 mediatek,smi = <&smi_common_vdo>; 2889 clocks = <&vdecsys CLK_VDEC_LARB1>, 2890 <&vdecsys CLK_VDEC_LARB1>; 2891 clock-names = "apb", "smi"; 2892 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2893 }; 2894 2895 vdecsys: clock-controller@1802f000 { 2896 compatible = "mediatek,mt8195-vdecsys"; 2897 reg = <0 0x1802f000 0 0x1000>; 2898 #clock-cells = <1>; 2899 }; 2900 2901 larb22: larb@1803e000 { 2902 compatible = "mediatek,mt8195-smi-larb"; 2903 reg = <0 0x1803e000 0 0x1000>; 2904 mediatek,larb-id = <22>; 2905 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2906 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2907 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2908 clock-names = "apb", "smi"; 2909 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2910 }; 2911 2912 vdecsys_core1: clock-controller@1803f000 { 2913 compatible = "mediatek,mt8195-vdecsys_core1"; 2914 reg = <0 0x1803f000 0 0x1000>; 2915 #clock-cells = <1>; 2916 }; 2917 2918 apusys_pll: clock-controller@190f3000 { 2919 compatible = "mediatek,mt8195-apusys_pll"; 2920 reg = <0 0x190f3000 0 0x1000>; 2921 #clock-cells = <1>; 2922 }; 2923 2924 vencsys: clock-controller@1a000000 { 2925 compatible = "mediatek,mt8195-vencsys"; 2926 reg = <0 0x1a000000 0 0x1000>; 2927 #clock-cells = <1>; 2928 }; 2929 2930 larb19: larb@1a010000 { 2931 compatible = "mediatek,mt8195-smi-larb"; 2932 reg = <0 0x1a010000 0 0x1000>; 2933 mediatek,larb-id = <19>; 2934 mediatek,smi = <&smi_common_vdo>; 2935 clocks = <&vencsys CLK_VENC_VENC>, 2936 <&vencsys CLK_VENC_GALS>; 2937 clock-names = "apb", "smi"; 2938 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2939 }; 2940 2941 venc: video-codec@1a020000 { 2942 compatible = "mediatek,mt8195-vcodec-enc"; 2943 reg = <0 0x1a020000 0 0x10000>; 2944 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2945 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2946 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2947 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2948 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2949 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2950 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2951 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2952 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2953 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2954 mediatek,scp = <&scp>; 2955 clocks = <&vencsys CLK_VENC_VENC>; 2956 clock-names = "venc_sel"; 2957 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2958 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2959 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2960 #address-cells = <2>; 2961 #size-cells = <2>; 2962 }; 2963 2964 jpgdec-master { 2965 compatible = "mediatek,mt8195-jpgdec"; 2966 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2967 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2968 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2969 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2970 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2971 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2972 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2973 #address-cells = <2>; 2974 #size-cells = <2>; 2975 ranges; 2976 2977 jpgdec@1a040000 { 2978 compatible = "mediatek,mt8195-jpgdec-hw"; 2979 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2980 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2981 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2982 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2983 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2984 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2985 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2986 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2987 clocks = <&vencsys CLK_VENC_JPGDEC>; 2988 clock-names = "jpgdec"; 2989 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2990 }; 2991 2992 jpgdec@1a050000 { 2993 compatible = "mediatek,mt8195-jpgdec-hw"; 2994 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2995 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2996 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2997 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2998 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2999 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3000 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3001 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3002 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3003 clock-names = "jpgdec"; 3004 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3005 }; 3006 3007 jpgdec@1b040000 { 3008 compatible = "mediatek,mt8195-jpgdec-hw"; 3009 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 3010 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3011 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3012 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3013 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3014 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3015 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3016 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3017 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3018 clock-names = "jpgdec"; 3019 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3020 }; 3021 }; 3022 3023 vencsys_core1: clock-controller@1b000000 { 3024 compatible = "mediatek,mt8195-vencsys_core1"; 3025 reg = <0 0x1b000000 0 0x1000>; 3026 #clock-cells = <1>; 3027 }; 3028 3029 vdosys0: syscon@1c01a000 { 3030 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3031 reg = <0 0x1c01a000 0 0x1000>; 3032 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3033 #clock-cells = <1>; 3034 }; 3035 3036 3037 jpgenc-master { 3038 compatible = "mediatek,mt8195-jpgenc"; 3039 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3040 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3041 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3042 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3043 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3044 #address-cells = <2>; 3045 #size-cells = <2>; 3046 ranges; 3047 3048 jpgenc@1a030000 { 3049 compatible = "mediatek,mt8195-jpgenc-hw"; 3050 reg = <0 0x1a030000 0 0x10000>; 3051 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3052 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3053 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3054 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3055 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3056 clocks = <&vencsys CLK_VENC_JPGENC>; 3057 clock-names = "jpgenc"; 3058 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3059 }; 3060 3061 jpgenc@1b030000 { 3062 compatible = "mediatek,mt8195-jpgenc-hw"; 3063 reg = <0 0x1b030000 0 0x10000>; 3064 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3065 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3066 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3067 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3068 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3069 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3070 clock-names = "jpgenc"; 3071 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3072 }; 3073 }; 3074 3075 larb20: larb@1b010000 { 3076 compatible = "mediatek,mt8195-smi-larb"; 3077 reg = <0 0x1b010000 0 0x1000>; 3078 mediatek,larb-id = <20>; 3079 mediatek,smi = <&smi_common_vpp>; 3080 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 3081 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3082 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3083 clock-names = "apb", "smi", "gals"; 3084 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3085 }; 3086 3087 ovl0: ovl@1c000000 { 3088 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 3089 reg = <0 0x1c000000 0 0x1000>; 3090 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3091 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3092 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3093 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3094 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3095 }; 3096 3097 rdma0: rdma@1c002000 { 3098 compatible = "mediatek,mt8195-disp-rdma"; 3099 reg = <0 0x1c002000 0 0x1000>; 3100 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3101 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3102 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3103 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3104 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3105 }; 3106 3107 color0: color@1c003000 { 3108 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3109 reg = <0 0x1c003000 0 0x1000>; 3110 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3111 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3112 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3113 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3114 }; 3115 3116 ccorr0: ccorr@1c004000 { 3117 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3118 reg = <0 0x1c004000 0 0x1000>; 3119 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3120 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3121 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3122 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3123 }; 3124 3125 aal0: aal@1c005000 { 3126 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3127 reg = <0 0x1c005000 0 0x1000>; 3128 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3129 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3130 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3131 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3132 }; 3133 3134 gamma0: gamma@1c006000 { 3135 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3136 reg = <0 0x1c006000 0 0x1000>; 3137 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3138 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3139 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3140 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3141 }; 3142 3143 dither0: dither@1c007000 { 3144 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3145 reg = <0 0x1c007000 0 0x1000>; 3146 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3148 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3149 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3150 }; 3151 3152 dsi0: dsi@1c008000 { 3153 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3154 reg = <0 0x1c008000 0 0x1000>; 3155 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3156 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3157 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3158 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3159 <&mipi_tx0>; 3160 clock-names = "engine", "digital", "hs"; 3161 phys = <&mipi_tx0>; 3162 phy-names = "dphy"; 3163 status = "disabled"; 3164 }; 3165 3166 dsc0: dsc@1c009000 { 3167 compatible = "mediatek,mt8195-disp-dsc"; 3168 reg = <0 0x1c009000 0 0x1000>; 3169 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3170 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3171 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3172 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3173 }; 3174 3175 dsi1: dsi@1c012000 { 3176 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3177 reg = <0 0x1c012000 0 0x1000>; 3178 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3179 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3180 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3181 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3182 <&mipi_tx1>; 3183 clock-names = "engine", "digital", "hs"; 3184 phys = <&mipi_tx1>; 3185 phy-names = "dphy"; 3186 status = "disabled"; 3187 }; 3188 3189 merge0: merge@1c014000 { 3190 compatible = "mediatek,mt8195-disp-merge"; 3191 reg = <0 0x1c014000 0 0x1000>; 3192 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3193 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3194 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3195 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3196 }; 3197 3198 dp_intf0: dp-intf@1c015000 { 3199 compatible = "mediatek,mt8195-dp-intf"; 3200 reg = <0 0x1c015000 0 0x1000>; 3201 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3202 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 3203 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3204 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3205 clock-names = "engine", "pixel", "pll"; 3206 status = "disabled"; 3207 }; 3208 3209 mutex: mutex@1c016000 { 3210 compatible = "mediatek,mt8195-disp-mutex"; 3211 reg = <0 0x1c016000 0 0x1000>; 3212 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3213 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3214 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3215 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3216 }; 3217 3218 larb0: larb@1c018000 { 3219 compatible = "mediatek,mt8195-smi-larb"; 3220 reg = <0 0x1c018000 0 0x1000>; 3221 mediatek,larb-id = <0>; 3222 mediatek,smi = <&smi_common_vdo>; 3223 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3224 <&vdosys0 CLK_VDO0_SMI_LARB>, 3225 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3226 clock-names = "apb", "smi", "gals"; 3227 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3228 }; 3229 3230 larb1: larb@1c019000 { 3231 compatible = "mediatek,mt8195-smi-larb"; 3232 reg = <0 0x1c019000 0 0x1000>; 3233 mediatek,larb-id = <1>; 3234 mediatek,smi = <&smi_common_vpp>; 3235 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3236 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3237 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3238 clock-names = "apb", "smi", "gals"; 3239 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3240 }; 3241 3242 vdosys1: syscon@1c100000 { 3243 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3244 reg = <0 0x1c100000 0 0x1000>; 3245 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3246 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3247 #clock-cells = <1>; 3248 #reset-cells = <1>; 3249 }; 3250 3251 smi_common_vdo: smi@1c01b000 { 3252 compatible = "mediatek,mt8195-smi-common-vdo"; 3253 reg = <0 0x1c01b000 0 0x1000>; 3254 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3255 <&vdosys0 CLK_VDO0_SMI_EMI>, 3256 <&vdosys0 CLK_VDO0_SMI_RSI>, 3257 <&vdosys0 CLK_VDO0_SMI_GALS>; 3258 clock-names = "apb", "smi", "gals0", "gals1"; 3259 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3260 3261 }; 3262 3263 iommu_vdo: iommu@1c01f000 { 3264 compatible = "mediatek,mt8195-iommu-vdo"; 3265 reg = <0 0x1c01f000 0 0x1000>; 3266 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3267 &larb10 &larb11 &larb13 &larb17 3268 &larb19 &larb21 &larb24 &larb25 3269 &larb28>; 3270 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3271 #iommu-cells = <1>; 3272 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3273 clock-names = "bclk"; 3274 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3275 }; 3276 3277 mutex1: mutex@1c101000 { 3278 compatible = "mediatek,mt8195-disp-mutex"; 3279 reg = <0 0x1c101000 0 0x1000>; 3280 reg-names = "vdo1_mutex"; 3281 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3282 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3283 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3284 clock-names = "vdo1_mutex"; 3285 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3286 }; 3287 3288 larb2: larb@1c102000 { 3289 compatible = "mediatek,mt8195-smi-larb"; 3290 reg = <0 0x1c102000 0 0x1000>; 3291 mediatek,larb-id = <2>; 3292 mediatek,smi = <&smi_common_vdo>; 3293 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3294 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3295 <&vdosys1 CLK_VDO1_GALS>; 3296 clock-names = "apb", "smi", "gals"; 3297 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3298 }; 3299 3300 larb3: larb@1c103000 { 3301 compatible = "mediatek,mt8195-smi-larb"; 3302 reg = <0 0x1c103000 0 0x1000>; 3303 mediatek,larb-id = <3>; 3304 mediatek,smi = <&smi_common_vpp>; 3305 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3306 <&vdosys1 CLK_VDO1_GALS>, 3307 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3308 clock-names = "apb", "smi", "gals"; 3309 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3310 }; 3311 3312 vdo1_rdma0: dma-controller@1c104000 { 3313 compatible = "mediatek,mt8195-vdo1-rdma"; 3314 reg = <0 0x1c104000 0 0x1000>; 3315 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3316 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3317 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3318 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3319 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3320 #dma-cells = <1>; 3321 }; 3322 3323 vdo1_rdma1: dma-controller@1c105000 { 3324 compatible = "mediatek,mt8195-vdo1-rdma"; 3325 reg = <0 0x1c105000 0 0x1000>; 3326 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3327 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3328 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3329 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3330 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3331 #dma-cells = <1>; 3332 }; 3333 3334 vdo1_rdma2: dma-controller@1c106000 { 3335 compatible = "mediatek,mt8195-vdo1-rdma"; 3336 reg = <0 0x1c106000 0 0x1000>; 3337 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3338 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3339 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3340 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3341 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3342 #dma-cells = <1>; 3343 }; 3344 3345 vdo1_rdma3: dma-controller@1c107000 { 3346 compatible = "mediatek,mt8195-vdo1-rdma"; 3347 reg = <0 0x1c107000 0 0x1000>; 3348 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3349 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3350 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3351 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3352 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3353 #dma-cells = <1>; 3354 }; 3355 3356 vdo1_rdma4: dma-controller@1c108000 { 3357 compatible = "mediatek,mt8195-vdo1-rdma"; 3358 reg = <0 0x1c108000 0 0x1000>; 3359 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3360 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3361 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3362 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3363 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3364 #dma-cells = <1>; 3365 }; 3366 3367 vdo1_rdma5: dma-controller@1c109000 { 3368 compatible = "mediatek,mt8195-vdo1-rdma"; 3369 reg = <0 0x1c109000 0 0x1000>; 3370 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3371 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3372 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3373 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3374 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3375 #dma-cells = <1>; 3376 }; 3377 3378 vdo1_rdma6: dma-controller@1c10a000 { 3379 compatible = "mediatek,mt8195-vdo1-rdma"; 3380 reg = <0 0x1c10a000 0 0x1000>; 3381 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3382 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3383 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3384 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3385 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3386 #dma-cells = <1>; 3387 }; 3388 3389 vdo1_rdma7: dma-controller@1c10b000 { 3390 compatible = "mediatek,mt8195-vdo1-rdma"; 3391 reg = <0 0x1c10b000 0 0x1000>; 3392 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3393 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3394 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3395 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3396 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3397 #dma-cells = <1>; 3398 }; 3399 3400 merge1: vpp-merge@1c10c000 { 3401 compatible = "mediatek,mt8195-disp-merge"; 3402 reg = <0 0x1c10c000 0 0x1000>; 3403 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3404 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3405 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3406 clock-names = "merge","merge_async"; 3407 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3408 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3409 mediatek,merge-mute; 3410 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3411 }; 3412 3413 merge2: vpp-merge@1c10d000 { 3414 compatible = "mediatek,mt8195-disp-merge"; 3415 reg = <0 0x1c10d000 0 0x1000>; 3416 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3417 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3418 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3419 clock-names = "merge","merge_async"; 3420 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3421 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3422 mediatek,merge-mute; 3423 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3424 }; 3425 3426 merge3: vpp-merge@1c10e000 { 3427 compatible = "mediatek,mt8195-disp-merge"; 3428 reg = <0 0x1c10e000 0 0x1000>; 3429 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3430 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3431 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3432 clock-names = "merge","merge_async"; 3433 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3434 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3435 mediatek,merge-mute; 3436 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3437 }; 3438 3439 merge4: vpp-merge@1c10f000 { 3440 compatible = "mediatek,mt8195-disp-merge"; 3441 reg = <0 0x1c10f000 0 0x1000>; 3442 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3443 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3444 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3445 clock-names = "merge","merge_async"; 3446 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3447 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3448 mediatek,merge-mute; 3449 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3450 }; 3451 3452 merge5: vpp-merge@1c110000 { 3453 compatible = "mediatek,mt8195-disp-merge"; 3454 reg = <0 0x1c110000 0 0x1000>; 3455 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3456 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3457 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3458 clock-names = "merge","merge_async"; 3459 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3460 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3461 mediatek,merge-fifo-en; 3462 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3463 }; 3464 3465 dp_intf1: dp-intf@1c113000 { 3466 compatible = "mediatek,mt8195-dp-intf"; 3467 reg = <0 0x1c113000 0 0x1000>; 3468 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3469 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3470 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3471 <&vdosys1 CLK_VDO1_DPINTF>, 3472 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3473 clock-names = "engine", "pixel", "pll"; 3474 status = "disabled"; 3475 }; 3476 3477 ethdr0: hdr-engine@1c114000 { 3478 compatible = "mediatek,mt8195-disp-ethdr"; 3479 reg = <0 0x1c114000 0 0x1000>, 3480 <0 0x1c115000 0 0x1000>, 3481 <0 0x1c117000 0 0x1000>, 3482 <0 0x1c119000 0 0x1000>, 3483 <0 0x1c11a000 0 0x1000>, 3484 <0 0x1c11b000 0 0x1000>, 3485 <0 0x1c11c000 0 0x1000>; 3486 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3487 "vdo_be", "adl_ds"; 3488 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3489 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3490 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3491 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3492 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3493 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3494 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3495 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3496 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3497 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3498 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3499 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3500 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3501 <&vdosys1 CLK_VDO1_26M_SLOW>, 3502 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3503 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3504 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3505 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3506 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3507 <&topckgen CLK_TOP_ETHDR>; 3508 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3509 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3510 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3511 "ethdr_top"; 3512 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3513 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3514 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3515 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3516 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3517 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3518 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3519 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3520 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3521 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3522 "gfx_fe1_async", "vdo_be_async"; 3523 }; 3524 3525 edp_tx: edp-tx@1c500000 { 3526 compatible = "mediatek,mt8195-edp-tx"; 3527 reg = <0 0x1c500000 0 0x8000>; 3528 nvmem-cells = <&dp_calibration>; 3529 nvmem-cell-names = "dp_calibration_data"; 3530 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3531 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3532 max-linkrate-mhz = <8100>; 3533 status = "disabled"; 3534 }; 3535 3536 dp_tx: dp-tx@1c600000 { 3537 compatible = "mediatek,mt8195-dp-tx"; 3538 reg = <0 0x1c600000 0 0x8000>; 3539 nvmem-cells = <&dp_calibration>; 3540 nvmem-cell-names = "dp_calibration_data"; 3541 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3542 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3543 max-linkrate-mhz = <8100>; 3544 status = "disabled"; 3545 }; 3546 }; 3547 3548 thermal_zones: thermal-zones { 3549 cpu0-thermal { 3550 polling-delay = <1000>; 3551 polling-delay-passive = <250>; 3552 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3553 3554 trips { 3555 cpu0_alert: trip-alert { 3556 temperature = <85000>; 3557 hysteresis = <2000>; 3558 type = "passive"; 3559 }; 3560 3561 cpu0_crit: trip-crit { 3562 temperature = <100000>; 3563 hysteresis = <2000>; 3564 type = "critical"; 3565 }; 3566 }; 3567 3568 cooling-maps { 3569 map0 { 3570 trip = <&cpu0_alert>; 3571 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3572 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3573 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3574 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3575 }; 3576 }; 3577 }; 3578 3579 cpu1-thermal { 3580 polling-delay = <1000>; 3581 polling-delay-passive = <250>; 3582 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3583 3584 trips { 3585 cpu1_alert: trip-alert { 3586 temperature = <85000>; 3587 hysteresis = <2000>; 3588 type = "passive"; 3589 }; 3590 3591 cpu1_crit: trip-crit { 3592 temperature = <100000>; 3593 hysteresis = <2000>; 3594 type = "critical"; 3595 }; 3596 }; 3597 3598 cooling-maps { 3599 map0 { 3600 trip = <&cpu1_alert>; 3601 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3602 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3603 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3604 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3605 }; 3606 }; 3607 }; 3608 3609 cpu2-thermal { 3610 polling-delay = <1000>; 3611 polling-delay-passive = <250>; 3612 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3613 3614 trips { 3615 cpu2_alert: trip-alert { 3616 temperature = <85000>; 3617 hysteresis = <2000>; 3618 type = "passive"; 3619 }; 3620 3621 cpu2_crit: trip-crit { 3622 temperature = <100000>; 3623 hysteresis = <2000>; 3624 type = "critical"; 3625 }; 3626 }; 3627 3628 cooling-maps { 3629 map0 { 3630 trip = <&cpu2_alert>; 3631 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3635 }; 3636 }; 3637 }; 3638 3639 cpu3-thermal { 3640 polling-delay = <1000>; 3641 polling-delay-passive = <250>; 3642 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3643 3644 trips { 3645 cpu3_alert: trip-alert { 3646 temperature = <85000>; 3647 hysteresis = <2000>; 3648 type = "passive"; 3649 }; 3650 3651 cpu3_crit: trip-crit { 3652 temperature = <100000>; 3653 hysteresis = <2000>; 3654 type = "critical"; 3655 }; 3656 }; 3657 3658 cooling-maps { 3659 map0 { 3660 trip = <&cpu3_alert>; 3661 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3662 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3663 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3664 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3665 }; 3666 }; 3667 }; 3668 3669 cpu4-thermal { 3670 polling-delay = <1000>; 3671 polling-delay-passive = <250>; 3672 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3673 3674 trips { 3675 cpu4_alert: trip-alert { 3676 temperature = <85000>; 3677 hysteresis = <2000>; 3678 type = "passive"; 3679 }; 3680 3681 cpu4_crit: trip-crit { 3682 temperature = <100000>; 3683 hysteresis = <2000>; 3684 type = "critical"; 3685 }; 3686 }; 3687 3688 cooling-maps { 3689 map0 { 3690 trip = <&cpu4_alert>; 3691 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3694 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3695 }; 3696 }; 3697 }; 3698 3699 cpu5-thermal { 3700 polling-delay = <1000>; 3701 polling-delay-passive = <250>; 3702 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3703 3704 trips { 3705 cpu5_alert: trip-alert { 3706 temperature = <85000>; 3707 hysteresis = <2000>; 3708 type = "passive"; 3709 }; 3710 3711 cpu5_crit: trip-crit { 3712 temperature = <100000>; 3713 hysteresis = <2000>; 3714 type = "critical"; 3715 }; 3716 }; 3717 3718 cooling-maps { 3719 map0 { 3720 trip = <&cpu5_alert>; 3721 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3725 }; 3726 }; 3727 }; 3728 3729 cpu6-thermal { 3730 polling-delay = <1000>; 3731 polling-delay-passive = <250>; 3732 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3733 3734 trips { 3735 cpu6_alert: trip-alert { 3736 temperature = <85000>; 3737 hysteresis = <2000>; 3738 type = "passive"; 3739 }; 3740 3741 cpu6_crit: trip-crit { 3742 temperature = <100000>; 3743 hysteresis = <2000>; 3744 type = "critical"; 3745 }; 3746 }; 3747 3748 cooling-maps { 3749 map0 { 3750 trip = <&cpu6_alert>; 3751 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3752 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3753 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3755 }; 3756 }; 3757 }; 3758 3759 cpu7-thermal { 3760 polling-delay = <1000>; 3761 polling-delay-passive = <250>; 3762 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3763 3764 trips { 3765 cpu7_alert: trip-alert { 3766 temperature = <85000>; 3767 hysteresis = <2000>; 3768 type = "passive"; 3769 }; 3770 3771 cpu7_crit: trip-crit { 3772 temperature = <100000>; 3773 hysteresis = <2000>; 3774 type = "critical"; 3775 }; 3776 }; 3777 3778 cooling-maps { 3779 map0 { 3780 trip = <&cpu7_alert>; 3781 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3785 }; 3786 }; 3787 }; 3788 3789 vpu0-thermal { 3790 polling-delay = <1000>; 3791 polling-delay-passive = <250>; 3792 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3793 3794 trips { 3795 vpu0_alert: trip-alert { 3796 temperature = <85000>; 3797 hysteresis = <2000>; 3798 type = "passive"; 3799 }; 3800 3801 vpu0_crit: trip-crit { 3802 temperature = <100000>; 3803 hysteresis = <2000>; 3804 type = "critical"; 3805 }; 3806 }; 3807 }; 3808 3809 vpu1-thermal { 3810 polling-delay = <1000>; 3811 polling-delay-passive = <250>; 3812 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3813 3814 trips { 3815 vpu1_alert: trip-alert { 3816 temperature = <85000>; 3817 hysteresis = <2000>; 3818 type = "passive"; 3819 }; 3820 3821 vpu1_crit: trip-crit { 3822 temperature = <100000>; 3823 hysteresis = <2000>; 3824 type = "critical"; 3825 }; 3826 }; 3827 }; 3828 3829 gpu0-thermal { 3830 polling-delay = <1000>; 3831 polling-delay-passive = <250>; 3832 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3833 3834 trips { 3835 gpu0_alert: trip-alert { 3836 temperature = <85000>; 3837 hysteresis = <2000>; 3838 type = "passive"; 3839 }; 3840 3841 gpu0_crit: trip-crit { 3842 temperature = <100000>; 3843 hysteresis = <2000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 }; 3848 3849 gpu1-thermal { 3850 polling-delay = <1000>; 3851 polling-delay-passive = <250>; 3852 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3853 3854 trips { 3855 gpu1_alert: trip-alert { 3856 temperature = <85000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 gpu1_crit: trip-crit { 3862 temperature = <100000>; 3863 hysteresis = <2000>; 3864 type = "critical"; 3865 }; 3866 }; 3867 }; 3868 3869 vdec-thermal { 3870 polling-delay = <1000>; 3871 polling-delay-passive = <250>; 3872 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3873 3874 trips { 3875 vdec_alert: trip-alert { 3876 temperature = <85000>; 3877 hysteresis = <2000>; 3878 type = "passive"; 3879 }; 3880 3881 vdec_crit: trip-crit { 3882 temperature = <100000>; 3883 hysteresis = <2000>; 3884 type = "critical"; 3885 }; 3886 }; 3887 }; 3888 3889 img-thermal { 3890 polling-delay = <1000>; 3891 polling-delay-passive = <250>; 3892 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3893 3894 trips { 3895 img_alert: trip-alert { 3896 temperature = <85000>; 3897 hysteresis = <2000>; 3898 type = "passive"; 3899 }; 3900 3901 img_crit: trip-crit { 3902 temperature = <100000>; 3903 hysteresis = <2000>; 3904 type = "critical"; 3905 }; 3906 }; 3907 }; 3908 3909 infra-thermal { 3910 polling-delay = <1000>; 3911 polling-delay-passive = <250>; 3912 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3913 3914 trips { 3915 infra_alert: trip-alert { 3916 temperature = <85000>; 3917 hysteresis = <2000>; 3918 type = "passive"; 3919 }; 3920 3921 infra_crit: trip-crit { 3922 temperature = <100000>; 3923 hysteresis = <2000>; 3924 type = "critical"; 3925 }; 3926 }; 3927 }; 3928 3929 cam0-thermal { 3930 polling-delay = <1000>; 3931 polling-delay-passive = <250>; 3932 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3933 3934 trips { 3935 cam0_alert: trip-alert { 3936 temperature = <85000>; 3937 hysteresis = <2000>; 3938 type = "passive"; 3939 }; 3940 3941 cam0_crit: trip-crit { 3942 temperature = <100000>; 3943 hysteresis = <2000>; 3944 type = "critical"; 3945 }; 3946 }; 3947 }; 3948 3949 cam1-thermal { 3950 polling-delay = <1000>; 3951 polling-delay-passive = <250>; 3952 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 3953 3954 trips { 3955 cam1_alert: trip-alert { 3956 temperature = <85000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cam1_crit: trip-crit { 3962 temperature = <100000>; 3963 hysteresis = <2000>; 3964 type = "critical"; 3965 }; 3966 }; 3967 }; 3968 }; 3969}; 3970