1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 621 reg = <MT8195_POWER_DOMAIN_VDEC1>; 622 clocks = <&vdecsys CLK_VDEC_LARB1>; 623 clock-names = "vdec1-0"; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 630 mediatek,infracfg = <&infracfg_ao>; 631 #power-domain-cells = <0>; 632 }; 633 634 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 635 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 636 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 637 <&vdosys0 CLK_VDO0_SMI_GALS>, 638 <&vdosys0 CLK_VDO0_SMI_COMMON>, 639 <&vdosys0 CLK_VDO0_SMI_EMI>, 640 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 641 <&vdosys0 CLK_VDO0_SMI_LARB>, 642 <&vdosys0 CLK_VDO0_SMI_RSI>; 643 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 644 "vdosys0-2", "vdosys0-3", 645 "vdosys0-4", "vdosys0-5"; 646 mediatek,infracfg = <&infracfg_ao>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 #power-domain-cells = <1>; 650 651 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 652 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 653 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 654 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 655 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 656 clock-names = "vppsys1", "vppsys1-0", 657 "vppsys1-1"; 658 mediatek,infracfg = <&infracfg_ao>; 659 #power-domain-cells = <0>; 660 }; 661 662 power-domain@MT8195_POWER_DOMAIN_WPESYS { 663 reg = <MT8195_POWER_DOMAIN_WPESYS>; 664 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 665 <&wpesys CLK_WPE_SMI_LARB8>, 666 <&wpesys CLK_WPE_SMI_LARB7_P>, 667 <&wpesys CLK_WPE_SMI_LARB8_P>; 668 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 669 "wepsys-3"; 670 mediatek,infracfg = <&infracfg_ao>; 671 #power-domain-cells = <0>; 672 }; 673 674 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 675 reg = <MT8195_POWER_DOMAIN_VDEC0>; 676 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 677 clock-names = "vdec0-0"; 678 mediatek,infracfg = <&infracfg_ao>; 679 #power-domain-cells = <0>; 680 }; 681 682 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 683 reg = <MT8195_POWER_DOMAIN_VDEC2>; 684 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 685 clock-names = "vdec2-0"; 686 mediatek,infracfg = <&infracfg_ao>; 687 #power-domain-cells = <0>; 688 }; 689 690 power-domain@MT8195_POWER_DOMAIN_VENC { 691 reg = <MT8195_POWER_DOMAIN_VENC>; 692 mediatek,infracfg = <&infracfg_ao>; 693 #power-domain-cells = <0>; 694 }; 695 696 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 697 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 698 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 699 <&vdosys1 CLK_VDO1_SMI_LARB2>, 700 <&vdosys1 CLK_VDO1_SMI_LARB3>, 701 <&vdosys1 CLK_VDO1_GALS>; 702 clock-names = "vdosys1", "vdosys1-0", 703 "vdosys1-1", "vdosys1-2"; 704 mediatek,infracfg = <&infracfg_ao>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 #power-domain-cells = <1>; 708 709 power-domain@MT8195_POWER_DOMAIN_DP_TX { 710 reg = <MT8195_POWER_DOMAIN_DP_TX>; 711 mediatek,infracfg = <&infracfg_ao>; 712 #power-domain-cells = <0>; 713 }; 714 715 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 716 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 717 mediatek,infracfg = <&infracfg_ao>; 718 #power-domain-cells = <0>; 719 }; 720 721 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 722 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 723 clocks = <&topckgen CLK_TOP_HDMI_APB>; 724 clock-names = "hdmi_tx"; 725 #power-domain-cells = <0>; 726 }; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_IMG { 730 reg = <MT8195_POWER_DOMAIN_IMG>; 731 clocks = <&imgsys CLK_IMG_LARB9>, 732 <&imgsys CLK_IMG_GALS>; 733 clock-names = "img-0", "img-1"; 734 mediatek,infracfg = <&infracfg_ao>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 #power-domain-cells = <1>; 738 739 power-domain@MT8195_POWER_DOMAIN_DIP { 740 reg = <MT8195_POWER_DOMAIN_DIP>; 741 #power-domain-cells = <0>; 742 }; 743 744 power-domain@MT8195_POWER_DOMAIN_IPE { 745 reg = <MT8195_POWER_DOMAIN_IPE>; 746 clocks = <&topckgen CLK_TOP_IPE>, 747 <&imgsys CLK_IMG_IPE>, 748 <&ipesys CLK_IPE_SMI_LARB12>; 749 clock-names = "ipe", "ipe-0", "ipe-1"; 750 mediatek,infracfg = <&infracfg_ao>; 751 #power-domain-cells = <0>; 752 }; 753 }; 754 755 power-domain@MT8195_POWER_DOMAIN_CAM { 756 reg = <MT8195_POWER_DOMAIN_CAM>; 757 clocks = <&camsys CLK_CAM_LARB13>, 758 <&camsys CLK_CAM_LARB14>, 759 <&camsys CLK_CAM_CAM2MM0_GALS>, 760 <&camsys CLK_CAM_CAM2MM1_GALS>, 761 <&camsys CLK_CAM_CAM2SYS_GALS>; 762 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 763 "cam-4"; 764 mediatek,infracfg = <&infracfg_ao>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 #power-domain-cells = <1>; 768 769 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 770 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 771 #power-domain-cells = <0>; 772 }; 773 774 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 775 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 776 #power-domain-cells = <0>; 777 }; 778 779 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 780 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 781 #power-domain-cells = <0>; 782 }; 783 }; 784 }; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 788 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 789 mediatek,infracfg = <&infracfg_ao>; 790 #power-domain-cells = <0>; 791 }; 792 793 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 794 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 795 mediatek,infracfg = <&infracfg_ao>; 796 #power-domain-cells = <0>; 797 }; 798 799 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 800 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 801 #power-domain-cells = <0>; 802 }; 803 804 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 805 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 806 #power-domain-cells = <0>; 807 }; 808 809 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 810 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 811 clocks = <&topckgen CLK_TOP_SENINF>, 812 <&topckgen CLK_TOP_SENINF2>; 813 clock-names = "csi_rx_top", "csi_rx_top1"; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_ETHER { 818 reg = <MT8195_POWER_DOMAIN_ETHER>; 819 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 820 clock-names = "ether"; 821 #power-domain-cells = <0>; 822 }; 823 824 power-domain@MT8195_POWER_DOMAIN_ADSP { 825 reg = <MT8195_POWER_DOMAIN_ADSP>; 826 clocks = <&topckgen CLK_TOP_ADSP>, 827 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 828 clock-names = "adsp", "adsp1"; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 mediatek,infracfg = <&infracfg_ao>; 832 #power-domain-cells = <1>; 833 834 power-domain@MT8195_POWER_DOMAIN_AUDIO { 835 reg = <MT8195_POWER_DOMAIN_AUDIO>; 836 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 837 <&topckgen CLK_TOP_AUD_INTBUS>, 838 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 839 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 840 clock-names = "audio", "audio1", "audio2", 841 "audio3"; 842 mediatek,infracfg = <&infracfg_ao>; 843 #power-domain-cells = <0>; 844 }; 845 }; 846 }; 847 }; 848 849 watchdog: watchdog@10007000 { 850 compatible = "mediatek,mt8195-wdt"; 851 mediatek,disable-extrst; 852 reg = <0 0x10007000 0 0x100>; 853 #reset-cells = <1>; 854 }; 855 856 apmixedsys: syscon@1000c000 { 857 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 858 reg = <0 0x1000c000 0 0x1000>; 859 #clock-cells = <1>; 860 }; 861 862 systimer: timer@10017000 { 863 compatible = "mediatek,mt8195-timer", 864 "mediatek,mt6765-timer"; 865 reg = <0 0x10017000 0 0x1000>; 866 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 867 clocks = <&clk13m>; 868 }; 869 870 pwrap: pwrap@10024000 { 871 compatible = "mediatek,mt8195-pwrap", "syscon"; 872 reg = <0 0x10024000 0 0x1000>; 873 reg-names = "pwrap"; 874 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 876 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 877 clock-names = "spi", "wrap"; 878 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 879 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 880 }; 881 882 spmi: spmi@10027000 { 883 compatible = "mediatek,mt8195-spmi"; 884 reg = <0 0x10027000 0 0x000e00>, 885 <0 0x10029000 0 0x000100>; 886 reg-names = "pmif", "spmimst"; 887 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 888 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 889 <&topckgen CLK_TOP_SPMI_M_MST>; 890 clock-names = "pmif_sys_ck", 891 "pmif_tmr_ck", 892 "spmimst_clk_mux"; 893 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 894 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 895 }; 896 897 iommu_infra: infra-iommu@10315000 { 898 compatible = "mediatek,mt8195-iommu-infra"; 899 reg = <0 0x10315000 0 0x5000>; 900 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 901 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 902 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 903 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 904 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 905 #iommu-cells = <1>; 906 }; 907 908 gce0: mailbox@10320000 { 909 compatible = "mediatek,mt8195-gce"; 910 reg = <0 0x10320000 0 0x4000>; 911 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 912 #mbox-cells = <2>; 913 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 914 }; 915 916 gce1: mailbox@10330000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10330000 0 0x4000>; 919 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 922 }; 923 924 scp: scp@10500000 { 925 compatible = "mediatek,mt8195-scp"; 926 reg = <0 0x10500000 0 0x100000>, 927 <0 0x10720000 0 0xe0000>, 928 <0 0x10700000 0 0x8000>; 929 reg-names = "sram", "cfg", "l1tcm"; 930 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 931 status = "disabled"; 932 }; 933 934 scp_adsp: clock-controller@10720000 { 935 compatible = "mediatek,mt8195-scp_adsp"; 936 reg = <0 0x10720000 0 0x1000>; 937 #clock-cells = <1>; 938 }; 939 940 adsp: dsp@10803000 { 941 compatible = "mediatek,mt8195-dsp"; 942 reg = <0 0x10803000 0 0x1000>, 943 <0 0x10840000 0 0x40000>; 944 reg-names = "cfg", "sram"; 945 clocks = <&topckgen CLK_TOP_ADSP>, 946 <&clk26m>, 947 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 948 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 949 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 950 <&topckgen CLK_TOP_AUDIO_H>; 951 clock-names = "adsp_sel", 952 "clk26m_ck", 953 "audio_local_bus", 954 "mainpll_d7_d2", 955 "scp_adsp_audiodsp", 956 "audio_h"; 957 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 958 mbox-names = "rx", "tx"; 959 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 960 status = "disabled"; 961 }; 962 963 adsp_mailbox0: mailbox@10816000 { 964 compatible = "mediatek,mt8195-adsp-mbox"; 965 #mbox-cells = <0>; 966 reg = <0 0x10816000 0 0x1000>; 967 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 968 }; 969 970 adsp_mailbox1: mailbox@10817000 { 971 compatible = "mediatek,mt8195-adsp-mbox"; 972 #mbox-cells = <0>; 973 reg = <0 0x10817000 0 0x1000>; 974 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 975 }; 976 977 afe: mt8195-afe-pcm@10890000 { 978 compatible = "mediatek,mt8195-audio"; 979 reg = <0 0x10890000 0 0x10000>; 980 mediatek,topckgen = <&topckgen>; 981 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 982 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 983 resets = <&watchdog 14>; 984 reset-names = "audiosys"; 985 clocks = <&clk26m>, 986 <&apmixedsys CLK_APMIXED_APLL1>, 987 <&apmixedsys CLK_APMIXED_APLL2>, 988 <&topckgen CLK_TOP_APLL12_DIV0>, 989 <&topckgen CLK_TOP_APLL12_DIV1>, 990 <&topckgen CLK_TOP_APLL12_DIV2>, 991 <&topckgen CLK_TOP_APLL12_DIV3>, 992 <&topckgen CLK_TOP_APLL12_DIV9>, 993 <&topckgen CLK_TOP_A1SYS_HP>, 994 <&topckgen CLK_TOP_AUD_INTBUS>, 995 <&topckgen CLK_TOP_AUDIO_H>, 996 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 997 <&topckgen CLK_TOP_DPTX_MCK>, 998 <&topckgen CLK_TOP_I2SO1_MCK>, 999 <&topckgen CLK_TOP_I2SO2_MCK>, 1000 <&topckgen CLK_TOP_I2SI1_MCK>, 1001 <&topckgen CLK_TOP_I2SI2_MCK>, 1002 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1003 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1004 clock-names = "clk26m", 1005 "apll1_ck", 1006 "apll2_ck", 1007 "apll12_div0", 1008 "apll12_div1", 1009 "apll12_div2", 1010 "apll12_div3", 1011 "apll12_div9", 1012 "a1sys_hp_sel", 1013 "aud_intbus_sel", 1014 "audio_h_sel", 1015 "audio_local_bus_sel", 1016 "dptx_m_sel", 1017 "i2so1_m_sel", 1018 "i2so2_m_sel", 1019 "i2si1_m_sel", 1020 "i2si2_m_sel", 1021 "infra_ao_audio_26m_b", 1022 "scp_adsp_audiodsp"; 1023 status = "disabled"; 1024 }; 1025 1026 uart0: serial@11001100 { 1027 compatible = "mediatek,mt8195-uart", 1028 "mediatek,mt6577-uart"; 1029 reg = <0 0x11001100 0 0x100>; 1030 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1032 clock-names = "baud", "bus"; 1033 status = "disabled"; 1034 }; 1035 1036 uart1: serial@11001200 { 1037 compatible = "mediatek,mt8195-uart", 1038 "mediatek,mt6577-uart"; 1039 reg = <0 0x11001200 0 0x100>; 1040 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1041 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1042 clock-names = "baud", "bus"; 1043 status = "disabled"; 1044 }; 1045 1046 uart2: serial@11001300 { 1047 compatible = "mediatek,mt8195-uart", 1048 "mediatek,mt6577-uart"; 1049 reg = <0 0x11001300 0 0x100>; 1050 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1051 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1052 clock-names = "baud", "bus"; 1053 status = "disabled"; 1054 }; 1055 1056 uart3: serial@11001400 { 1057 compatible = "mediatek,mt8195-uart", 1058 "mediatek,mt6577-uart"; 1059 reg = <0 0x11001400 0 0x100>; 1060 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1061 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1062 clock-names = "baud", "bus"; 1063 status = "disabled"; 1064 }; 1065 1066 uart4: serial@11001500 { 1067 compatible = "mediatek,mt8195-uart", 1068 "mediatek,mt6577-uart"; 1069 reg = <0 0x11001500 0 0x100>; 1070 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1071 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1072 clock-names = "baud", "bus"; 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@11001600 { 1077 compatible = "mediatek,mt8195-uart", 1078 "mediatek,mt6577-uart"; 1079 reg = <0 0x11001600 0 0x100>; 1080 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1081 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1082 clock-names = "baud", "bus"; 1083 status = "disabled"; 1084 }; 1085 1086 auxadc: auxadc@11002000 { 1087 compatible = "mediatek,mt8195-auxadc", 1088 "mediatek,mt8173-auxadc"; 1089 reg = <0 0x11002000 0 0x1000>; 1090 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1091 clock-names = "main"; 1092 #io-channel-cells = <1>; 1093 status = "disabled"; 1094 }; 1095 1096 pericfg_ao: syscon@11003000 { 1097 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1098 reg = <0 0x11003000 0 0x1000>; 1099 #clock-cells = <1>; 1100 }; 1101 1102 spi0: spi@1100a000 { 1103 compatible = "mediatek,mt8195-spi", 1104 "mediatek,mt6765-spi"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 reg = <0 0x1100a000 0 0x1000>; 1108 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1109 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1110 <&topckgen CLK_TOP_SPI>, 1111 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1112 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1113 status = "disabled"; 1114 }; 1115 1116 lvts_ap: thermal-sensor@1100b000 { 1117 compatible = "mediatek,mt8195-lvts-ap"; 1118 reg = <0 0x1100b000 0 0xc00>; 1119 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1120 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1121 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1122 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1123 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1124 #thermal-sensor-cells = <1>; 1125 }; 1126 1127 svs: svs@1100bc00 { 1128 compatible = "mediatek,mt8195-svs"; 1129 reg = <0 0x1100bc00 0 0x400>; 1130 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; 1131 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1132 clock-names = "main"; 1133 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; 1134 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1135 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 1136 reset-names = "svs_rst"; 1137 }; 1138 1139 disp_pwm0: pwm@1100e000 { 1140 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1141 reg = <0 0x1100e000 0 0x1000>; 1142 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1143 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1144 #pwm-cells = <2>; 1145 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1146 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1147 clock-names = "main", "mm"; 1148 status = "disabled"; 1149 }; 1150 1151 disp_pwm1: pwm@1100f000 { 1152 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1153 reg = <0 0x1100f000 0 0x1000>; 1154 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1155 #pwm-cells = <2>; 1156 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1157 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1158 clock-names = "main", "mm"; 1159 status = "disabled"; 1160 }; 1161 1162 spi1: spi@11010000 { 1163 compatible = "mediatek,mt8195-spi", 1164 "mediatek,mt6765-spi"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 reg = <0 0x11010000 0 0x1000>; 1168 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1169 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1170 <&topckgen CLK_TOP_SPI>, 1171 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1172 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1173 status = "disabled"; 1174 }; 1175 1176 spi2: spi@11012000 { 1177 compatible = "mediatek,mt8195-spi", 1178 "mediatek,mt6765-spi"; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 reg = <0 0x11012000 0 0x1000>; 1182 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1183 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1184 <&topckgen CLK_TOP_SPI>, 1185 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1186 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1187 status = "disabled"; 1188 }; 1189 1190 spi3: spi@11013000 { 1191 compatible = "mediatek,mt8195-spi", 1192 "mediatek,mt6765-spi"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 reg = <0 0x11013000 0 0x1000>; 1196 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1197 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1198 <&topckgen CLK_TOP_SPI>, 1199 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1200 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1201 status = "disabled"; 1202 }; 1203 1204 spi4: spi@11018000 { 1205 compatible = "mediatek,mt8195-spi", 1206 "mediatek,mt6765-spi"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 reg = <0 0x11018000 0 0x1000>; 1210 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1211 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1212 <&topckgen CLK_TOP_SPI>, 1213 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1214 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1215 status = "disabled"; 1216 }; 1217 1218 spi5: spi@11019000 { 1219 compatible = "mediatek,mt8195-spi", 1220 "mediatek,mt6765-spi"; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 reg = <0 0x11019000 0 0x1000>; 1224 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1225 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1226 <&topckgen CLK_TOP_SPI>, 1227 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1228 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1229 status = "disabled"; 1230 }; 1231 1232 spis0: spi@1101d000 { 1233 compatible = "mediatek,mt8195-spi-slave"; 1234 reg = <0 0x1101d000 0 0x1000>; 1235 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1236 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1237 clock-names = "spi"; 1238 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1239 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1240 status = "disabled"; 1241 }; 1242 1243 spis1: spi@1101e000 { 1244 compatible = "mediatek,mt8195-spi-slave"; 1245 reg = <0 0x1101e000 0 0x1000>; 1246 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1247 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1248 clock-names = "spi"; 1249 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1250 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1251 status = "disabled"; 1252 }; 1253 1254 eth: ethernet@11021000 { 1255 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1256 reg = <0 0x11021000 0 0x4000>; 1257 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1258 interrupt-names = "macirq"; 1259 clock-names = "axi", 1260 "apb", 1261 "mac_main", 1262 "ptp_ref", 1263 "rmii_internal", 1264 "mac_cg"; 1265 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1266 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1267 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1268 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1269 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1270 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1271 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1272 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1273 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1274 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1275 <&topckgen CLK_TOP_ETHPLL_D8>, 1276 <&topckgen CLK_TOP_ETHPLL_D10>; 1277 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1278 mediatek,pericfg = <&infracfg_ao>; 1279 snps,axi-config = <&stmmac_axi_setup>; 1280 snps,mtl-rx-config = <&mtl_rx_setup>; 1281 snps,mtl-tx-config = <&mtl_tx_setup>; 1282 snps,txpbl = <16>; 1283 snps,rxpbl = <16>; 1284 snps,clk-csr = <0>; 1285 status = "disabled"; 1286 1287 mdio { 1288 compatible = "snps,dwmac-mdio"; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 }; 1292 1293 stmmac_axi_setup: stmmac-axi-config { 1294 snps,wr_osr_lmt = <0x7>; 1295 snps,rd_osr_lmt = <0x7>; 1296 snps,blen = <0 0 0 0 16 8 4>; 1297 }; 1298 1299 mtl_rx_setup: rx-queues-config { 1300 snps,rx-queues-to-use = <4>; 1301 snps,rx-sched-sp; 1302 queue0 { 1303 snps,dcb-algorithm; 1304 snps,map-to-dma-channel = <0x0>; 1305 }; 1306 queue1 { 1307 snps,dcb-algorithm; 1308 snps,map-to-dma-channel = <0x0>; 1309 }; 1310 queue2 { 1311 snps,dcb-algorithm; 1312 snps,map-to-dma-channel = <0x0>; 1313 }; 1314 queue3 { 1315 snps,dcb-algorithm; 1316 snps,map-to-dma-channel = <0x0>; 1317 }; 1318 }; 1319 1320 mtl_tx_setup: tx-queues-config { 1321 snps,tx-queues-to-use = <4>; 1322 snps,tx-sched-wrr; 1323 queue0 { 1324 snps,weight = <0x10>; 1325 snps,dcb-algorithm; 1326 snps,priority = <0x0>; 1327 }; 1328 queue1 { 1329 snps,weight = <0x11>; 1330 snps,dcb-algorithm; 1331 snps,priority = <0x1>; 1332 }; 1333 queue2 { 1334 snps,weight = <0x12>; 1335 snps,dcb-algorithm; 1336 snps,priority = <0x2>; 1337 }; 1338 queue3 { 1339 snps,weight = <0x13>; 1340 snps,dcb-algorithm; 1341 snps,priority = <0x3>; 1342 }; 1343 }; 1344 }; 1345 1346 xhci0: usb@11200000 { 1347 compatible = "mediatek,mt8195-xhci", 1348 "mediatek,mtk-xhci"; 1349 reg = <0 0x11200000 0 0x1000>, 1350 <0 0x11203e00 0 0x0100>; 1351 reg-names = "mac", "ippc"; 1352 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1353 phys = <&u2port0 PHY_TYPE_USB2>, 1354 <&u3port0 PHY_TYPE_USB3>; 1355 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1356 <&topckgen CLK_TOP_SSUSB_XHCI>; 1357 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1358 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1359 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1360 <&topckgen CLK_TOP_SSUSB_REF>, 1361 <&apmixedsys CLK_APMIXED_USB1PLL>, 1362 <&clk26m>, 1363 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1364 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1365 "xhci_ck"; 1366 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1367 wakeup-source; 1368 status = "disabled"; 1369 }; 1370 1371 mmc0: mmc@11230000 { 1372 compatible = "mediatek,mt8195-mmc", 1373 "mediatek,mt8183-mmc"; 1374 reg = <0 0x11230000 0 0x10000>, 1375 <0 0x11f50000 0 0x1000>; 1376 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1377 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1378 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1379 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1380 clock-names = "source", "hclk", "source_cg"; 1381 status = "disabled"; 1382 }; 1383 1384 mmc1: mmc@11240000 { 1385 compatible = "mediatek,mt8195-mmc", 1386 "mediatek,mt8183-mmc"; 1387 reg = <0 0x11240000 0 0x1000>, 1388 <0 0x11c70000 0 0x1000>; 1389 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1390 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1391 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1392 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1393 clock-names = "source", "hclk", "source_cg"; 1394 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1395 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1396 status = "disabled"; 1397 }; 1398 1399 mmc2: mmc@11250000 { 1400 compatible = "mediatek,mt8195-mmc", 1401 "mediatek,mt8183-mmc"; 1402 reg = <0 0x11250000 0 0x1000>, 1403 <0 0x11e60000 0 0x1000>; 1404 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1405 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1406 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1407 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1408 clock-names = "source", "hclk", "source_cg"; 1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1411 status = "disabled"; 1412 }; 1413 1414 lvts_mcu: thermal-sensor@11278000 { 1415 compatible = "mediatek,mt8195-lvts-mcu"; 1416 reg = <0 0x11278000 0 0x1000>; 1417 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1418 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1419 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1420 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1421 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1422 #thermal-sensor-cells = <1>; 1423 }; 1424 1425 xhci1: usb@11290000 { 1426 compatible = "mediatek,mt8195-xhci", 1427 "mediatek,mtk-xhci"; 1428 reg = <0 0x11290000 0 0x1000>, 1429 <0 0x11293e00 0 0x0100>; 1430 reg-names = "mac", "ippc"; 1431 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1432 phys = <&u2port1 PHY_TYPE_USB2>; 1433 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1434 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1435 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1436 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1437 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1438 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1439 <&apmixedsys CLK_APMIXED_USB1PLL>, 1440 <&clk26m>, 1441 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1442 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1443 "xhci_ck"; 1444 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1445 wakeup-source; 1446 status = "disabled"; 1447 }; 1448 1449 xhci2: usb@112a0000 { 1450 compatible = "mediatek,mt8195-xhci", 1451 "mediatek,mtk-xhci"; 1452 reg = <0 0x112a0000 0 0x1000>, 1453 <0 0x112a3e00 0 0x0100>; 1454 reg-names = "mac", "ippc"; 1455 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1456 phys = <&u2port2 PHY_TYPE_USB2>; 1457 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1458 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1459 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1460 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1461 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1462 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1463 <&clk26m>, 1464 <&clk26m>, 1465 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1466 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1467 "xhci_ck"; 1468 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1469 wakeup-source; 1470 status = "disabled"; 1471 }; 1472 1473 xhci3: usb@112b0000 { 1474 compatible = "mediatek,mt8195-xhci", 1475 "mediatek,mtk-xhci"; 1476 reg = <0 0x112b0000 0 0x1000>, 1477 <0 0x112b3e00 0 0x0100>; 1478 reg-names = "mac", "ippc"; 1479 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1480 phys = <&u2port3 PHY_TYPE_USB2>; 1481 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1482 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1483 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1484 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1485 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1486 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1487 <&clk26m>, 1488 <&clk26m>, 1489 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1490 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1491 "xhci_ck"; 1492 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1493 wakeup-source; 1494 status = "disabled"; 1495 }; 1496 1497 pcie0: pcie@112f0000 { 1498 compatible = "mediatek,mt8195-pcie", 1499 "mediatek,mt8192-pcie"; 1500 device_type = "pci"; 1501 #address-cells = <3>; 1502 #size-cells = <2>; 1503 reg = <0 0x112f0000 0 0x4000>; 1504 reg-names = "pcie-mac"; 1505 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1506 bus-range = <0x00 0xff>; 1507 ranges = <0x81000000 0 0x20000000 1508 0x0 0x20000000 0 0x200000>, 1509 <0x82000000 0 0x20200000 1510 0x0 0x20200000 0 0x3e00000>; 1511 1512 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1513 iommu-map-mask = <0x0>; 1514 1515 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1516 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1517 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1518 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1519 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1520 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1521 clock-names = "pl_250m", "tl_26m", "tl_96m", 1522 "tl_32k", "peri_26m", "peri_mem"; 1523 assigned-clocks = <&topckgen CLK_TOP_TL>; 1524 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1525 1526 phys = <&pciephy>; 1527 phy-names = "pcie-phy"; 1528 1529 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1530 1531 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1532 reset-names = "mac"; 1533 1534 #interrupt-cells = <1>; 1535 interrupt-map-mask = <0 0 0 7>; 1536 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1537 <0 0 0 2 &pcie_intc0 1>, 1538 <0 0 0 3 &pcie_intc0 2>, 1539 <0 0 0 4 &pcie_intc0 3>; 1540 status = "disabled"; 1541 1542 pcie_intc0: interrupt-controller { 1543 interrupt-controller; 1544 #address-cells = <0>; 1545 #interrupt-cells = <1>; 1546 }; 1547 }; 1548 1549 pcie1: pcie@112f8000 { 1550 compatible = "mediatek,mt8195-pcie", 1551 "mediatek,mt8192-pcie"; 1552 device_type = "pci"; 1553 #address-cells = <3>; 1554 #size-cells = <2>; 1555 reg = <0 0x112f8000 0 0x4000>; 1556 reg-names = "pcie-mac"; 1557 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1558 bus-range = <0x00 0xff>; 1559 ranges = <0x81000000 0 0x24000000 1560 0x0 0x24000000 0 0x200000>, 1561 <0x82000000 0 0x24200000 1562 0x0 0x24200000 0 0x3e00000>; 1563 1564 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1565 iommu-map-mask = <0x0>; 1566 1567 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1568 <&clk26m>, 1569 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1570 <&clk26m>, 1571 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1572 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1573 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1574 clock-names = "pl_250m", "tl_26m", "tl_96m", 1575 "tl_32k", "peri_26m", "peri_mem"; 1576 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1577 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1578 1579 phys = <&u3port1 PHY_TYPE_PCIE>; 1580 phy-names = "pcie-phy"; 1581 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1582 1583 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1584 reset-names = "mac"; 1585 1586 #interrupt-cells = <1>; 1587 interrupt-map-mask = <0 0 0 7>; 1588 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1589 <0 0 0 2 &pcie_intc1 1>, 1590 <0 0 0 3 &pcie_intc1 2>, 1591 <0 0 0 4 &pcie_intc1 3>; 1592 status = "disabled"; 1593 1594 pcie_intc1: interrupt-controller { 1595 interrupt-controller; 1596 #address-cells = <0>; 1597 #interrupt-cells = <1>; 1598 }; 1599 }; 1600 1601 nor_flash: spi@1132c000 { 1602 compatible = "mediatek,mt8195-nor", 1603 "mediatek,mt8173-nor"; 1604 reg = <0 0x1132c000 0 0x1000>; 1605 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1606 clocks = <&topckgen CLK_TOP_SPINOR>, 1607 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1608 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1609 clock-names = "spi", "sf", "axi"; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 1615 efuse: efuse@11c10000 { 1616 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1617 reg = <0 0x11c10000 0 0x1000>; 1618 #address-cells = <1>; 1619 #size-cells = <1>; 1620 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1621 reg = <0x184 0x1>; 1622 bits = <0 5>; 1623 }; 1624 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1625 reg = <0x184 0x2>; 1626 bits = <5 5>; 1627 }; 1628 u3_intr_p0: usb3-intr@185 { 1629 reg = <0x185 0x1>; 1630 bits = <2 6>; 1631 }; 1632 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1633 reg = <0x186 0x1>; 1634 bits = <0 5>; 1635 }; 1636 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1637 reg = <0x186 0x2>; 1638 bits = <5 5>; 1639 }; 1640 comb_intr_p1: usb3-intr@187 { 1641 reg = <0x187 0x1>; 1642 bits = <2 6>; 1643 }; 1644 u2_intr_p0: usb2-intr-p0@188,1 { 1645 reg = <0x188 0x1>; 1646 bits = <0 5>; 1647 }; 1648 u2_intr_p1: usb2-intr-p1@188,2 { 1649 reg = <0x188 0x2>; 1650 bits = <5 5>; 1651 }; 1652 u2_intr_p2: usb2-intr-p2@189,1 { 1653 reg = <0x189 0x1>; 1654 bits = <2 5>; 1655 }; 1656 u2_intr_p3: usb2-intr-p3@189,2 { 1657 reg = <0x189 0x2>; 1658 bits = <7 5>; 1659 }; 1660 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1661 reg = <0x190 0x1>; 1662 bits = <0 4>; 1663 }; 1664 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1665 reg = <0x190 0x1>; 1666 bits = <4 4>; 1667 }; 1668 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1669 reg = <0x191 0x1>; 1670 bits = <0 4>; 1671 }; 1672 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1673 reg = <0x191 0x1>; 1674 bits = <4 4>; 1675 }; 1676 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1677 reg = <0x192 0x1>; 1678 bits = <0 4>; 1679 }; 1680 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1681 reg = <0x192 0x1>; 1682 bits = <4 4>; 1683 }; 1684 pciephy_glb_intr: pciephy-glb-intr@193 { 1685 reg = <0x193 0x1>; 1686 bits = <0 4>; 1687 }; 1688 dp_calibration: dp-data@1ac { 1689 reg = <0x1ac 0x10>; 1690 }; 1691 lvts_efuse_data1: lvts1-calib@1bc { 1692 reg = <0x1bc 0x14>; 1693 }; 1694 lvts_efuse_data2: lvts2-calib@1d0 { 1695 reg = <0x1d0 0x38>; 1696 }; 1697 svs_calib_data: svs-calib@580 { 1698 reg = <0x580 0x64>; 1699 }; 1700 }; 1701 1702 u3phy2: t-phy@11c40000 { 1703 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1704 #address-cells = <1>; 1705 #size-cells = <1>; 1706 ranges = <0 0 0x11c40000 0x700>; 1707 status = "disabled"; 1708 1709 u2port2: usb-phy@0 { 1710 reg = <0x0 0x700>; 1711 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1712 clock-names = "ref"; 1713 #phy-cells = <1>; 1714 }; 1715 }; 1716 1717 u3phy3: t-phy@11c50000 { 1718 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1719 #address-cells = <1>; 1720 #size-cells = <1>; 1721 ranges = <0 0 0x11c50000 0x700>; 1722 status = "disabled"; 1723 1724 u2port3: usb-phy@0 { 1725 reg = <0x0 0x700>; 1726 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1727 clock-names = "ref"; 1728 #phy-cells = <1>; 1729 }; 1730 }; 1731 1732 mipi_tx0: dsi-phy@11c80000 { 1733 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1734 reg = <0 0x11c80000 0 0x1000>; 1735 clocks = <&clk26m>; 1736 clock-output-names = "mipi_tx0_pll"; 1737 #clock-cells = <0>; 1738 #phy-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 mipi_tx1: dsi-phy@11c90000 { 1743 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1744 reg = <0 0x11c90000 0 0x1000>; 1745 clocks = <&clk26m>; 1746 clock-output-names = "mipi_tx1_pll"; 1747 #clock-cells = <0>; 1748 #phy-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 i2c5: i2c@11d00000 { 1753 compatible = "mediatek,mt8195-i2c", 1754 "mediatek,mt8192-i2c"; 1755 reg = <0 0x11d00000 0 0x1000>, 1756 <0 0x10220580 0 0x80>; 1757 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1758 clock-div = <1>; 1759 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1760 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1761 clock-names = "main", "dma"; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 status = "disabled"; 1765 }; 1766 1767 i2c6: i2c@11d01000 { 1768 compatible = "mediatek,mt8195-i2c", 1769 "mediatek,mt8192-i2c"; 1770 reg = <0 0x11d01000 0 0x1000>, 1771 <0 0x10220600 0 0x80>; 1772 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1773 clock-div = <1>; 1774 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1775 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1776 clock-names = "main", "dma"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c7: i2c@11d02000 { 1783 compatible = "mediatek,mt8195-i2c", 1784 "mediatek,mt8192-i2c"; 1785 reg = <0 0x11d02000 0 0x1000>, 1786 <0 0x10220680 0 0x80>; 1787 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1788 clock-div = <1>; 1789 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1790 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1791 clock-names = "main", "dma"; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 status = "disabled"; 1795 }; 1796 1797 imp_iic_wrap_s: clock-controller@11d03000 { 1798 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1799 reg = <0 0x11d03000 0 0x1000>; 1800 #clock-cells = <1>; 1801 }; 1802 1803 i2c0: i2c@11e00000 { 1804 compatible = "mediatek,mt8195-i2c", 1805 "mediatek,mt8192-i2c"; 1806 reg = <0 0x11e00000 0 0x1000>, 1807 <0 0x10220080 0 0x80>; 1808 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1809 clock-div = <1>; 1810 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1811 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1812 clock-names = "main", "dma"; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 status = "disabled"; 1816 }; 1817 1818 i2c1: i2c@11e01000 { 1819 compatible = "mediatek,mt8195-i2c", 1820 "mediatek,mt8192-i2c"; 1821 reg = <0 0x11e01000 0 0x1000>, 1822 <0 0x10220200 0 0x80>; 1823 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1824 clock-div = <1>; 1825 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1826 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1827 clock-names = "main", "dma"; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 i2c2: i2c@11e02000 { 1834 compatible = "mediatek,mt8195-i2c", 1835 "mediatek,mt8192-i2c"; 1836 reg = <0 0x11e02000 0 0x1000>, 1837 <0 0x10220380 0 0x80>; 1838 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1839 clock-div = <1>; 1840 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1841 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1842 clock-names = "main", "dma"; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 }; 1847 1848 i2c3: i2c@11e03000 { 1849 compatible = "mediatek,mt8195-i2c", 1850 "mediatek,mt8192-i2c"; 1851 reg = <0 0x11e03000 0 0x1000>, 1852 <0 0x10220480 0 0x80>; 1853 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1854 clock-div = <1>; 1855 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1856 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1857 clock-names = "main", "dma"; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 status = "disabled"; 1861 }; 1862 1863 i2c4: i2c@11e04000 { 1864 compatible = "mediatek,mt8195-i2c", 1865 "mediatek,mt8192-i2c"; 1866 reg = <0 0x11e04000 0 0x1000>, 1867 <0 0x10220500 0 0x80>; 1868 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1869 clock-div = <1>; 1870 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1871 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1872 clock-names = "main", "dma"; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 status = "disabled"; 1876 }; 1877 1878 imp_iic_wrap_w: clock-controller@11e05000 { 1879 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1880 reg = <0 0x11e05000 0 0x1000>; 1881 #clock-cells = <1>; 1882 }; 1883 1884 u3phy1: t-phy@11e30000 { 1885 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1886 #address-cells = <1>; 1887 #size-cells = <1>; 1888 ranges = <0 0 0x11e30000 0xe00>; 1889 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1890 status = "disabled"; 1891 1892 u2port1: usb-phy@0 { 1893 reg = <0x0 0x700>; 1894 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1895 <&clk26m>; 1896 clock-names = "ref", "da_ref"; 1897 #phy-cells = <1>; 1898 }; 1899 1900 u3port1: usb-phy@700 { 1901 reg = <0x700 0x700>; 1902 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1903 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1904 clock-names = "ref", "da_ref"; 1905 nvmem-cells = <&comb_intr_p1>, 1906 <&comb_rx_imp_p1>, 1907 <&comb_tx_imp_p1>; 1908 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1909 #phy-cells = <1>; 1910 }; 1911 }; 1912 1913 u3phy0: t-phy@11e40000 { 1914 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1915 #address-cells = <1>; 1916 #size-cells = <1>; 1917 ranges = <0 0 0x11e40000 0xe00>; 1918 status = "disabled"; 1919 1920 u2port0: usb-phy@0 { 1921 reg = <0x0 0x700>; 1922 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1923 <&clk26m>; 1924 clock-names = "ref", "da_ref"; 1925 #phy-cells = <1>; 1926 }; 1927 1928 u3port0: usb-phy@700 { 1929 reg = <0x700 0x700>; 1930 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1931 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1932 clock-names = "ref", "da_ref"; 1933 nvmem-cells = <&u3_intr_p0>, 1934 <&u3_rx_imp_p0>, 1935 <&u3_tx_imp_p0>; 1936 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1937 #phy-cells = <1>; 1938 }; 1939 }; 1940 1941 pciephy: phy@11e80000 { 1942 compatible = "mediatek,mt8195-pcie-phy"; 1943 reg = <0 0x11e80000 0 0x10000>; 1944 reg-names = "sif"; 1945 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1946 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1947 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1948 <&pciephy_rx_ln1>; 1949 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1950 "tx_ln0_nmos", "rx_ln0", 1951 "tx_ln1_pmos", "tx_ln1_nmos", 1952 "rx_ln1"; 1953 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1954 #phy-cells = <0>; 1955 status = "disabled"; 1956 }; 1957 1958 ufsphy: ufs-phy@11fa0000 { 1959 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1960 reg = <0 0x11fa0000 0 0xc000>; 1961 clocks = <&clk26m>, <&clk26m>; 1962 clock-names = "unipro", "mp"; 1963 #phy-cells = <0>; 1964 status = "disabled"; 1965 }; 1966 1967 gpu: gpu@13000000 { 1968 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1969 "arm,mali-valhall-jm"; 1970 reg = <0 0x13000000 0 0x4000>; 1971 1972 clocks = <&mfgcfg CLK_MFG_BG3D>; 1973 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1974 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1975 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1976 interrupt-names = "job", "mmu", "gpu"; 1977 operating-points-v2 = <&gpu_opp_table>; 1978 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1979 <&spm MT8195_POWER_DOMAIN_MFG3>, 1980 <&spm MT8195_POWER_DOMAIN_MFG4>, 1981 <&spm MT8195_POWER_DOMAIN_MFG5>, 1982 <&spm MT8195_POWER_DOMAIN_MFG6>; 1983 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1984 status = "disabled"; 1985 }; 1986 1987 mfgcfg: clock-controller@13fbf000 { 1988 compatible = "mediatek,mt8195-mfgcfg"; 1989 reg = <0 0x13fbf000 0 0x1000>; 1990 #clock-cells = <1>; 1991 }; 1992 1993 vppsys0: syscon@14000000 { 1994 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1995 reg = <0 0x14000000 0 0x1000>; 1996 #clock-cells = <1>; 1997 }; 1998 1999 dma-controller@14001000 { 2000 compatible = "mediatek,mt8195-mdp3-rdma"; 2001 reg = <0 0x14001000 0 0x1000>; 2002 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2003 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2004 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2005 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2006 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 2007 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2008 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 2009 <&gce1 13 CMDQ_THR_PRIO_1>, 2010 <&gce1 14 CMDQ_THR_PRIO_1>, 2011 <&gce1 21 CMDQ_THR_PRIO_1>, 2012 <&gce1 22 CMDQ_THR_PRIO_1>; 2013 #dma-cells = <1>; 2014 }; 2015 2016 display@14002000 { 2017 compatible = "mediatek,mt8195-mdp3-fg"; 2018 reg = <0 0x14002000 0 0x1000>; 2019 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2020 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2021 }; 2022 2023 display@14003000 { 2024 compatible = "mediatek,mt8195-mdp3-stitch"; 2025 reg = <0 0x14003000 0 0x1000>; 2026 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2027 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2028 }; 2029 2030 display@14004000 { 2031 compatible = "mediatek,mt8195-mdp3-hdr"; 2032 reg = <0 0x14004000 0 0x1000>; 2033 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2034 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2035 }; 2036 2037 display@14005000 { 2038 compatible = "mediatek,mt8195-mdp3-aal"; 2039 reg = <0 0x14005000 0 0x1000>; 2040 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2041 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2042 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2043 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2044 }; 2045 2046 display@14006000 { 2047 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2048 reg = <0 0x14006000 0 0x1000>; 2049 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2050 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2051 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2052 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2053 }; 2054 2055 display@14007000 { 2056 compatible = "mediatek,mt8195-mdp3-tdshp"; 2057 reg = <0 0x14007000 0 0x1000>; 2058 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2059 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2060 }; 2061 2062 display@14008000 { 2063 compatible = "mediatek,mt8195-mdp3-color"; 2064 reg = <0 0x14008000 0 0x1000>; 2065 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2066 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2067 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2068 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2069 }; 2070 2071 display@14009000 { 2072 compatible = "mediatek,mt8195-mdp3-ovl"; 2073 reg = <0 0x14009000 0 0x1000>; 2074 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2075 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2076 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2077 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2078 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2079 }; 2080 2081 display@1400a000 { 2082 compatible = "mediatek,mt8195-mdp3-padding"; 2083 reg = <0 0x1400a000 0 0x1000>; 2084 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2085 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2086 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2087 }; 2088 2089 display@1400b000 { 2090 compatible = "mediatek,mt8195-mdp3-tcc"; 2091 reg = <0 0x1400b000 0 0x1000>; 2092 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2093 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2094 }; 2095 2096 dma-controller@1400c000 { 2097 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2098 reg = <0 0x1400c000 0 0x1000>; 2099 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2100 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2101 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2102 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2103 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2104 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2105 #dma-cells = <1>; 2106 }; 2107 2108 mutex@1400f000 { 2109 compatible = "mediatek,mt8195-vpp-mutex"; 2110 reg = <0 0x1400f000 0 0x1000>; 2111 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2112 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2113 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2114 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2115 }; 2116 2117 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2118 compatible = "mediatek,mt8195-smi-sub-common"; 2119 reg = <0 0x14010000 0 0x1000>; 2120 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2121 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2122 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2123 clock-names = "apb", "smi", "gals0"; 2124 mediatek,smi = <&smi_common_vpp>; 2125 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2126 }; 2127 2128 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2129 compatible = "mediatek,mt8195-smi-sub-common"; 2130 reg = <0 0x14011000 0 0x1000>; 2131 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2132 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2133 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2134 clock-names = "apb", "smi", "gals0"; 2135 mediatek,smi = <&smi_common_vpp>; 2136 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2137 }; 2138 2139 smi_common_vpp: smi@14012000 { 2140 compatible = "mediatek,mt8195-smi-common-vpp"; 2141 reg = <0 0x14012000 0 0x1000>; 2142 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2143 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2144 <&vppsys0 CLK_VPP0_SMI_RSI>, 2145 <&vppsys0 CLK_VPP0_SMI_RSI>; 2146 clock-names = "apb", "smi", "gals0", "gals1"; 2147 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2148 }; 2149 2150 larb4: larb@14013000 { 2151 compatible = "mediatek,mt8195-smi-larb"; 2152 reg = <0 0x14013000 0 0x1000>; 2153 mediatek,larb-id = <4>; 2154 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2155 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2156 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2157 clock-names = "apb", "smi"; 2158 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2159 }; 2160 2161 iommu_vpp: iommu@14018000 { 2162 compatible = "mediatek,mt8195-iommu-vpp"; 2163 reg = <0 0x14018000 0 0x1000>; 2164 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2165 &larb12 &larb14 &larb16 &larb18 2166 &larb20 &larb22 &larb23 &larb26 2167 &larb27>; 2168 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2169 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2170 clock-names = "bclk"; 2171 #iommu-cells = <1>; 2172 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2173 }; 2174 2175 wpesys: clock-controller@14e00000 { 2176 compatible = "mediatek,mt8195-wpesys"; 2177 reg = <0 0x14e00000 0 0x1000>; 2178 #clock-cells = <1>; 2179 }; 2180 2181 wpesys_vpp0: clock-controller@14e02000 { 2182 compatible = "mediatek,mt8195-wpesys_vpp0"; 2183 reg = <0 0x14e02000 0 0x1000>; 2184 #clock-cells = <1>; 2185 }; 2186 2187 wpesys_vpp1: clock-controller@14e03000 { 2188 compatible = "mediatek,mt8195-wpesys_vpp1"; 2189 reg = <0 0x14e03000 0 0x1000>; 2190 #clock-cells = <1>; 2191 }; 2192 2193 larb7: larb@14e04000 { 2194 compatible = "mediatek,mt8195-smi-larb"; 2195 reg = <0 0x14e04000 0 0x1000>; 2196 mediatek,larb-id = <7>; 2197 mediatek,smi = <&smi_common_vdo>; 2198 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2199 <&wpesys CLK_WPE_SMI_LARB7>; 2200 clock-names = "apb", "smi"; 2201 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2202 }; 2203 2204 larb8: larb@14e05000 { 2205 compatible = "mediatek,mt8195-smi-larb"; 2206 reg = <0 0x14e05000 0 0x1000>; 2207 mediatek,larb-id = <8>; 2208 mediatek,smi = <&smi_common_vpp>; 2209 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2210 <&wpesys CLK_WPE_SMI_LARB8>, 2211 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2212 clock-names = "apb", "smi", "gals"; 2213 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2214 }; 2215 2216 vppsys1: syscon@14f00000 { 2217 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2218 reg = <0 0x14f00000 0 0x1000>; 2219 #clock-cells = <1>; 2220 }; 2221 2222 mutex@14f01000 { 2223 compatible = "mediatek,mt8195-vpp-mutex"; 2224 reg = <0 0x14f01000 0 0x1000>; 2225 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2226 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2227 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2228 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2229 }; 2230 2231 larb5: larb@14f02000 { 2232 compatible = "mediatek,mt8195-smi-larb"; 2233 reg = <0 0x14f02000 0 0x1000>; 2234 mediatek,larb-id = <5>; 2235 mediatek,smi = <&smi_common_vdo>; 2236 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2237 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2238 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2239 clock-names = "apb", "smi", "gals"; 2240 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2241 }; 2242 2243 larb6: larb@14f03000 { 2244 compatible = "mediatek,mt8195-smi-larb"; 2245 reg = <0 0x14f03000 0 0x1000>; 2246 mediatek,larb-id = <6>; 2247 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2248 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2249 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2250 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2251 clock-names = "apb", "smi", "gals"; 2252 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2253 }; 2254 2255 display@14f06000 { 2256 compatible = "mediatek,mt8195-mdp3-split"; 2257 reg = <0 0x14f06000 0 0x1000>; 2258 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2259 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2260 <&vppsys1 CLK_VPP1_HDMI_META>, 2261 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2262 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2263 }; 2264 2265 display@14f07000 { 2266 compatible = "mediatek,mt8195-mdp3-tcc"; 2267 reg = <0 0x14f07000 0 0x1000>; 2268 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2269 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2270 }; 2271 2272 dma-controller@14f08000 { 2273 compatible = "mediatek,mt8195-mdp3-rdma"; 2274 reg = <0 0x14f08000 0 0x1000>; 2275 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2276 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2277 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2278 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2279 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2280 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2281 #dma-cells = <1>; 2282 }; 2283 2284 dma-controller@14f09000 { 2285 compatible = "mediatek,mt8195-mdp3-rdma"; 2286 reg = <0 0x14f09000 0 0x1000>; 2287 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2288 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2289 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2290 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2291 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2292 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2293 #dma-cells = <1>; 2294 }; 2295 2296 dma-controller@14f0a000 { 2297 compatible = "mediatek,mt8195-mdp3-rdma"; 2298 reg = <0 0x14f0a000 0 0x1000>; 2299 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2300 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2301 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2302 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2303 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2304 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2305 #dma-cells = <1>; 2306 }; 2307 2308 display@14f0b000 { 2309 compatible = "mediatek,mt8195-mdp3-fg"; 2310 reg = <0 0x14f0b000 0 0x1000>; 2311 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2312 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2313 }; 2314 2315 display@14f0c000 { 2316 compatible = "mediatek,mt8195-mdp3-fg"; 2317 reg = <0 0x14f0c000 0 0x1000>; 2318 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2319 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2320 }; 2321 2322 display@14f0d000 { 2323 compatible = "mediatek,mt8195-mdp3-fg"; 2324 reg = <0 0x14f0d000 0 0x1000>; 2325 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2326 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2327 }; 2328 2329 display@14f0e000 { 2330 compatible = "mediatek,mt8195-mdp3-hdr"; 2331 reg = <0 0x14f0e000 0 0x1000>; 2332 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2333 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2334 }; 2335 2336 display@14f0f000 { 2337 compatible = "mediatek,mt8195-mdp3-hdr"; 2338 reg = <0 0x14f0f000 0 0x1000>; 2339 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2340 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2341 }; 2342 2343 display@14f10000 { 2344 compatible = "mediatek,mt8195-mdp3-hdr"; 2345 reg = <0 0x14f10000 0 0x1000>; 2346 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2347 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2348 }; 2349 2350 display@14f11000 { 2351 compatible = "mediatek,mt8195-mdp3-aal"; 2352 reg = <0 0x14f11000 0 0x1000>; 2353 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2354 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2355 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2356 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2357 }; 2358 2359 display@14f12000 { 2360 compatible = "mediatek,mt8195-mdp3-aal"; 2361 reg = <0 0x14f12000 0 0x1000>; 2362 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2363 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2364 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2365 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2366 }; 2367 2368 display@14f13000 { 2369 compatible = "mediatek,mt8195-mdp3-aal"; 2370 reg = <0 0x14f13000 0 0x1000>; 2371 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2372 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2373 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2374 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2375 }; 2376 2377 display@14f14000 { 2378 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2379 reg = <0 0x14f14000 0 0x1000>; 2380 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2381 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2382 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2383 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2384 }; 2385 2386 display@14f15000 { 2387 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2388 reg = <0 0x14f15000 0 0x1000>; 2389 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2390 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2391 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2392 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2393 }; 2394 2395 display@14f16000 { 2396 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2397 reg = <0 0x14f16000 0 0x1000>; 2398 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2399 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2400 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2401 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2402 }; 2403 2404 display@14f17000 { 2405 compatible = "mediatek,mt8195-mdp3-tdshp"; 2406 reg = <0 0x14f17000 0 0x1000>; 2407 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2408 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2409 }; 2410 2411 display@14f18000 { 2412 compatible = "mediatek,mt8195-mdp3-tdshp"; 2413 reg = <0 0x14f18000 0 0x1000>; 2414 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2415 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2416 }; 2417 2418 display@14f19000 { 2419 compatible = "mediatek,mt8195-mdp3-tdshp"; 2420 reg = <0 0x14f19000 0 0x1000>; 2421 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2422 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2423 }; 2424 2425 display@14f1a000 { 2426 compatible = "mediatek,mt8195-mdp3-merge"; 2427 reg = <0 0x14f1a000 0 0x1000>; 2428 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2429 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2430 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2431 }; 2432 2433 display@14f1b000 { 2434 compatible = "mediatek,mt8195-mdp3-merge"; 2435 reg = <0 0x14f1b000 0 0x1000>; 2436 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2437 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2438 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2439 }; 2440 2441 display@14f1c000 { 2442 compatible = "mediatek,mt8195-mdp3-color"; 2443 reg = <0 0x14f1c000 0 0x1000>; 2444 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2445 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2446 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2447 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2448 }; 2449 2450 display@14f1d000 { 2451 compatible = "mediatek,mt8195-mdp3-color"; 2452 reg = <0 0x14f1d000 0 0x1000>; 2453 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2454 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2455 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2456 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2457 }; 2458 2459 display@14f1e000 { 2460 compatible = "mediatek,mt8195-mdp3-color"; 2461 reg = <0 0x14f1e000 0 0x1000>; 2462 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2463 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2464 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2465 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2466 }; 2467 2468 display@14f1f000 { 2469 compatible = "mediatek,mt8195-mdp3-ovl"; 2470 reg = <0 0x14f1f000 0 0x1000>; 2471 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2472 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2473 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2474 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2475 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2476 }; 2477 2478 display@14f20000 { 2479 compatible = "mediatek,mt8195-mdp3-padding"; 2480 reg = <0 0x14f20000 0 0x1000>; 2481 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2482 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2483 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2484 }; 2485 2486 display@14f21000 { 2487 compatible = "mediatek,mt8195-mdp3-padding"; 2488 reg = <0 0x14f21000 0 0x1000>; 2489 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2490 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2491 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2492 }; 2493 2494 display@14f22000 { 2495 compatible = "mediatek,mt8195-mdp3-padding"; 2496 reg = <0 0x14f22000 0 0x1000>; 2497 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2498 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2499 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2500 }; 2501 2502 dma-controller@14f23000 { 2503 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2504 reg = <0 0x14f23000 0 0x1000>; 2505 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2506 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2507 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2508 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2509 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2510 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2511 #dma-cells = <1>; 2512 }; 2513 2514 dma-controller@14f24000 { 2515 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2516 reg = <0 0x14f24000 0 0x1000>; 2517 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2518 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2519 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2520 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2521 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2522 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2523 #dma-cells = <1>; 2524 }; 2525 2526 dma-controller@14f25000 { 2527 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2528 reg = <0 0x14f25000 0 0x1000>; 2529 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2530 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2531 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2532 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2533 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2534 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2535 #dma-cells = <1>; 2536 }; 2537 2538 imgsys: clock-controller@15000000 { 2539 compatible = "mediatek,mt8195-imgsys"; 2540 reg = <0 0x15000000 0 0x1000>; 2541 #clock-cells = <1>; 2542 }; 2543 2544 larb9: larb@15001000 { 2545 compatible = "mediatek,mt8195-smi-larb"; 2546 reg = <0 0x15001000 0 0x1000>; 2547 mediatek,larb-id = <9>; 2548 mediatek,smi = <&smi_sub_common_img1_3x1>; 2549 clocks = <&imgsys CLK_IMG_LARB9>, 2550 <&imgsys CLK_IMG_LARB9>, 2551 <&imgsys CLK_IMG_GALS>; 2552 clock-names = "apb", "smi", "gals"; 2553 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2554 }; 2555 2556 smi_sub_common_img0_3x1: smi@15002000 { 2557 compatible = "mediatek,mt8195-smi-sub-common"; 2558 reg = <0 0x15002000 0 0x1000>; 2559 clocks = <&imgsys CLK_IMG_IPE>, 2560 <&imgsys CLK_IMG_IPE>, 2561 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2562 clock-names = "apb", "smi", "gals0"; 2563 mediatek,smi = <&smi_common_vpp>; 2564 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2565 }; 2566 2567 smi_sub_common_img1_3x1: smi@15003000 { 2568 compatible = "mediatek,mt8195-smi-sub-common"; 2569 reg = <0 0x15003000 0 0x1000>; 2570 clocks = <&imgsys CLK_IMG_LARB9>, 2571 <&imgsys CLK_IMG_LARB9>, 2572 <&imgsys CLK_IMG_GALS>; 2573 clock-names = "apb", "smi", "gals0"; 2574 mediatek,smi = <&smi_common_vdo>; 2575 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2576 }; 2577 2578 imgsys1_dip_top: clock-controller@15110000 { 2579 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2580 reg = <0 0x15110000 0 0x1000>; 2581 #clock-cells = <1>; 2582 }; 2583 2584 larb10: larb@15120000 { 2585 compatible = "mediatek,mt8195-smi-larb"; 2586 reg = <0 0x15120000 0 0x1000>; 2587 mediatek,larb-id = <10>; 2588 mediatek,smi = <&smi_sub_common_img1_3x1>; 2589 clocks = <&imgsys CLK_IMG_DIP0>, 2590 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2591 clock-names = "apb", "smi"; 2592 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2593 }; 2594 2595 imgsys1_dip_nr: clock-controller@15130000 { 2596 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2597 reg = <0 0x15130000 0 0x1000>; 2598 #clock-cells = <1>; 2599 }; 2600 2601 imgsys1_wpe: clock-controller@15220000 { 2602 compatible = "mediatek,mt8195-imgsys1_wpe"; 2603 reg = <0 0x15220000 0 0x1000>; 2604 #clock-cells = <1>; 2605 }; 2606 2607 larb11: larb@15230000 { 2608 compatible = "mediatek,mt8195-smi-larb"; 2609 reg = <0 0x15230000 0 0x1000>; 2610 mediatek,larb-id = <11>; 2611 mediatek,smi = <&smi_sub_common_img1_3x1>; 2612 clocks = <&imgsys CLK_IMG_WPE0>, 2613 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2614 clock-names = "apb", "smi"; 2615 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2616 }; 2617 2618 ipesys: clock-controller@15330000 { 2619 compatible = "mediatek,mt8195-ipesys"; 2620 reg = <0 0x15330000 0 0x1000>; 2621 #clock-cells = <1>; 2622 }; 2623 2624 larb12: larb@15340000 { 2625 compatible = "mediatek,mt8195-smi-larb"; 2626 reg = <0 0x15340000 0 0x1000>; 2627 mediatek,larb-id = <12>; 2628 mediatek,smi = <&smi_sub_common_img0_3x1>; 2629 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2630 <&ipesys CLK_IPE_SMI_LARB12>; 2631 clock-names = "apb", "smi"; 2632 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2633 }; 2634 2635 camsys: clock-controller@16000000 { 2636 compatible = "mediatek,mt8195-camsys"; 2637 reg = <0 0x16000000 0 0x1000>; 2638 #clock-cells = <1>; 2639 }; 2640 2641 larb13: larb@16001000 { 2642 compatible = "mediatek,mt8195-smi-larb"; 2643 reg = <0 0x16001000 0 0x1000>; 2644 mediatek,larb-id = <13>; 2645 mediatek,smi = <&smi_sub_common_cam_4x1>; 2646 clocks = <&camsys CLK_CAM_LARB13>, 2647 <&camsys CLK_CAM_LARB13>, 2648 <&camsys CLK_CAM_CAM2MM0_GALS>; 2649 clock-names = "apb", "smi", "gals"; 2650 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2651 }; 2652 2653 larb14: larb@16002000 { 2654 compatible = "mediatek,mt8195-smi-larb"; 2655 reg = <0 0x16002000 0 0x1000>; 2656 mediatek,larb-id = <14>; 2657 mediatek,smi = <&smi_sub_common_cam_7x1>; 2658 clocks = <&camsys CLK_CAM_LARB14>, 2659 <&camsys CLK_CAM_LARB14>; 2660 clock-names = "apb", "smi"; 2661 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2662 }; 2663 2664 smi_sub_common_cam_4x1: smi@16004000 { 2665 compatible = "mediatek,mt8195-smi-sub-common"; 2666 reg = <0 0x16004000 0 0x1000>; 2667 clocks = <&camsys CLK_CAM_LARB13>, 2668 <&camsys CLK_CAM_LARB13>, 2669 <&camsys CLK_CAM_CAM2MM0_GALS>; 2670 clock-names = "apb", "smi", "gals0"; 2671 mediatek,smi = <&smi_common_vdo>; 2672 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2673 }; 2674 2675 smi_sub_common_cam_7x1: smi@16005000 { 2676 compatible = "mediatek,mt8195-smi-sub-common"; 2677 reg = <0 0x16005000 0 0x1000>; 2678 clocks = <&camsys CLK_CAM_LARB14>, 2679 <&camsys CLK_CAM_CAM2MM1_GALS>, 2680 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2681 clock-names = "apb", "smi", "gals0"; 2682 mediatek,smi = <&smi_common_vpp>; 2683 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2684 }; 2685 2686 larb16: larb@16012000 { 2687 compatible = "mediatek,mt8195-smi-larb"; 2688 reg = <0 0x16012000 0 0x1000>; 2689 mediatek,larb-id = <16>; 2690 mediatek,smi = <&smi_sub_common_cam_7x1>; 2691 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2692 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2693 clock-names = "apb", "smi"; 2694 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2695 }; 2696 2697 larb17: larb@16013000 { 2698 compatible = "mediatek,mt8195-smi-larb"; 2699 reg = <0 0x16013000 0 0x1000>; 2700 mediatek,larb-id = <17>; 2701 mediatek,smi = <&smi_sub_common_cam_4x1>; 2702 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2703 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2704 clock-names = "apb", "smi"; 2705 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2706 }; 2707 2708 larb27: larb@16014000 { 2709 compatible = "mediatek,mt8195-smi-larb"; 2710 reg = <0 0x16014000 0 0x1000>; 2711 mediatek,larb-id = <27>; 2712 mediatek,smi = <&smi_sub_common_cam_7x1>; 2713 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2714 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2715 clock-names = "apb", "smi"; 2716 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2717 }; 2718 2719 larb28: larb@16015000 { 2720 compatible = "mediatek,mt8195-smi-larb"; 2721 reg = <0 0x16015000 0 0x1000>; 2722 mediatek,larb-id = <28>; 2723 mediatek,smi = <&smi_sub_common_cam_4x1>; 2724 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2725 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2726 clock-names = "apb", "smi"; 2727 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2728 }; 2729 2730 camsys_rawa: clock-controller@1604f000 { 2731 compatible = "mediatek,mt8195-camsys_rawa"; 2732 reg = <0 0x1604f000 0 0x1000>; 2733 #clock-cells = <1>; 2734 }; 2735 2736 camsys_yuva: clock-controller@1606f000 { 2737 compatible = "mediatek,mt8195-camsys_yuva"; 2738 reg = <0 0x1606f000 0 0x1000>; 2739 #clock-cells = <1>; 2740 }; 2741 2742 camsys_rawb: clock-controller@1608f000 { 2743 compatible = "mediatek,mt8195-camsys_rawb"; 2744 reg = <0 0x1608f000 0 0x1000>; 2745 #clock-cells = <1>; 2746 }; 2747 2748 camsys_yuvb: clock-controller@160af000 { 2749 compatible = "mediatek,mt8195-camsys_yuvb"; 2750 reg = <0 0x160af000 0 0x1000>; 2751 #clock-cells = <1>; 2752 }; 2753 2754 camsys_mraw: clock-controller@16140000 { 2755 compatible = "mediatek,mt8195-camsys_mraw"; 2756 reg = <0 0x16140000 0 0x1000>; 2757 #clock-cells = <1>; 2758 }; 2759 2760 larb25: larb@16141000 { 2761 compatible = "mediatek,mt8195-smi-larb"; 2762 reg = <0 0x16141000 0 0x1000>; 2763 mediatek,larb-id = <25>; 2764 mediatek,smi = <&smi_sub_common_cam_4x1>; 2765 clocks = <&camsys CLK_CAM_LARB13>, 2766 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2767 <&camsys CLK_CAM_CAM2MM0_GALS>; 2768 clock-names = "apb", "smi", "gals"; 2769 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2770 }; 2771 2772 larb26: larb@16142000 { 2773 compatible = "mediatek,mt8195-smi-larb"; 2774 reg = <0 0x16142000 0 0x1000>; 2775 mediatek,larb-id = <26>; 2776 mediatek,smi = <&smi_sub_common_cam_7x1>; 2777 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2778 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2779 clock-names = "apb", "smi"; 2780 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2781 2782 }; 2783 2784 ccusys: clock-controller@17200000 { 2785 compatible = "mediatek,mt8195-ccusys"; 2786 reg = <0 0x17200000 0 0x1000>; 2787 #clock-cells = <1>; 2788 }; 2789 2790 larb18: larb@17201000 { 2791 compatible = "mediatek,mt8195-smi-larb"; 2792 reg = <0 0x17201000 0 0x1000>; 2793 mediatek,larb-id = <18>; 2794 mediatek,smi = <&smi_sub_common_cam_7x1>; 2795 clocks = <&ccusys CLK_CCU_LARB18>, 2796 <&ccusys CLK_CCU_LARB18>; 2797 clock-names = "apb", "smi"; 2798 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2799 }; 2800 2801 video-codec@18000000 { 2802 compatible = "mediatek,mt8195-vcodec-dec"; 2803 mediatek,scp = <&scp>; 2804 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2805 #address-cells = <2>; 2806 #size-cells = <2>; 2807 reg = <0 0x18000000 0 0x1000>, 2808 <0 0x18004000 0 0x1000>; 2809 ranges = <0 0 0 0x18000000 0 0x26000>; 2810 2811 video-codec@2000 { 2812 compatible = "mediatek,mtk-vcodec-lat-soc"; 2813 reg = <0 0x2000 0 0x800>; 2814 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2815 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2816 clocks = <&topckgen CLK_TOP_VDEC>, 2817 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2818 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2819 <&topckgen CLK_TOP_UNIVPLL_D4>; 2820 clock-names = "sel", "vdec", "lat", "top"; 2821 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2822 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2823 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2824 }; 2825 2826 video-codec@10000 { 2827 compatible = "mediatek,mtk-vcodec-lat"; 2828 reg = <0 0x10000 0 0x800>; 2829 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2830 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2831 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2832 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2833 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2834 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2835 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2836 clocks = <&topckgen CLK_TOP_VDEC>, 2837 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2838 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2839 <&topckgen CLK_TOP_UNIVPLL_D4>; 2840 clock-names = "sel", "vdec", "lat", "top"; 2841 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2842 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2843 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2844 }; 2845 2846 video-codec@25000 { 2847 compatible = "mediatek,mtk-vcodec-core"; 2848 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2849 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2850 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2851 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2852 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2853 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2854 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2855 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2856 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2857 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2858 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2859 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2860 clocks = <&topckgen CLK_TOP_VDEC>, 2861 <&vdecsys CLK_VDEC_VDEC>, 2862 <&vdecsys CLK_VDEC_LAT>, 2863 <&topckgen CLK_TOP_UNIVPLL_D4>; 2864 clock-names = "sel", "vdec", "lat", "top"; 2865 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2866 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2867 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2868 }; 2869 }; 2870 2871 larb24: larb@1800d000 { 2872 compatible = "mediatek,mt8195-smi-larb"; 2873 reg = <0 0x1800d000 0 0x1000>; 2874 mediatek,larb-id = <24>; 2875 mediatek,smi = <&smi_common_vdo>; 2876 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2877 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2878 clock-names = "apb", "smi"; 2879 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2880 }; 2881 2882 larb23: larb@1800e000 { 2883 compatible = "mediatek,mt8195-smi-larb"; 2884 reg = <0 0x1800e000 0 0x1000>; 2885 mediatek,larb-id = <23>; 2886 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2887 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2888 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2889 clock-names = "apb", "smi"; 2890 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2891 }; 2892 2893 vdecsys_soc: clock-controller@1800f000 { 2894 compatible = "mediatek,mt8195-vdecsys_soc"; 2895 reg = <0 0x1800f000 0 0x1000>; 2896 #clock-cells = <1>; 2897 }; 2898 2899 larb21: larb@1802e000 { 2900 compatible = "mediatek,mt8195-smi-larb"; 2901 reg = <0 0x1802e000 0 0x1000>; 2902 mediatek,larb-id = <21>; 2903 mediatek,smi = <&smi_common_vdo>; 2904 clocks = <&vdecsys CLK_VDEC_LARB1>, 2905 <&vdecsys CLK_VDEC_LARB1>; 2906 clock-names = "apb", "smi"; 2907 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2908 }; 2909 2910 vdecsys: clock-controller@1802f000 { 2911 compatible = "mediatek,mt8195-vdecsys"; 2912 reg = <0 0x1802f000 0 0x1000>; 2913 #clock-cells = <1>; 2914 }; 2915 2916 larb22: larb@1803e000 { 2917 compatible = "mediatek,mt8195-smi-larb"; 2918 reg = <0 0x1803e000 0 0x1000>; 2919 mediatek,larb-id = <22>; 2920 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2921 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2922 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2923 clock-names = "apb", "smi"; 2924 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2925 }; 2926 2927 vdecsys_core1: clock-controller@1803f000 { 2928 compatible = "mediatek,mt8195-vdecsys_core1"; 2929 reg = <0 0x1803f000 0 0x1000>; 2930 #clock-cells = <1>; 2931 }; 2932 2933 apusys_pll: clock-controller@190f3000 { 2934 compatible = "mediatek,mt8195-apusys_pll"; 2935 reg = <0 0x190f3000 0 0x1000>; 2936 #clock-cells = <1>; 2937 }; 2938 2939 vencsys: clock-controller@1a000000 { 2940 compatible = "mediatek,mt8195-vencsys"; 2941 reg = <0 0x1a000000 0 0x1000>; 2942 #clock-cells = <1>; 2943 }; 2944 2945 larb19: larb@1a010000 { 2946 compatible = "mediatek,mt8195-smi-larb"; 2947 reg = <0 0x1a010000 0 0x1000>; 2948 mediatek,larb-id = <19>; 2949 mediatek,smi = <&smi_common_vdo>; 2950 clocks = <&vencsys CLK_VENC_VENC>, 2951 <&vencsys CLK_VENC_GALS>; 2952 clock-names = "apb", "smi"; 2953 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2954 }; 2955 2956 venc: video-codec@1a020000 { 2957 compatible = "mediatek,mt8195-vcodec-enc"; 2958 reg = <0 0x1a020000 0 0x10000>; 2959 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2960 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2961 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2962 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2963 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2964 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2965 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2966 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2967 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2968 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2969 mediatek,scp = <&scp>; 2970 clocks = <&vencsys CLK_VENC_VENC>; 2971 clock-names = "venc_sel"; 2972 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2973 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2974 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2975 #address-cells = <2>; 2976 #size-cells = <2>; 2977 }; 2978 2979 jpgdec-master { 2980 compatible = "mediatek,mt8195-jpgdec"; 2981 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2982 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2983 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2984 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2985 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2986 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2987 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2988 #address-cells = <2>; 2989 #size-cells = <2>; 2990 ranges; 2991 2992 jpgdec@1a040000 { 2993 compatible = "mediatek,mt8195-jpgdec-hw"; 2994 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2995 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2996 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2997 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2998 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2999 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3000 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3001 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 3002 clocks = <&vencsys CLK_VENC_JPGDEC>; 3003 clock-names = "jpgdec"; 3004 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 3005 }; 3006 3007 jpgdec@1a050000 { 3008 compatible = "mediatek,mt8195-jpgdec-hw"; 3009 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 3010 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3011 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3012 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3013 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3014 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3015 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3016 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3017 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3018 clock-names = "jpgdec"; 3019 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3020 }; 3021 3022 jpgdec@1b040000 { 3023 compatible = "mediatek,mt8195-jpgdec-hw"; 3024 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 3025 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3026 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3027 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3028 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3029 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3030 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3031 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3032 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3033 clock-names = "jpgdec"; 3034 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3035 }; 3036 }; 3037 3038 vencsys_core1: clock-controller@1b000000 { 3039 compatible = "mediatek,mt8195-vencsys_core1"; 3040 reg = <0 0x1b000000 0 0x1000>; 3041 #clock-cells = <1>; 3042 }; 3043 3044 vdosys0: syscon@1c01a000 { 3045 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3046 reg = <0 0x1c01a000 0 0x1000>; 3047 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3048 #clock-cells = <1>; 3049 }; 3050 3051 3052 jpgenc-master { 3053 compatible = "mediatek,mt8195-jpgenc"; 3054 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3055 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3056 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3057 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3058 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3059 #address-cells = <2>; 3060 #size-cells = <2>; 3061 ranges; 3062 3063 jpgenc@1a030000 { 3064 compatible = "mediatek,mt8195-jpgenc-hw"; 3065 reg = <0 0x1a030000 0 0x10000>; 3066 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3067 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3068 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3069 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3070 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3071 clocks = <&vencsys CLK_VENC_JPGENC>; 3072 clock-names = "jpgenc"; 3073 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3074 }; 3075 3076 jpgenc@1b030000 { 3077 compatible = "mediatek,mt8195-jpgenc-hw"; 3078 reg = <0 0x1b030000 0 0x10000>; 3079 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3080 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3081 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3082 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3083 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3084 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3085 clock-names = "jpgenc"; 3086 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3087 }; 3088 }; 3089 3090 larb20: larb@1b010000 { 3091 compatible = "mediatek,mt8195-smi-larb"; 3092 reg = <0 0x1b010000 0 0x1000>; 3093 mediatek,larb-id = <20>; 3094 mediatek,smi = <&smi_common_vpp>; 3095 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 3096 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3097 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3098 clock-names = "apb", "smi", "gals"; 3099 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3100 }; 3101 3102 ovl0: ovl@1c000000 { 3103 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 3104 reg = <0 0x1c000000 0 0x1000>; 3105 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3106 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3107 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3108 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3109 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3110 }; 3111 3112 rdma0: rdma@1c002000 { 3113 compatible = "mediatek,mt8195-disp-rdma"; 3114 reg = <0 0x1c002000 0 0x1000>; 3115 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3116 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3117 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3118 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3119 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3120 }; 3121 3122 color0: color@1c003000 { 3123 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3124 reg = <0 0x1c003000 0 0x1000>; 3125 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3126 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3127 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3128 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3129 }; 3130 3131 ccorr0: ccorr@1c004000 { 3132 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3133 reg = <0 0x1c004000 0 0x1000>; 3134 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3135 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3136 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3137 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3138 }; 3139 3140 aal0: aal@1c005000 { 3141 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3142 reg = <0 0x1c005000 0 0x1000>; 3143 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3144 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3145 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3146 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3147 }; 3148 3149 gamma0: gamma@1c006000 { 3150 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3151 reg = <0 0x1c006000 0 0x1000>; 3152 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3153 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3154 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3155 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3156 }; 3157 3158 dither0: dither@1c007000 { 3159 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3160 reg = <0 0x1c007000 0 0x1000>; 3161 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3162 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3163 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3164 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3165 }; 3166 3167 dsi0: dsi@1c008000 { 3168 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3169 reg = <0 0x1c008000 0 0x1000>; 3170 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3171 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3172 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3173 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3174 <&mipi_tx0>; 3175 clock-names = "engine", "digital", "hs"; 3176 phys = <&mipi_tx0>; 3177 phy-names = "dphy"; 3178 status = "disabled"; 3179 }; 3180 3181 dsc0: dsc@1c009000 { 3182 compatible = "mediatek,mt8195-disp-dsc"; 3183 reg = <0 0x1c009000 0 0x1000>; 3184 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3185 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3186 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3187 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3188 }; 3189 3190 dsi1: dsi@1c012000 { 3191 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3192 reg = <0 0x1c012000 0 0x1000>; 3193 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3194 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3195 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3196 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3197 <&mipi_tx1>; 3198 clock-names = "engine", "digital", "hs"; 3199 phys = <&mipi_tx1>; 3200 phy-names = "dphy"; 3201 status = "disabled"; 3202 }; 3203 3204 merge0: merge@1c014000 { 3205 compatible = "mediatek,mt8195-disp-merge"; 3206 reg = <0 0x1c014000 0 0x1000>; 3207 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3208 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3209 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3210 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3211 }; 3212 3213 dp_intf0: dp-intf@1c015000 { 3214 compatible = "mediatek,mt8195-dp-intf"; 3215 reg = <0 0x1c015000 0 0x1000>; 3216 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3217 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 3218 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3219 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3220 clock-names = "engine", "pixel", "pll"; 3221 status = "disabled"; 3222 }; 3223 3224 mutex: mutex@1c016000 { 3225 compatible = "mediatek,mt8195-disp-mutex"; 3226 reg = <0 0x1c016000 0 0x1000>; 3227 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3228 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3229 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3230 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3231 }; 3232 3233 larb0: larb@1c018000 { 3234 compatible = "mediatek,mt8195-smi-larb"; 3235 reg = <0 0x1c018000 0 0x1000>; 3236 mediatek,larb-id = <0>; 3237 mediatek,smi = <&smi_common_vdo>; 3238 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3239 <&vdosys0 CLK_VDO0_SMI_LARB>, 3240 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3241 clock-names = "apb", "smi", "gals"; 3242 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3243 }; 3244 3245 larb1: larb@1c019000 { 3246 compatible = "mediatek,mt8195-smi-larb"; 3247 reg = <0 0x1c019000 0 0x1000>; 3248 mediatek,larb-id = <1>; 3249 mediatek,smi = <&smi_common_vpp>; 3250 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3251 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3252 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3253 clock-names = "apb", "smi", "gals"; 3254 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3255 }; 3256 3257 vdosys1: syscon@1c100000 { 3258 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3259 reg = <0 0x1c100000 0 0x1000>; 3260 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3261 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3262 #clock-cells = <1>; 3263 #reset-cells = <1>; 3264 }; 3265 3266 smi_common_vdo: smi@1c01b000 { 3267 compatible = "mediatek,mt8195-smi-common-vdo"; 3268 reg = <0 0x1c01b000 0 0x1000>; 3269 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3270 <&vdosys0 CLK_VDO0_SMI_EMI>, 3271 <&vdosys0 CLK_VDO0_SMI_RSI>, 3272 <&vdosys0 CLK_VDO0_SMI_GALS>; 3273 clock-names = "apb", "smi", "gals0", "gals1"; 3274 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3275 3276 }; 3277 3278 iommu_vdo: iommu@1c01f000 { 3279 compatible = "mediatek,mt8195-iommu-vdo"; 3280 reg = <0 0x1c01f000 0 0x1000>; 3281 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3282 &larb10 &larb11 &larb13 &larb17 3283 &larb19 &larb21 &larb24 &larb25 3284 &larb28>; 3285 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3286 #iommu-cells = <1>; 3287 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3288 clock-names = "bclk"; 3289 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3290 }; 3291 3292 mutex1: mutex@1c101000 { 3293 compatible = "mediatek,mt8195-disp-mutex"; 3294 reg = <0 0x1c101000 0 0x1000>; 3295 reg-names = "vdo1_mutex"; 3296 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3297 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3298 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3299 clock-names = "vdo1_mutex"; 3300 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3301 }; 3302 3303 larb2: larb@1c102000 { 3304 compatible = "mediatek,mt8195-smi-larb"; 3305 reg = <0 0x1c102000 0 0x1000>; 3306 mediatek,larb-id = <2>; 3307 mediatek,smi = <&smi_common_vdo>; 3308 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3309 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3310 <&vdosys1 CLK_VDO1_GALS>; 3311 clock-names = "apb", "smi", "gals"; 3312 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3313 }; 3314 3315 larb3: larb@1c103000 { 3316 compatible = "mediatek,mt8195-smi-larb"; 3317 reg = <0 0x1c103000 0 0x1000>; 3318 mediatek,larb-id = <3>; 3319 mediatek,smi = <&smi_common_vpp>; 3320 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3321 <&vdosys1 CLK_VDO1_GALS>, 3322 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3323 clock-names = "apb", "smi", "gals"; 3324 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3325 }; 3326 3327 vdo1_rdma0: dma-controller@1c104000 { 3328 compatible = "mediatek,mt8195-vdo1-rdma"; 3329 reg = <0 0x1c104000 0 0x1000>; 3330 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3331 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3332 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3333 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3334 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3335 #dma-cells = <1>; 3336 }; 3337 3338 vdo1_rdma1: dma-controller@1c105000 { 3339 compatible = "mediatek,mt8195-vdo1-rdma"; 3340 reg = <0 0x1c105000 0 0x1000>; 3341 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3342 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3343 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3344 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3345 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3346 #dma-cells = <1>; 3347 }; 3348 3349 vdo1_rdma2: dma-controller@1c106000 { 3350 compatible = "mediatek,mt8195-vdo1-rdma"; 3351 reg = <0 0x1c106000 0 0x1000>; 3352 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3353 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3354 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3355 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3356 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3357 #dma-cells = <1>; 3358 }; 3359 3360 vdo1_rdma3: dma-controller@1c107000 { 3361 compatible = "mediatek,mt8195-vdo1-rdma"; 3362 reg = <0 0x1c107000 0 0x1000>; 3363 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3364 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3365 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3366 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3367 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3368 #dma-cells = <1>; 3369 }; 3370 3371 vdo1_rdma4: dma-controller@1c108000 { 3372 compatible = "mediatek,mt8195-vdo1-rdma"; 3373 reg = <0 0x1c108000 0 0x1000>; 3374 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3375 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3376 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3377 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3378 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3379 #dma-cells = <1>; 3380 }; 3381 3382 vdo1_rdma5: dma-controller@1c109000 { 3383 compatible = "mediatek,mt8195-vdo1-rdma"; 3384 reg = <0 0x1c109000 0 0x1000>; 3385 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3386 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3387 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3388 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3389 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3390 #dma-cells = <1>; 3391 }; 3392 3393 vdo1_rdma6: dma-controller@1c10a000 { 3394 compatible = "mediatek,mt8195-vdo1-rdma"; 3395 reg = <0 0x1c10a000 0 0x1000>; 3396 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3397 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3398 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3399 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3400 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3401 #dma-cells = <1>; 3402 }; 3403 3404 vdo1_rdma7: dma-controller@1c10b000 { 3405 compatible = "mediatek,mt8195-vdo1-rdma"; 3406 reg = <0 0x1c10b000 0 0x1000>; 3407 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3408 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3409 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3410 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3411 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3412 #dma-cells = <1>; 3413 }; 3414 3415 merge1: vpp-merge@1c10c000 { 3416 compatible = "mediatek,mt8195-disp-merge"; 3417 reg = <0 0x1c10c000 0 0x1000>; 3418 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3419 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3420 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3421 clock-names = "merge","merge_async"; 3422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3423 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3424 mediatek,merge-mute; 3425 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3426 }; 3427 3428 merge2: vpp-merge@1c10d000 { 3429 compatible = "mediatek,mt8195-disp-merge"; 3430 reg = <0 0x1c10d000 0 0x1000>; 3431 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3432 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3433 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3434 clock-names = "merge","merge_async"; 3435 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3436 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3437 mediatek,merge-mute; 3438 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3439 }; 3440 3441 merge3: vpp-merge@1c10e000 { 3442 compatible = "mediatek,mt8195-disp-merge"; 3443 reg = <0 0x1c10e000 0 0x1000>; 3444 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3445 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3446 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3447 clock-names = "merge","merge_async"; 3448 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3449 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3450 mediatek,merge-mute; 3451 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3452 }; 3453 3454 merge4: vpp-merge@1c10f000 { 3455 compatible = "mediatek,mt8195-disp-merge"; 3456 reg = <0 0x1c10f000 0 0x1000>; 3457 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3458 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3459 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3460 clock-names = "merge","merge_async"; 3461 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3462 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3463 mediatek,merge-mute; 3464 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3465 }; 3466 3467 merge5: vpp-merge@1c110000 { 3468 compatible = "mediatek,mt8195-disp-merge"; 3469 reg = <0 0x1c110000 0 0x1000>; 3470 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3471 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3472 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3473 clock-names = "merge","merge_async"; 3474 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3475 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3476 mediatek,merge-fifo-en; 3477 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3478 }; 3479 3480 dp_intf1: dp-intf@1c113000 { 3481 compatible = "mediatek,mt8195-dp-intf"; 3482 reg = <0 0x1c113000 0 0x1000>; 3483 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3484 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3485 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3486 <&vdosys1 CLK_VDO1_DPINTF>, 3487 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3488 clock-names = "engine", "pixel", "pll"; 3489 status = "disabled"; 3490 }; 3491 3492 ethdr0: hdr-engine@1c114000 { 3493 compatible = "mediatek,mt8195-disp-ethdr"; 3494 reg = <0 0x1c114000 0 0x1000>, 3495 <0 0x1c115000 0 0x1000>, 3496 <0 0x1c117000 0 0x1000>, 3497 <0 0x1c119000 0 0x1000>, 3498 <0 0x1c11a000 0 0x1000>, 3499 <0 0x1c11b000 0 0x1000>, 3500 <0 0x1c11c000 0 0x1000>; 3501 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3502 "vdo_be", "adl_ds"; 3503 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3504 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3505 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3506 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3507 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3508 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3509 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3510 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3511 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3512 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3513 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3514 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3515 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3516 <&vdosys1 CLK_VDO1_26M_SLOW>, 3517 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3518 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3519 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3520 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3521 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3522 <&topckgen CLK_TOP_ETHDR>; 3523 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3524 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3525 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3526 "ethdr_top"; 3527 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3528 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3529 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3530 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3531 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3532 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3533 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3534 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3535 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3536 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3537 "gfx_fe1_async", "vdo_be_async"; 3538 }; 3539 3540 edp_tx: edp-tx@1c500000 { 3541 compatible = "mediatek,mt8195-edp-tx"; 3542 reg = <0 0x1c500000 0 0x8000>; 3543 nvmem-cells = <&dp_calibration>; 3544 nvmem-cell-names = "dp_calibration_data"; 3545 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3546 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3547 max-linkrate-mhz = <8100>; 3548 status = "disabled"; 3549 }; 3550 3551 dp_tx: dp-tx@1c600000 { 3552 compatible = "mediatek,mt8195-dp-tx"; 3553 reg = <0 0x1c600000 0 0x8000>; 3554 nvmem-cells = <&dp_calibration>; 3555 nvmem-cell-names = "dp_calibration_data"; 3556 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3557 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3558 max-linkrate-mhz = <8100>; 3559 status = "disabled"; 3560 }; 3561 }; 3562 3563 thermal_zones: thermal-zones { 3564 cpu0-thermal { 3565 polling-delay = <1000>; 3566 polling-delay-passive = <250>; 3567 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3568 3569 trips { 3570 cpu0_alert: trip-alert { 3571 temperature = <85000>; 3572 hysteresis = <2000>; 3573 type = "passive"; 3574 }; 3575 3576 cpu0_crit: trip-crit { 3577 temperature = <100000>; 3578 hysteresis = <2000>; 3579 type = "critical"; 3580 }; 3581 }; 3582 3583 cooling-maps { 3584 map0 { 3585 trip = <&cpu0_alert>; 3586 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3587 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3588 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3589 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3590 }; 3591 }; 3592 }; 3593 3594 cpu1-thermal { 3595 polling-delay = <1000>; 3596 polling-delay-passive = <250>; 3597 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3598 3599 trips { 3600 cpu1_alert: trip-alert { 3601 temperature = <85000>; 3602 hysteresis = <2000>; 3603 type = "passive"; 3604 }; 3605 3606 cpu1_crit: trip-crit { 3607 temperature = <100000>; 3608 hysteresis = <2000>; 3609 type = "critical"; 3610 }; 3611 }; 3612 3613 cooling-maps { 3614 map0 { 3615 trip = <&cpu1_alert>; 3616 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3617 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3618 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3619 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3620 }; 3621 }; 3622 }; 3623 3624 cpu2-thermal { 3625 polling-delay = <1000>; 3626 polling-delay-passive = <250>; 3627 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3628 3629 trips { 3630 cpu2_alert: trip-alert { 3631 temperature = <85000>; 3632 hysteresis = <2000>; 3633 type = "passive"; 3634 }; 3635 3636 cpu2_crit: trip-crit { 3637 temperature = <100000>; 3638 hysteresis = <2000>; 3639 type = "critical"; 3640 }; 3641 }; 3642 3643 cooling-maps { 3644 map0 { 3645 trip = <&cpu2_alert>; 3646 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3650 }; 3651 }; 3652 }; 3653 3654 cpu3-thermal { 3655 polling-delay = <1000>; 3656 polling-delay-passive = <250>; 3657 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3658 3659 trips { 3660 cpu3_alert: trip-alert { 3661 temperature = <85000>; 3662 hysteresis = <2000>; 3663 type = "passive"; 3664 }; 3665 3666 cpu3_crit: trip-crit { 3667 temperature = <100000>; 3668 hysteresis = <2000>; 3669 type = "critical"; 3670 }; 3671 }; 3672 3673 cooling-maps { 3674 map0 { 3675 trip = <&cpu3_alert>; 3676 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3677 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3678 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3679 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3680 }; 3681 }; 3682 }; 3683 3684 cpu4-thermal { 3685 polling-delay = <1000>; 3686 polling-delay-passive = <250>; 3687 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3688 3689 trips { 3690 cpu4_alert: trip-alert { 3691 temperature = <85000>; 3692 hysteresis = <2000>; 3693 type = "passive"; 3694 }; 3695 3696 cpu4_crit: trip-crit { 3697 temperature = <100000>; 3698 hysteresis = <2000>; 3699 type = "critical"; 3700 }; 3701 }; 3702 3703 cooling-maps { 3704 map0 { 3705 trip = <&cpu4_alert>; 3706 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3707 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3710 }; 3711 }; 3712 }; 3713 3714 cpu5-thermal { 3715 polling-delay = <1000>; 3716 polling-delay-passive = <250>; 3717 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3718 3719 trips { 3720 cpu5_alert: trip-alert { 3721 temperature = <85000>; 3722 hysteresis = <2000>; 3723 type = "passive"; 3724 }; 3725 3726 cpu5_crit: trip-crit { 3727 temperature = <100000>; 3728 hysteresis = <2000>; 3729 type = "critical"; 3730 }; 3731 }; 3732 3733 cooling-maps { 3734 map0 { 3735 trip = <&cpu5_alert>; 3736 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3740 }; 3741 }; 3742 }; 3743 3744 cpu6-thermal { 3745 polling-delay = <1000>; 3746 polling-delay-passive = <250>; 3747 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3748 3749 trips { 3750 cpu6_alert: trip-alert { 3751 temperature = <85000>; 3752 hysteresis = <2000>; 3753 type = "passive"; 3754 }; 3755 3756 cpu6_crit: trip-crit { 3757 temperature = <100000>; 3758 hysteresis = <2000>; 3759 type = "critical"; 3760 }; 3761 }; 3762 3763 cooling-maps { 3764 map0 { 3765 trip = <&cpu6_alert>; 3766 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3770 }; 3771 }; 3772 }; 3773 3774 cpu7-thermal { 3775 polling-delay = <1000>; 3776 polling-delay-passive = <250>; 3777 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3778 3779 trips { 3780 cpu7_alert: trip-alert { 3781 temperature = <85000>; 3782 hysteresis = <2000>; 3783 type = "passive"; 3784 }; 3785 3786 cpu7_crit: trip-crit { 3787 temperature = <100000>; 3788 hysteresis = <2000>; 3789 type = "critical"; 3790 }; 3791 }; 3792 3793 cooling-maps { 3794 map0 { 3795 trip = <&cpu7_alert>; 3796 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3800 }; 3801 }; 3802 }; 3803 3804 vpu0-thermal { 3805 polling-delay = <1000>; 3806 polling-delay-passive = <250>; 3807 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3808 3809 trips { 3810 vpu0_alert: trip-alert { 3811 temperature = <85000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 vpu0_crit: trip-crit { 3817 temperature = <100000>; 3818 hysteresis = <2000>; 3819 type = "critical"; 3820 }; 3821 }; 3822 }; 3823 3824 vpu1-thermal { 3825 polling-delay = <1000>; 3826 polling-delay-passive = <250>; 3827 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3828 3829 trips { 3830 vpu1_alert: trip-alert { 3831 temperature = <85000>; 3832 hysteresis = <2000>; 3833 type = "passive"; 3834 }; 3835 3836 vpu1_crit: trip-crit { 3837 temperature = <100000>; 3838 hysteresis = <2000>; 3839 type = "critical"; 3840 }; 3841 }; 3842 }; 3843 3844 gpu0-thermal { 3845 polling-delay = <1000>; 3846 polling-delay-passive = <250>; 3847 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3848 3849 trips { 3850 gpu0_alert: trip-alert { 3851 temperature = <85000>; 3852 hysteresis = <2000>; 3853 type = "passive"; 3854 }; 3855 3856 gpu0_crit: trip-crit { 3857 temperature = <100000>; 3858 hysteresis = <2000>; 3859 type = "critical"; 3860 }; 3861 }; 3862 }; 3863 3864 gpu1-thermal { 3865 polling-delay = <1000>; 3866 polling-delay-passive = <250>; 3867 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3868 3869 trips { 3870 gpu1_alert: trip-alert { 3871 temperature = <85000>; 3872 hysteresis = <2000>; 3873 type = "passive"; 3874 }; 3875 3876 gpu1_crit: trip-crit { 3877 temperature = <100000>; 3878 hysteresis = <2000>; 3879 type = "critical"; 3880 }; 3881 }; 3882 }; 3883 3884 vdec-thermal { 3885 polling-delay = <1000>; 3886 polling-delay-passive = <250>; 3887 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3888 3889 trips { 3890 vdec_alert: trip-alert { 3891 temperature = <85000>; 3892 hysteresis = <2000>; 3893 type = "passive"; 3894 }; 3895 3896 vdec_crit: trip-crit { 3897 temperature = <100000>; 3898 hysteresis = <2000>; 3899 type = "critical"; 3900 }; 3901 }; 3902 }; 3903 3904 img-thermal { 3905 polling-delay = <1000>; 3906 polling-delay-passive = <250>; 3907 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3908 3909 trips { 3910 img_alert: trip-alert { 3911 temperature = <85000>; 3912 hysteresis = <2000>; 3913 type = "passive"; 3914 }; 3915 3916 img_crit: trip-crit { 3917 temperature = <100000>; 3918 hysteresis = <2000>; 3919 type = "critical"; 3920 }; 3921 }; 3922 }; 3923 3924 infra-thermal { 3925 polling-delay = <1000>; 3926 polling-delay-passive = <250>; 3927 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3928 3929 trips { 3930 infra_alert: trip-alert { 3931 temperature = <85000>; 3932 hysteresis = <2000>; 3933 type = "passive"; 3934 }; 3935 3936 infra_crit: trip-crit { 3937 temperature = <100000>; 3938 hysteresis = <2000>; 3939 type = "critical"; 3940 }; 3941 }; 3942 }; 3943 3944 cam0-thermal { 3945 polling-delay = <1000>; 3946 polling-delay-passive = <250>; 3947 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3948 3949 trips { 3950 cam0_alert: trip-alert { 3951 temperature = <85000>; 3952 hysteresis = <2000>; 3953 type = "passive"; 3954 }; 3955 3956 cam0_crit: trip-crit { 3957 temperature = <100000>; 3958 hysteresis = <2000>; 3959 type = "critical"; 3960 }; 3961 }; 3962 }; 3963 3964 cam1-thermal { 3965 polling-delay = <1000>; 3966 polling-delay-passive = <250>; 3967 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 3968 3969 trips { 3970 cam1_alert: trip-alert { 3971 temperature = <85000>; 3972 hysteresis = <2000>; 3973 type = "passive"; 3974 }; 3975 3976 cam1_crit: trip-crit { 3977 temperature = <100000>; 3978 hysteresis = <2000>; 3979 type = "critical"; 3980 }; 3981 }; 3982 }; 3983 }; 3984}; 3985