mt8195.dtsi (7dd5bc578974a96025cb120012706bb4bf4e41fc) mt8195.dtsi (04cd978316c992711f341b0c91fdb44f2c21836b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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675 };
676 };
677
678 watchdog: watchdog@10007000 {
679 compatible = "mediatek,mt8195-wdt",
680 "mediatek,mt6589-wdt";
681 mediatek,disable-extrst;
682 reg = <0 0x10007000 0 0x100>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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675 };
676 };
677
678 watchdog: watchdog@10007000 {
679 compatible = "mediatek,mt8195-wdt",
680 "mediatek,mt6589-wdt";
681 mediatek,disable-extrst;
682 reg = <0 0x10007000 0 0x100>;
683 #reset-cells = <1>;
683 };
684
685 apmixedsys: syscon@1000c000 {
686 compatible = "mediatek,mt8195-apmixedsys", "syscon";
687 reg = <0 0x1000c000 0 0x1000>;
688 #clock-cells = <1>;
689 };
690

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777 };
778
779 afe: mt8195-afe-pcm@10890000 {
780 compatible = "mediatek,mt8195-audio";
781 reg = <0 0x10890000 0 0x10000>;
782 mediatek,topckgen = <&topckgen>;
783 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
784 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
684 };
685
686 apmixedsys: syscon@1000c000 {
687 compatible = "mediatek,mt8195-apmixedsys", "syscon";
688 reg = <0 0x1000c000 0 0x1000>;
689 #clock-cells = <1>;
690 };
691

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778 };
779
780 afe: mt8195-afe-pcm@10890000 {
781 compatible = "mediatek,mt8195-audio";
782 reg = <0 0x10890000 0 0x10000>;
783 mediatek,topckgen = <&topckgen>;
784 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
785 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
786 resets = <&watchdog 14>;
787 reset-names = "audiosys";
785 clocks = <&clk26m>,
786 <&apmixedsys CLK_APMIXED_APLL1>,
787 <&apmixedsys CLK_APMIXED_APLL2>,
788 <&topckgen CLK_TOP_APLL12_DIV0>,
789 <&topckgen CLK_TOP_APLL12_DIV1>,
790 <&topckgen CLK_TOP_APLL12_DIV2>,
791 <&topckgen CLK_TOP_APLL12_DIV3>,
792 <&topckgen CLK_TOP_APLL12_DIV9>,

--- 790 unchanged lines hidden --- 		788 clocks = <&clk26m>,
789 <&apmixedsys CLK_APMIXED_APLL1>,
790 <&apmixedsys CLK_APMIXED_APLL2>,
791 <&topckgen CLK_TOP_APLL12_DIV0>,
792 <&topckgen CLK_TOP_APLL12_DIV1>,
793 <&topckgen CLK_TOP_APLL12_DIV2>,
794 <&topckgen CLK_TOP_APLL12_DIV3>,
795 <&topckgen CLK_TOP_APLL12_DIV9>,

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