1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/power/mt8195-power.h> 14 15/ { 16 compatible = "mediatek,mt8195"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x000>; 29 enable-method = "psci"; 30 performance-domains = <&performance 0>; 31 clock-frequency = <1701000000>; 32 capacity-dmips-mhz = <578>; 33 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 }; 37 38 cpu1: cpu@100 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x100>; 42 enable-method = "psci"; 43 performance-domains = <&performance 0>; 44 clock-frequency = <1701000000>; 45 capacity-dmips-mhz = <578>; 46 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 47 next-level-cache = <&l2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 cpu2: cpu@200 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x200>; 55 enable-method = "psci"; 56 performance-domains = <&performance 0>; 57 clock-frequency = <1701000000>; 58 capacity-dmips-mhz = <578>; 59 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 60 next-level-cache = <&l2_0>; 61 #cooling-cells = <2>; 62 }; 63 64 cpu3: cpu@300 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x300>; 68 enable-method = "psci"; 69 performance-domains = <&performance 0>; 70 clock-frequency = <1701000000>; 71 capacity-dmips-mhz = <578>; 72 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 73 next-level-cache = <&l2_0>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu4: cpu@400 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a78"; 80 reg = <0x400>; 81 enable-method = "psci"; 82 performance-domains = <&performance 1>; 83 clock-frequency = <2171000000>; 84 capacity-dmips-mhz = <1024>; 85 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 86 next-level-cache = <&l2_1>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a78"; 93 reg = <0x500>; 94 enable-method = "psci"; 95 performance-domains = <&performance 1>; 96 clock-frequency = <2171000000>; 97 capacity-dmips-mhz = <1024>; 98 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 99 next-level-cache = <&l2_1>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu6: cpu@600 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a78"; 106 reg = <0x600>; 107 enable-method = "psci"; 108 performance-domains = <&performance 1>; 109 clock-frequency = <2171000000>; 110 capacity-dmips-mhz = <1024>; 111 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu7: cpu@700 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a78"; 119 reg = <0x700>; 120 enable-method = "psci"; 121 performance-domains = <&performance 1>; 122 clock-frequency = <2171000000>; 123 capacity-dmips-mhz = <1024>; 124 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 125 next-level-cache = <&l2_1>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu-map { 130 cluster0 { 131 core0 { 132 cpu = <&cpu0>; 133 }; 134 135 core1 { 136 cpu = <&cpu1>; 137 }; 138 139 core2 { 140 cpu = <&cpu2>; 141 }; 142 143 core3 { 144 cpu = <&cpu3>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu4>; 151 }; 152 153 core1 { 154 cpu = <&cpu5>; 155 }; 156 157 core2 { 158 cpu = <&cpu6>; 159 }; 160 161 core3 { 162 cpu = <&cpu7>; 163 }; 164 }; 165 }; 166 167 idle-states { 168 entry-method = "psci"; 169 170 cpu_off_l: cpu-off-l { 171 compatible = "arm,idle-state"; 172 arm,psci-suspend-param = <0x00010001>; 173 local-timer-stop; 174 entry-latency-us = <50>; 175 exit-latency-us = <95>; 176 min-residency-us = <580>; 177 }; 178 179 cpu_off_b: cpu-off-b { 180 compatible = "arm,idle-state"; 181 arm,psci-suspend-param = <0x00010001>; 182 local-timer-stop; 183 entry-latency-us = <45>; 184 exit-latency-us = <140>; 185 min-residency-us = <740>; 186 }; 187 188 cluster_off_l: cluster-off-l { 189 compatible = "arm,idle-state"; 190 arm,psci-suspend-param = <0x01010002>; 191 local-timer-stop; 192 entry-latency-us = <55>; 193 exit-latency-us = <155>; 194 min-residency-us = <840>; 195 }; 196 197 cluster_off_b: cluster-off-b { 198 compatible = "arm,idle-state"; 199 arm,psci-suspend-param = <0x01010002>; 200 local-timer-stop; 201 entry-latency-us = <50>; 202 exit-latency-us = <200>; 203 min-residency-us = <1000>; 204 }; 205 }; 206 207 l2_0: l2-cache0 { 208 compatible = "cache"; 209 next-level-cache = <&l3_0>; 210 }; 211 212 l2_1: l2-cache1 { 213 compatible = "cache"; 214 next-level-cache = <&l3_0>; 215 }; 216 217 l3_0: l3-cache { 218 compatible = "cache"; 219 }; 220 }; 221 222 dsu-pmu { 223 compatible = "arm,dsu-pmu"; 224 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 225 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 226 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 227 }; 228 229 dmic_codec: dmic-codec { 230 compatible = "dmic-codec"; 231 num-channels = <2>; 232 wakeup-delay-ms = <50>; 233 }; 234 235 sound: mt8195-sound { 236 mediatek,platform = <&afe>; 237 status = "disabled"; 238 }; 239 240 clk26m: oscillator-26m { 241 compatible = "fixed-clock"; 242 #clock-cells = <0>; 243 clock-frequency = <26000000>; 244 clock-output-names = "clk26m"; 245 }; 246 247 clk32k: oscillator-32k { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <32768>; 251 clock-output-names = "clk32k"; 252 }; 253 254 performance: performance-controller@11bc10 { 255 compatible = "mediatek,cpufreq-hw"; 256 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 257 #performance-domain-cells = <1>; 258 }; 259 260 pmu-a55 { 261 compatible = "arm,cortex-a55-pmu"; 262 interrupt-parent = <&gic>; 263 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 264 }; 265 266 pmu-a78 { 267 compatible = "arm,cortex-a78-pmu"; 268 interrupt-parent = <&gic>; 269 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 270 }; 271 272 psci { 273 compatible = "arm,psci-1.0"; 274 method = "smc"; 275 }; 276 277 timer: timer { 278 compatible = "arm,armv8-timer"; 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 281 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 282 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 283 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 284 }; 285 286 soc { 287 #address-cells = <2>; 288 #size-cells = <2>; 289 compatible = "simple-bus"; 290 ranges; 291 292 gic: interrupt-controller@c000000 { 293 compatible = "arm,gic-v3"; 294 #interrupt-cells = <4>; 295 #redistributor-regions = <1>; 296 interrupt-parent = <&gic>; 297 interrupt-controller; 298 reg = <0 0x0c000000 0 0x40000>, 299 <0 0x0c040000 0 0x200000>; 300 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 301 302 ppi-partitions { 303 ppi_cluster0: interrupt-partition-0 { 304 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 305 }; 306 307 ppi_cluster1: interrupt-partition-1 { 308 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 309 }; 310 }; 311 }; 312 313 topckgen: syscon@10000000 { 314 compatible = "mediatek,mt8195-topckgen", "syscon"; 315 reg = <0 0x10000000 0 0x1000>; 316 #clock-cells = <1>; 317 }; 318 319 infracfg_ao: syscon@10001000 { 320 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 321 reg = <0 0x10001000 0 0x1000>; 322 #clock-cells = <1>; 323 #reset-cells = <1>; 324 }; 325 326 pericfg: syscon@10003000 { 327 compatible = "mediatek,mt8195-pericfg", "syscon"; 328 reg = <0 0x10003000 0 0x1000>; 329 #clock-cells = <1>; 330 }; 331 332 pio: pinctrl@10005000 { 333 compatible = "mediatek,mt8195-pinctrl"; 334 reg = <0 0x10005000 0 0x1000>, 335 <0 0x11d10000 0 0x1000>, 336 <0 0x11d30000 0 0x1000>, 337 <0 0x11d40000 0 0x1000>, 338 <0 0x11e20000 0 0x1000>, 339 <0 0x11eb0000 0 0x1000>, 340 <0 0x11f40000 0 0x1000>, 341 <0 0x1000b000 0 0x1000>; 342 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 343 "iocfg_br", "iocfg_lm", "iocfg_rb", 344 "iocfg_tl", "eint"; 345 gpio-controller; 346 #gpio-cells = <2>; 347 gpio-ranges = <&pio 0 0 144>; 348 interrupt-controller; 349 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 350 #interrupt-cells = <2>; 351 }; 352 353 scpsys: syscon@10006000 { 354 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 355 reg = <0 0x10006000 0 0x1000>; 356 357 /* System Power Manager */ 358 spm: power-controller { 359 compatible = "mediatek,mt8195-power-controller"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 #power-domain-cells = <1>; 363 364 /* power domain of the SoC */ 365 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 366 reg = <MT8195_POWER_DOMAIN_MFG0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #power-domain-cells = <1>; 370 371 power-domain@MT8195_POWER_DOMAIN_MFG1 { 372 reg = <MT8195_POWER_DOMAIN_MFG1>; 373 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 374 clock-names = "mfg"; 375 mediatek,infracfg = <&infracfg_ao>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 #power-domain-cells = <1>; 379 380 power-domain@MT8195_POWER_DOMAIN_MFG2 { 381 reg = <MT8195_POWER_DOMAIN_MFG2>; 382 #power-domain-cells = <0>; 383 }; 384 385 power-domain@MT8195_POWER_DOMAIN_MFG3 { 386 reg = <MT8195_POWER_DOMAIN_MFG3>; 387 #power-domain-cells = <0>; 388 }; 389 390 power-domain@MT8195_POWER_DOMAIN_MFG4 { 391 reg = <MT8195_POWER_DOMAIN_MFG4>; 392 #power-domain-cells = <0>; 393 }; 394 395 power-domain@MT8195_POWER_DOMAIN_MFG5 { 396 reg = <MT8195_POWER_DOMAIN_MFG5>; 397 #power-domain-cells = <0>; 398 }; 399 400 power-domain@MT8195_POWER_DOMAIN_MFG6 { 401 reg = <MT8195_POWER_DOMAIN_MFG6>; 402 #power-domain-cells = <0>; 403 }; 404 }; 405 }; 406 407 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 408 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 409 clocks = <&topckgen CLK_TOP_VPP>, 410 <&topckgen CLK_TOP_CAM>, 411 <&topckgen CLK_TOP_CCU>, 412 <&topckgen CLK_TOP_IMG>, 413 <&topckgen CLK_TOP_VENC>, 414 <&topckgen CLK_TOP_VDEC>, 415 <&topckgen CLK_TOP_WPE_VPP>, 416 <&topckgen CLK_TOP_CFG_VPP0>, 417 <&vppsys0 CLK_VPP0_SMI_COMMON>, 418 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 419 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 420 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 421 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 422 <&vppsys0 CLK_VPP0_GALS_INFRA>, 423 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 424 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 425 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 426 <&vppsys0 CLK_VPP0_SMI_REORDER>, 427 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 428 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 429 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 430 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 431 <&vppsys0 CLK_VPP0_SMI_RSI>, 432 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 433 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 434 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 435 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 436 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 437 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 438 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 439 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 440 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 441 "vppsys0-12", "vppsys0-13", "vppsys0-14", 442 "vppsys0-15", "vppsys0-16", "vppsys0-17", 443 "vppsys0-18"; 444 mediatek,infracfg = <&infracfg_ao>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 #power-domain-cells = <1>; 448 449 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 450 reg = <MT8195_POWER_DOMAIN_VDEC1>; 451 clocks = <&vdecsys CLK_VDEC_LARB1>; 452 clock-names = "vdec1-0"; 453 mediatek,infracfg = <&infracfg_ao>; 454 #power-domain-cells = <0>; 455 }; 456 457 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 458 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 459 mediatek,infracfg = <&infracfg_ao>; 460 #power-domain-cells = <0>; 461 }; 462 463 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 464 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 465 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 466 <&vdosys0 CLK_VDO0_SMI_GALS>, 467 <&vdosys0 CLK_VDO0_SMI_COMMON>, 468 <&vdosys0 CLK_VDO0_SMI_EMI>, 469 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 470 <&vdosys0 CLK_VDO0_SMI_LARB>, 471 <&vdosys0 CLK_VDO0_SMI_RSI>; 472 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 473 "vdosys0-2", "vdosys0-3", 474 "vdosys0-4", "vdosys0-5"; 475 mediatek,infracfg = <&infracfg_ao>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 #power-domain-cells = <1>; 479 480 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 481 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 482 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 483 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 484 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 485 clock-names = "vppsys1", "vppsys1-0", 486 "vppsys1-1"; 487 mediatek,infracfg = <&infracfg_ao>; 488 #power-domain-cells = <0>; 489 }; 490 491 power-domain@MT8195_POWER_DOMAIN_WPESYS { 492 reg = <MT8195_POWER_DOMAIN_WPESYS>; 493 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 494 <&wpesys CLK_WPE_SMI_LARB8>, 495 <&wpesys CLK_WPE_SMI_LARB7_P>, 496 <&wpesys CLK_WPE_SMI_LARB8_P>; 497 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 498 "wepsys-3"; 499 mediatek,infracfg = <&infracfg_ao>; 500 #power-domain-cells = <0>; 501 }; 502 503 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 504 reg = <MT8195_POWER_DOMAIN_VDEC0>; 505 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 506 clock-names = "vdec0-0"; 507 mediatek,infracfg = <&infracfg_ao>; 508 #power-domain-cells = <0>; 509 }; 510 511 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 512 reg = <MT8195_POWER_DOMAIN_VDEC2>; 513 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 514 clock-names = "vdec2-0"; 515 mediatek,infracfg = <&infracfg_ao>; 516 #power-domain-cells = <0>; 517 }; 518 519 power-domain@MT8195_POWER_DOMAIN_VENC { 520 reg = <MT8195_POWER_DOMAIN_VENC>; 521 mediatek,infracfg = <&infracfg_ao>; 522 #power-domain-cells = <0>; 523 }; 524 525 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 526 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 527 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 528 <&vdosys1 CLK_VDO1_SMI_LARB2>, 529 <&vdosys1 CLK_VDO1_SMI_LARB3>, 530 <&vdosys1 CLK_VDO1_GALS>; 531 clock-names = "vdosys1", "vdosys1-0", 532 "vdosys1-1", "vdosys1-2"; 533 mediatek,infracfg = <&infracfg_ao>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 #power-domain-cells = <1>; 537 538 power-domain@MT8195_POWER_DOMAIN_DP_TX { 539 reg = <MT8195_POWER_DOMAIN_DP_TX>; 540 mediatek,infracfg = <&infracfg_ao>; 541 #power-domain-cells = <0>; 542 }; 543 544 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 545 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 546 mediatek,infracfg = <&infracfg_ao>; 547 #power-domain-cells = <0>; 548 }; 549 550 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 551 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 552 clocks = <&topckgen CLK_TOP_HDMI_APB>; 553 clock-names = "hdmi_tx"; 554 #power-domain-cells = <0>; 555 }; 556 }; 557 558 power-domain@MT8195_POWER_DOMAIN_IMG { 559 reg = <MT8195_POWER_DOMAIN_IMG>; 560 clocks = <&imgsys CLK_IMG_LARB9>, 561 <&imgsys CLK_IMG_GALS>; 562 clock-names = "img-0", "img-1"; 563 mediatek,infracfg = <&infracfg_ao>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 #power-domain-cells = <1>; 567 568 power-domain@MT8195_POWER_DOMAIN_DIP { 569 reg = <MT8195_POWER_DOMAIN_DIP>; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@MT8195_POWER_DOMAIN_IPE { 574 reg = <MT8195_POWER_DOMAIN_IPE>; 575 clocks = <&topckgen CLK_TOP_IPE>, 576 <&imgsys CLK_IMG_IPE>, 577 <&ipesys CLK_IPE_SMI_LARB12>; 578 clock-names = "ipe", "ipe-0", "ipe-1"; 579 mediatek,infracfg = <&infracfg_ao>; 580 #power-domain-cells = <0>; 581 }; 582 }; 583 584 power-domain@MT8195_POWER_DOMAIN_CAM { 585 reg = <MT8195_POWER_DOMAIN_CAM>; 586 clocks = <&camsys CLK_CAM_LARB13>, 587 <&camsys CLK_CAM_LARB14>, 588 <&camsys CLK_CAM_CAM2MM0_GALS>, 589 <&camsys CLK_CAM_CAM2MM1_GALS>, 590 <&camsys CLK_CAM_CAM2SYS_GALS>; 591 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 592 "cam-4"; 593 mediatek,infracfg = <&infracfg_ao>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 #power-domain-cells = <1>; 597 598 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 599 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 600 #power-domain-cells = <0>; 601 }; 602 603 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 604 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 605 #power-domain-cells = <0>; 606 }; 607 608 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 609 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 610 #power-domain-cells = <0>; 611 }; 612 }; 613 }; 614 }; 615 616 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 617 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 618 mediatek,infracfg = <&infracfg_ao>; 619 #power-domain-cells = <0>; 620 }; 621 622 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 623 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 629 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 630 #power-domain-cells = <0>; 631 }; 632 633 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 634 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 635 #power-domain-cells = <0>; 636 }; 637 638 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 639 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 640 clocks = <&topckgen CLK_TOP_SENINF>, 641 <&topckgen CLK_TOP_SENINF2>; 642 clock-names = "csi_rx_top", "csi_rx_top1"; 643 #power-domain-cells = <0>; 644 }; 645 646 power-domain@MT8195_POWER_DOMAIN_ETHER { 647 reg = <MT8195_POWER_DOMAIN_ETHER>; 648 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 649 clock-names = "ether"; 650 #power-domain-cells = <0>; 651 }; 652 653 power-domain@MT8195_POWER_DOMAIN_ADSP { 654 reg = <MT8195_POWER_DOMAIN_ADSP>; 655 clocks = <&topckgen CLK_TOP_ADSP>, 656 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 657 clock-names = "adsp", "adsp1"; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 mediatek,infracfg = <&infracfg_ao>; 661 #power-domain-cells = <1>; 662 663 power-domain@MT8195_POWER_DOMAIN_AUDIO { 664 reg = <MT8195_POWER_DOMAIN_AUDIO>; 665 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 666 <&topckgen CLK_TOP_AUD_INTBUS>, 667 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 668 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 669 clock-names = "audio", "audio1", "audio2", 670 "audio3"; 671 mediatek,infracfg = <&infracfg_ao>; 672 #power-domain-cells = <0>; 673 }; 674 }; 675 }; 676 }; 677 678 watchdog: watchdog@10007000 { 679 compatible = "mediatek,mt8195-wdt", 680 "mediatek,mt6589-wdt"; 681 mediatek,disable-extrst; 682 reg = <0 0x10007000 0 0x100>; 683 }; 684 685 apmixedsys: syscon@1000c000 { 686 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 687 reg = <0 0x1000c000 0 0x1000>; 688 #clock-cells = <1>; 689 }; 690 691 systimer: timer@10017000 { 692 compatible = "mediatek,mt8195-timer", 693 "mediatek,mt6765-timer"; 694 reg = <0 0x10017000 0 0x1000>; 695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 696 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 697 }; 698 699 pwrap: pwrap@10024000 { 700 compatible = "mediatek,mt8195-pwrap", "syscon"; 701 reg = <0 0x10024000 0 0x1000>; 702 reg-names = "pwrap"; 703 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 704 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 705 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 706 clock-names = "spi", "wrap"; 707 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 708 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 709 }; 710 711 spmi: spmi@10027000 { 712 compatible = "mediatek,mt8195-spmi"; 713 reg = <0 0x10027000 0 0x000e00>, 714 <0 0x10029000 0 0x000100>; 715 reg-names = "pmif", "spmimst"; 716 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 717 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 718 <&topckgen CLK_TOP_SPMI_M_MST>; 719 clock-names = "pmif_sys_ck", 720 "pmif_tmr_ck", 721 "spmimst_clk_mux"; 722 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 723 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 724 }; 725 726 scp: scp@10500000 { 727 compatible = "mediatek,mt8195-scp"; 728 reg = <0 0x10500000 0 0x100000>, 729 <0 0x10720000 0 0xe0000>, 730 <0 0x10700000 0 0x8000>; 731 reg-names = "sram", "cfg", "l1tcm"; 732 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 733 status = "disabled"; 734 }; 735 736 scp_adsp: clock-controller@10720000 { 737 compatible = "mediatek,mt8195-scp_adsp"; 738 reg = <0 0x10720000 0 0x1000>; 739 #clock-cells = <1>; 740 }; 741 742 adsp: dsp@10803000 { 743 compatible = "mediatek,mt8195-dsp"; 744 reg = <0 0x10803000 0 0x1000>, 745 <0 0x10840000 0 0x40000>; 746 reg-names = "cfg", "sram"; 747 clocks = <&topckgen CLK_TOP_ADSP>, 748 <&clk26m>, 749 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 750 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 751 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 752 <&topckgen CLK_TOP_AUDIO_H>; 753 clock-names = "adsp_sel", 754 "clk26m_ck", 755 "audio_local_bus", 756 "mainpll_d7_d2", 757 "scp_adsp_audiodsp", 758 "audio_h"; 759 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 760 mbox-names = "rx", "tx"; 761 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 762 status = "disabled"; 763 }; 764 765 adsp_mailbox0: mailbox@10816000 { 766 compatible = "mediatek,mt8195-adsp-mbox"; 767 #mbox-cells = <0>; 768 reg = <0 0x10816000 0 0x1000>; 769 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 770 }; 771 772 adsp_mailbox1: mailbox@10817000 { 773 compatible = "mediatek,mt8195-adsp-mbox"; 774 #mbox-cells = <0>; 775 reg = <0 0x10817000 0 0x1000>; 776 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 777 }; 778 779 afe: mt8195-afe-pcm@10890000 { 780 compatible = "mediatek,mt8195-audio"; 781 reg = <0 0x10890000 0 0x10000>; 782 mediatek,topckgen = <&topckgen>; 783 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 784 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 785 clocks = <&clk26m>, 786 <&apmixedsys CLK_APMIXED_APLL1>, 787 <&apmixedsys CLK_APMIXED_APLL2>, 788 <&topckgen CLK_TOP_APLL12_DIV0>, 789 <&topckgen CLK_TOP_APLL12_DIV1>, 790 <&topckgen CLK_TOP_APLL12_DIV2>, 791 <&topckgen CLK_TOP_APLL12_DIV3>, 792 <&topckgen CLK_TOP_APLL12_DIV9>, 793 <&topckgen CLK_TOP_A1SYS_HP>, 794 <&topckgen CLK_TOP_AUD_INTBUS>, 795 <&topckgen CLK_TOP_AUDIO_H>, 796 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 797 <&topckgen CLK_TOP_DPTX_MCK>, 798 <&topckgen CLK_TOP_I2SO1_MCK>, 799 <&topckgen CLK_TOP_I2SO2_MCK>, 800 <&topckgen CLK_TOP_I2SI1_MCK>, 801 <&topckgen CLK_TOP_I2SI2_MCK>, 802 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 803 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 804 clock-names = "clk26m", 805 "apll1_ck", 806 "apll2_ck", 807 "apll12_div0", 808 "apll12_div1", 809 "apll12_div2", 810 "apll12_div3", 811 "apll12_div9", 812 "a1sys_hp_sel", 813 "aud_intbus_sel", 814 "audio_h_sel", 815 "audio_local_bus_sel", 816 "dptx_m_sel", 817 "i2so1_m_sel", 818 "i2so2_m_sel", 819 "i2si1_m_sel", 820 "i2si2_m_sel", 821 "infra_ao_audio_26m_b", 822 "scp_adsp_audiodsp"; 823 status = "disabled"; 824 }; 825 826 uart0: serial@11001100 { 827 compatible = "mediatek,mt8195-uart", 828 "mediatek,mt6577-uart"; 829 reg = <0 0x11001100 0 0x100>; 830 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 831 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 832 clock-names = "baud", "bus"; 833 status = "disabled"; 834 }; 835 836 uart1: serial@11001200 { 837 compatible = "mediatek,mt8195-uart", 838 "mediatek,mt6577-uart"; 839 reg = <0 0x11001200 0 0x100>; 840 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 841 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 842 clock-names = "baud", "bus"; 843 status = "disabled"; 844 }; 845 846 uart2: serial@11001300 { 847 compatible = "mediatek,mt8195-uart", 848 "mediatek,mt6577-uart"; 849 reg = <0 0x11001300 0 0x100>; 850 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 851 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 852 clock-names = "baud", "bus"; 853 status = "disabled"; 854 }; 855 856 uart3: serial@11001400 { 857 compatible = "mediatek,mt8195-uart", 858 "mediatek,mt6577-uart"; 859 reg = <0 0x11001400 0 0x100>; 860 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 861 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 862 clock-names = "baud", "bus"; 863 status = "disabled"; 864 }; 865 866 uart4: serial@11001500 { 867 compatible = "mediatek,mt8195-uart", 868 "mediatek,mt6577-uart"; 869 reg = <0 0x11001500 0 0x100>; 870 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 871 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 872 clock-names = "baud", "bus"; 873 status = "disabled"; 874 }; 875 876 uart5: serial@11001600 { 877 compatible = "mediatek,mt8195-uart", 878 "mediatek,mt6577-uart"; 879 reg = <0 0x11001600 0 0x100>; 880 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 881 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 882 clock-names = "baud", "bus"; 883 status = "disabled"; 884 }; 885 886 auxadc: auxadc@11002000 { 887 compatible = "mediatek,mt8195-auxadc", 888 "mediatek,mt8173-auxadc"; 889 reg = <0 0x11002000 0 0x1000>; 890 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 891 clock-names = "main"; 892 #io-channel-cells = <1>; 893 status = "disabled"; 894 }; 895 896 pericfg_ao: syscon@11003000 { 897 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 898 reg = <0 0x11003000 0 0x1000>; 899 #clock-cells = <1>; 900 }; 901 902 spi0: spi@1100a000 { 903 compatible = "mediatek,mt8195-spi", 904 "mediatek,mt6765-spi"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 reg = <0 0x1100a000 0 0x1000>; 908 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 909 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 910 <&topckgen CLK_TOP_SPI>, 911 <&infracfg_ao CLK_INFRA_AO_SPI0>; 912 clock-names = "parent-clk", "sel-clk", "spi-clk"; 913 status = "disabled"; 914 }; 915 916 spi1: spi@11010000 { 917 compatible = "mediatek,mt8195-spi", 918 "mediatek,mt6765-spi"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 reg = <0 0x11010000 0 0x1000>; 922 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 923 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 924 <&topckgen CLK_TOP_SPI>, 925 <&infracfg_ao CLK_INFRA_AO_SPI1>; 926 clock-names = "parent-clk", "sel-clk", "spi-clk"; 927 status = "disabled"; 928 }; 929 930 spi2: spi@11012000 { 931 compatible = "mediatek,mt8195-spi", 932 "mediatek,mt6765-spi"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 reg = <0 0x11012000 0 0x1000>; 936 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 937 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 938 <&topckgen CLK_TOP_SPI>, 939 <&infracfg_ao CLK_INFRA_AO_SPI2>; 940 clock-names = "parent-clk", "sel-clk", "spi-clk"; 941 status = "disabled"; 942 }; 943 944 spi3: spi@11013000 { 945 compatible = "mediatek,mt8195-spi", 946 "mediatek,mt6765-spi"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 reg = <0 0x11013000 0 0x1000>; 950 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 951 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 952 <&topckgen CLK_TOP_SPI>, 953 <&infracfg_ao CLK_INFRA_AO_SPI3>; 954 clock-names = "parent-clk", "sel-clk", "spi-clk"; 955 status = "disabled"; 956 }; 957 958 spi4: spi@11018000 { 959 compatible = "mediatek,mt8195-spi", 960 "mediatek,mt6765-spi"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 reg = <0 0x11018000 0 0x1000>; 964 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 965 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 966 <&topckgen CLK_TOP_SPI>, 967 <&infracfg_ao CLK_INFRA_AO_SPI4>; 968 clock-names = "parent-clk", "sel-clk", "spi-clk"; 969 status = "disabled"; 970 }; 971 972 spi5: spi@11019000 { 973 compatible = "mediatek,mt8195-spi", 974 "mediatek,mt6765-spi"; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 reg = <0 0x11019000 0 0x1000>; 978 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 979 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 980 <&topckgen CLK_TOP_SPI>, 981 <&infracfg_ao CLK_INFRA_AO_SPI5>; 982 clock-names = "parent-clk", "sel-clk", "spi-clk"; 983 status = "disabled"; 984 }; 985 986 spis0: spi@1101d000 { 987 compatible = "mediatek,mt8195-spi-slave"; 988 reg = <0 0x1101d000 0 0x1000>; 989 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 990 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 991 clock-names = "spi"; 992 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 993 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 994 status = "disabled"; 995 }; 996 997 spis1: spi@1101e000 { 998 compatible = "mediatek,mt8195-spi-slave"; 999 reg = <0 0x1101e000 0 0x1000>; 1000 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1001 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1002 clock-names = "spi"; 1003 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1004 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1005 status = "disabled"; 1006 }; 1007 1008 xhci0: usb@11200000 { 1009 compatible = "mediatek,mt8195-xhci", 1010 "mediatek,mtk-xhci"; 1011 reg = <0 0x11200000 0 0x1000>, 1012 <0 0x11203e00 0 0x0100>; 1013 reg-names = "mac", "ippc"; 1014 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1015 phys = <&u2port0 PHY_TYPE_USB2>, 1016 <&u3port0 PHY_TYPE_USB3>; 1017 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1018 <&topckgen CLK_TOP_SSUSB_XHCI>; 1019 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1020 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1021 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1022 <&topckgen CLK_TOP_SSUSB_REF>, 1023 <&apmixedsys CLK_APMIXED_USB1PLL>, 1024 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1025 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 1026 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1027 wakeup-source; 1028 status = "disabled"; 1029 }; 1030 1031 mmc0: mmc@11230000 { 1032 compatible = "mediatek,mt8195-mmc", 1033 "mediatek,mt8183-mmc"; 1034 reg = <0 0x11230000 0 0x10000>, 1035 <0 0x11f50000 0 0x1000>; 1036 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1037 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1038 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1039 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1040 clock-names = "source", "hclk", "source_cg"; 1041 status = "disabled"; 1042 }; 1043 1044 mmc1: mmc@11240000 { 1045 compatible = "mediatek,mt8195-mmc", 1046 "mediatek,mt8183-mmc"; 1047 reg = <0 0x11240000 0 0x1000>, 1048 <0 0x11c70000 0 0x1000>; 1049 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1050 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1051 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1052 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1053 clock-names = "source", "hclk", "source_cg"; 1054 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1055 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1056 status = "disabled"; 1057 }; 1058 1059 mmc2: mmc@11250000 { 1060 compatible = "mediatek,mt8195-mmc", 1061 "mediatek,mt8183-mmc"; 1062 reg = <0 0x11250000 0 0x1000>, 1063 <0 0x11e60000 0 0x1000>; 1064 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1065 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1066 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1067 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1068 clock-names = "source", "hclk", "source_cg"; 1069 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1070 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1071 status = "disabled"; 1072 }; 1073 1074 xhci1: usb@11290000 { 1075 compatible = "mediatek,mt8195-xhci", 1076 "mediatek,mtk-xhci"; 1077 reg = <0 0x11290000 0 0x1000>, 1078 <0 0x11293e00 0 0x0100>; 1079 reg-names = "mac", "ippc"; 1080 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1081 phys = <&u2port1 PHY_TYPE_USB2>; 1082 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1083 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1084 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1085 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1086 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1087 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1088 <&apmixedsys CLK_APMIXED_USB1PLL>, 1089 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1090 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 1091 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1092 wakeup-source; 1093 status = "disabled"; 1094 }; 1095 1096 xhci2: usb@112a0000 { 1097 compatible = "mediatek,mt8195-xhci", 1098 "mediatek,mtk-xhci"; 1099 reg = <0 0x112a0000 0 0x1000>, 1100 <0 0x112a3e00 0 0x0100>; 1101 reg-names = "mac", "ippc"; 1102 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1103 phys = <&u2port2 PHY_TYPE_USB2>; 1104 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1105 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1106 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1107 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1108 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1109 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1110 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1111 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1112 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1113 wakeup-source; 1114 status = "disabled"; 1115 }; 1116 1117 xhci3: usb@112b0000 { 1118 compatible = "mediatek,mt8195-xhci", 1119 "mediatek,mtk-xhci"; 1120 reg = <0 0x112b0000 0 0x1000>, 1121 <0 0x112b3e00 0 0x0100>; 1122 reg-names = "mac", "ippc"; 1123 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1124 phys = <&u2port3 PHY_TYPE_USB2>; 1125 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1126 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1127 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1128 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1129 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1130 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1131 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1132 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1133 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1134 wakeup-source; 1135 status = "disabled"; 1136 }; 1137 1138 nor_flash: spi@1132c000 { 1139 compatible = "mediatek,mt8195-nor", 1140 "mediatek,mt8173-nor"; 1141 reg = <0 0x1132c000 0 0x1000>; 1142 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1143 clocks = <&topckgen CLK_TOP_SPINOR>, 1144 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1145 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1146 clock-names = "spi", "sf", "axi"; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 efuse: efuse@11c10000 { 1153 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1154 reg = <0 0x11c10000 0 0x1000>; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1158 reg = <0x184 0x1>; 1159 bits = <0 5>; 1160 }; 1161 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1162 reg = <0x184 0x2>; 1163 bits = <5 5>; 1164 }; 1165 u3_intr_p0: usb3-intr@185 { 1166 reg = <0x185 0x1>; 1167 bits = <2 6>; 1168 }; 1169 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1170 reg = <0x186 0x1>; 1171 bits = <0 5>; 1172 }; 1173 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1174 reg = <0x186 0x2>; 1175 bits = <5 5>; 1176 }; 1177 comb_intr_p1: usb3-intr@187 { 1178 reg = <0x187 0x1>; 1179 bits = <2 6>; 1180 }; 1181 u2_intr_p0: usb2-intr-p0@188,1 { 1182 reg = <0x188 0x1>; 1183 bits = <0 5>; 1184 }; 1185 u2_intr_p1: usb2-intr-p1@188,2 { 1186 reg = <0x188 0x2>; 1187 bits = <5 5>; 1188 }; 1189 u2_intr_p2: usb2-intr-p2@189,1 { 1190 reg = <0x189 0x1>; 1191 bits = <2 5>; 1192 }; 1193 u2_intr_p3: usb2-intr-p3@189,2 { 1194 reg = <0x189 0x2>; 1195 bits = <7 5>; 1196 }; 1197 }; 1198 1199 u3phy2: t-phy@11c40000 { 1200 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1201 #address-cells = <1>; 1202 #size-cells = <1>; 1203 ranges = <0 0 0x11c40000 0x700>; 1204 status = "disabled"; 1205 1206 u2port2: usb-phy@0 { 1207 reg = <0x0 0x700>; 1208 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1209 clock-names = "ref"; 1210 #phy-cells = <1>; 1211 }; 1212 }; 1213 1214 u3phy3: t-phy@11c50000 { 1215 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 ranges = <0 0 0x11c50000 0x700>; 1219 status = "disabled"; 1220 1221 u2port3: usb-phy@0 { 1222 reg = <0x0 0x700>; 1223 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1224 clock-names = "ref"; 1225 #phy-cells = <1>; 1226 }; 1227 }; 1228 1229 i2c5: i2c@11d00000 { 1230 compatible = "mediatek,mt8195-i2c", 1231 "mediatek,mt8192-i2c"; 1232 reg = <0 0x11d00000 0 0x1000>, 1233 <0 0x10220580 0 0x80>; 1234 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clock-div = <1>; 1236 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1237 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1238 clock-names = "main", "dma"; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 status = "disabled"; 1242 }; 1243 1244 i2c6: i2c@11d01000 { 1245 compatible = "mediatek,mt8195-i2c", 1246 "mediatek,mt8192-i2c"; 1247 reg = <0 0x11d01000 0 0x1000>, 1248 <0 0x10220600 0 0x80>; 1249 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1250 clock-div = <1>; 1251 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1252 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1253 clock-names = "main", "dma"; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 i2c7: i2c@11d02000 { 1260 compatible = "mediatek,mt8195-i2c", 1261 "mediatek,mt8192-i2c"; 1262 reg = <0 0x11d02000 0 0x1000>, 1263 <0 0x10220680 0 0x80>; 1264 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1265 clock-div = <1>; 1266 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1267 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1268 clock-names = "main", "dma"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 imp_iic_wrap_s: clock-controller@11d03000 { 1275 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1276 reg = <0 0x11d03000 0 0x1000>; 1277 #clock-cells = <1>; 1278 }; 1279 1280 i2c0: i2c@11e00000 { 1281 compatible = "mediatek,mt8195-i2c", 1282 "mediatek,mt8192-i2c"; 1283 reg = <0 0x11e00000 0 0x1000>, 1284 <0 0x10220080 0 0x80>; 1285 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1286 clock-div = <1>; 1287 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1288 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1289 clock-names = "main", "dma"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c1: i2c@11e01000 { 1296 compatible = "mediatek,mt8195-i2c", 1297 "mediatek,mt8192-i2c"; 1298 reg = <0 0x11e01000 0 0x1000>, 1299 <0 0x10220200 0 0x80>; 1300 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1301 clock-div = <1>; 1302 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1303 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1304 clock-names = "main", "dma"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 i2c2: i2c@11e02000 { 1311 compatible = "mediatek,mt8195-i2c", 1312 "mediatek,mt8192-i2c"; 1313 reg = <0 0x11e02000 0 0x1000>, 1314 <0 0x10220380 0 0x80>; 1315 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1316 clock-div = <1>; 1317 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1318 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1319 clock-names = "main", "dma"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2c3: i2c@11e03000 { 1326 compatible = "mediatek,mt8195-i2c", 1327 "mediatek,mt8192-i2c"; 1328 reg = <0 0x11e03000 0 0x1000>, 1329 <0 0x10220480 0 0x80>; 1330 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1331 clock-div = <1>; 1332 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1333 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1334 clock-names = "main", "dma"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c4: i2c@11e04000 { 1341 compatible = "mediatek,mt8195-i2c", 1342 "mediatek,mt8192-i2c"; 1343 reg = <0 0x11e04000 0 0x1000>, 1344 <0 0x10220500 0 0x80>; 1345 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1346 clock-div = <1>; 1347 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1348 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1349 clock-names = "main", "dma"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 status = "disabled"; 1353 }; 1354 1355 imp_iic_wrap_w: clock-controller@11e05000 { 1356 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1357 reg = <0 0x11e05000 0 0x1000>; 1358 #clock-cells = <1>; 1359 }; 1360 1361 u3phy1: t-phy@11e30000 { 1362 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1363 #address-cells = <1>; 1364 #size-cells = <1>; 1365 ranges = <0 0 0x11e30000 0xe00>; 1366 status = "disabled"; 1367 1368 u2port1: usb-phy@0 { 1369 reg = <0x0 0x700>; 1370 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1371 <&clk26m>; 1372 clock-names = "ref", "da_ref"; 1373 #phy-cells = <1>; 1374 }; 1375 1376 u3port1: usb-phy@700 { 1377 reg = <0x700 0x700>; 1378 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1379 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1380 clock-names = "ref", "da_ref"; 1381 nvmem-cells = <&comb_intr_p1>, 1382 <&comb_rx_imp_p1>, 1383 <&comb_tx_imp_p1>; 1384 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1385 #phy-cells = <1>; 1386 }; 1387 }; 1388 1389 u3phy0: t-phy@11e40000 { 1390 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1391 #address-cells = <1>; 1392 #size-cells = <1>; 1393 ranges = <0 0 0x11e40000 0xe00>; 1394 status = "disabled"; 1395 1396 u2port0: usb-phy@0 { 1397 reg = <0x0 0x700>; 1398 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1399 <&clk26m>; 1400 clock-names = "ref", "da_ref"; 1401 #phy-cells = <1>; 1402 }; 1403 1404 u3port0: usb-phy@700 { 1405 reg = <0x700 0x700>; 1406 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1407 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1408 clock-names = "ref", "da_ref"; 1409 nvmem-cells = <&u3_intr_p0>, 1410 <&u3_rx_imp_p0>, 1411 <&u3_tx_imp_p0>; 1412 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1413 #phy-cells = <1>; 1414 }; 1415 }; 1416 1417 ufsphy: ufs-phy@11fa0000 { 1418 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1419 reg = <0 0x11fa0000 0 0xc000>; 1420 clocks = <&clk26m>, <&clk26m>; 1421 clock-names = "unipro", "mp"; 1422 #phy-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 mfgcfg: clock-controller@13fbf000 { 1427 compatible = "mediatek,mt8195-mfgcfg"; 1428 reg = <0 0x13fbf000 0 0x1000>; 1429 #clock-cells = <1>; 1430 }; 1431 1432 vppsys0: clock-controller@14000000 { 1433 compatible = "mediatek,mt8195-vppsys0"; 1434 reg = <0 0x14000000 0 0x1000>; 1435 #clock-cells = <1>; 1436 }; 1437 1438 wpesys: clock-controller@14e00000 { 1439 compatible = "mediatek,mt8195-wpesys"; 1440 reg = <0 0x14e00000 0 0x1000>; 1441 #clock-cells = <1>; 1442 }; 1443 1444 wpesys_vpp0: clock-controller@14e02000 { 1445 compatible = "mediatek,mt8195-wpesys_vpp0"; 1446 reg = <0 0x14e02000 0 0x1000>; 1447 #clock-cells = <1>; 1448 }; 1449 1450 wpesys_vpp1: clock-controller@14e03000 { 1451 compatible = "mediatek,mt8195-wpesys_vpp1"; 1452 reg = <0 0x14e03000 0 0x1000>; 1453 #clock-cells = <1>; 1454 }; 1455 1456 vppsys1: clock-controller@14f00000 { 1457 compatible = "mediatek,mt8195-vppsys1"; 1458 reg = <0 0x14f00000 0 0x1000>; 1459 #clock-cells = <1>; 1460 }; 1461 1462 imgsys: clock-controller@15000000 { 1463 compatible = "mediatek,mt8195-imgsys"; 1464 reg = <0 0x15000000 0 0x1000>; 1465 #clock-cells = <1>; 1466 }; 1467 1468 imgsys1_dip_top: clock-controller@15110000 { 1469 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1470 reg = <0 0x15110000 0 0x1000>; 1471 #clock-cells = <1>; 1472 }; 1473 1474 imgsys1_dip_nr: clock-controller@15130000 { 1475 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1476 reg = <0 0x15130000 0 0x1000>; 1477 #clock-cells = <1>; 1478 }; 1479 1480 imgsys1_wpe: clock-controller@15220000 { 1481 compatible = "mediatek,mt8195-imgsys1_wpe"; 1482 reg = <0 0x15220000 0 0x1000>; 1483 #clock-cells = <1>; 1484 }; 1485 1486 ipesys: clock-controller@15330000 { 1487 compatible = "mediatek,mt8195-ipesys"; 1488 reg = <0 0x15330000 0 0x1000>; 1489 #clock-cells = <1>; 1490 }; 1491 1492 camsys: clock-controller@16000000 { 1493 compatible = "mediatek,mt8195-camsys"; 1494 reg = <0 0x16000000 0 0x1000>; 1495 #clock-cells = <1>; 1496 }; 1497 1498 camsys_rawa: clock-controller@1604f000 { 1499 compatible = "mediatek,mt8195-camsys_rawa"; 1500 reg = <0 0x1604f000 0 0x1000>; 1501 #clock-cells = <1>; 1502 }; 1503 1504 camsys_yuva: clock-controller@1606f000 { 1505 compatible = "mediatek,mt8195-camsys_yuva"; 1506 reg = <0 0x1606f000 0 0x1000>; 1507 #clock-cells = <1>; 1508 }; 1509 1510 camsys_rawb: clock-controller@1608f000 { 1511 compatible = "mediatek,mt8195-camsys_rawb"; 1512 reg = <0 0x1608f000 0 0x1000>; 1513 #clock-cells = <1>; 1514 }; 1515 1516 camsys_yuvb: clock-controller@160af000 { 1517 compatible = "mediatek,mt8195-camsys_yuvb"; 1518 reg = <0 0x160af000 0 0x1000>; 1519 #clock-cells = <1>; 1520 }; 1521 1522 camsys_mraw: clock-controller@16140000 { 1523 compatible = "mediatek,mt8195-camsys_mraw"; 1524 reg = <0 0x16140000 0 0x1000>; 1525 #clock-cells = <1>; 1526 }; 1527 1528 ccusys: clock-controller@17200000 { 1529 compatible = "mediatek,mt8195-ccusys"; 1530 reg = <0 0x17200000 0 0x1000>; 1531 #clock-cells = <1>; 1532 }; 1533 1534 vdecsys_soc: clock-controller@1800f000 { 1535 compatible = "mediatek,mt8195-vdecsys_soc"; 1536 reg = <0 0x1800f000 0 0x1000>; 1537 #clock-cells = <1>; 1538 }; 1539 1540 vdecsys: clock-controller@1802f000 { 1541 compatible = "mediatek,mt8195-vdecsys"; 1542 reg = <0 0x1802f000 0 0x1000>; 1543 #clock-cells = <1>; 1544 }; 1545 1546 vdecsys_core1: clock-controller@1803f000 { 1547 compatible = "mediatek,mt8195-vdecsys_core1"; 1548 reg = <0 0x1803f000 0 0x1000>; 1549 #clock-cells = <1>; 1550 }; 1551 1552 apusys_pll: clock-controller@190f3000 { 1553 compatible = "mediatek,mt8195-apusys_pll"; 1554 reg = <0 0x190f3000 0 0x1000>; 1555 #clock-cells = <1>; 1556 }; 1557 1558 vencsys: clock-controller@1a000000 { 1559 compatible = "mediatek,mt8195-vencsys"; 1560 reg = <0 0x1a000000 0 0x1000>; 1561 #clock-cells = <1>; 1562 }; 1563 1564 vencsys_core1: clock-controller@1b000000 { 1565 compatible = "mediatek,mt8195-vencsys_core1"; 1566 reg = <0 0x1b000000 0 0x1000>; 1567 #clock-cells = <1>; 1568 }; 1569 1570 vdosys0: syscon@1c01a000 { 1571 compatible = "mediatek,mt8195-mmsys", "syscon"; 1572 reg = <0 0x1c01a000 0 0x1000>; 1573 #clock-cells = <1>; 1574 }; 1575 1576 vdosys1: syscon@1c100000 { 1577 compatible = "mediatek,mt8195-mmsys", "syscon"; 1578 reg = <0 0x1c100000 0 0x1000>; 1579 #clock-cells = <1>; 1580 }; 1581 }; 1582}; 1583