1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/power/mt8195-power.h> 14 15/ { 16 compatible = "mediatek,mt8195"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x000>; 29 enable-method = "psci"; 30 performance-domains = <&performance 0>; 31 clock-frequency = <1701000000>; 32 capacity-dmips-mhz = <578>; 33 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 }; 37 38 cpu1: cpu@100 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x100>; 42 enable-method = "psci"; 43 performance-domains = <&performance 0>; 44 clock-frequency = <1701000000>; 45 capacity-dmips-mhz = <578>; 46 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 47 next-level-cache = <&l2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 cpu2: cpu@200 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x200>; 55 enable-method = "psci"; 56 performance-domains = <&performance 0>; 57 clock-frequency = <1701000000>; 58 capacity-dmips-mhz = <578>; 59 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 60 next-level-cache = <&l2_0>; 61 #cooling-cells = <2>; 62 }; 63 64 cpu3: cpu@300 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x300>; 68 enable-method = "psci"; 69 performance-domains = <&performance 0>; 70 clock-frequency = <1701000000>; 71 capacity-dmips-mhz = <578>; 72 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 73 next-level-cache = <&l2_0>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu4: cpu@400 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a78"; 80 reg = <0x400>; 81 enable-method = "psci"; 82 performance-domains = <&performance 1>; 83 clock-frequency = <2171000000>; 84 capacity-dmips-mhz = <1024>; 85 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 86 next-level-cache = <&l2_1>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a78"; 93 reg = <0x500>; 94 enable-method = "psci"; 95 performance-domains = <&performance 1>; 96 clock-frequency = <2171000000>; 97 capacity-dmips-mhz = <1024>; 98 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 99 next-level-cache = <&l2_1>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu6: cpu@600 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a78"; 106 reg = <0x600>; 107 enable-method = "psci"; 108 performance-domains = <&performance 1>; 109 clock-frequency = <2171000000>; 110 capacity-dmips-mhz = <1024>; 111 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu7: cpu@700 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a78"; 119 reg = <0x700>; 120 enable-method = "psci"; 121 performance-domains = <&performance 1>; 122 clock-frequency = <2171000000>; 123 capacity-dmips-mhz = <1024>; 124 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 125 next-level-cache = <&l2_1>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu-map { 130 cluster0 { 131 core0 { 132 cpu = <&cpu0>; 133 }; 134 135 core1 { 136 cpu = <&cpu1>; 137 }; 138 139 core2 { 140 cpu = <&cpu2>; 141 }; 142 143 core3 { 144 cpu = <&cpu3>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu4>; 151 }; 152 153 core1 { 154 cpu = <&cpu5>; 155 }; 156 157 core2 { 158 cpu = <&cpu6>; 159 }; 160 161 core3 { 162 cpu = <&cpu7>; 163 }; 164 }; 165 }; 166 167 idle-states { 168 entry-method = "psci"; 169 170 cpu_off_l: cpu-off-l { 171 compatible = "arm,idle-state"; 172 arm,psci-suspend-param = <0x00010001>; 173 local-timer-stop; 174 entry-latency-us = <50>; 175 exit-latency-us = <95>; 176 min-residency-us = <580>; 177 }; 178 179 cpu_off_b: cpu-off-b { 180 compatible = "arm,idle-state"; 181 arm,psci-suspend-param = <0x00010001>; 182 local-timer-stop; 183 entry-latency-us = <45>; 184 exit-latency-us = <140>; 185 min-residency-us = <740>; 186 }; 187 188 cluster_off_l: cluster-off-l { 189 compatible = "arm,idle-state"; 190 arm,psci-suspend-param = <0x01010002>; 191 local-timer-stop; 192 entry-latency-us = <55>; 193 exit-latency-us = <155>; 194 min-residency-us = <840>; 195 }; 196 197 cluster_off_b: cluster-off-b { 198 compatible = "arm,idle-state"; 199 arm,psci-suspend-param = <0x01010002>; 200 local-timer-stop; 201 entry-latency-us = <50>; 202 exit-latency-us = <200>; 203 min-residency-us = <1000>; 204 }; 205 }; 206 207 l2_0: l2-cache0 { 208 compatible = "cache"; 209 next-level-cache = <&l3_0>; 210 }; 211 212 l2_1: l2-cache1 { 213 compatible = "cache"; 214 next-level-cache = <&l3_0>; 215 }; 216 217 l3_0: l3-cache { 218 compatible = "cache"; 219 }; 220 }; 221 222 dsu-pmu { 223 compatible = "arm,dsu-pmu"; 224 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 225 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 226 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 227 }; 228 229 dmic_codec: dmic-codec { 230 compatible = "dmic-codec"; 231 num-channels = <2>; 232 wakeup-delay-ms = <50>; 233 }; 234 235 sound: mt8195-sound { 236 mediatek,platform = <&afe>; 237 status = "disabled"; 238 }; 239 240 clk26m: oscillator-26m { 241 compatible = "fixed-clock"; 242 #clock-cells = <0>; 243 clock-frequency = <26000000>; 244 clock-output-names = "clk26m"; 245 }; 246 247 clk32k: oscillator-32k { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <32768>; 251 clock-output-names = "clk32k"; 252 }; 253 254 performance: performance-controller@11bc10 { 255 compatible = "mediatek,cpufreq-hw"; 256 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 257 #performance-domain-cells = <1>; 258 }; 259 260 pmu-a55 { 261 compatible = "arm,cortex-a55-pmu"; 262 interrupt-parent = <&gic>; 263 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 264 }; 265 266 pmu-a78 { 267 compatible = "arm,cortex-a78-pmu"; 268 interrupt-parent = <&gic>; 269 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 270 }; 271 272 psci { 273 compatible = "arm,psci-1.0"; 274 method = "smc"; 275 }; 276 277 timer: timer { 278 compatible = "arm,armv8-timer"; 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 281 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 282 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 283 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 284 }; 285 286 soc { 287 #address-cells = <2>; 288 #size-cells = <2>; 289 compatible = "simple-bus"; 290 ranges; 291 292 gic: interrupt-controller@c000000 { 293 compatible = "arm,gic-v3"; 294 #interrupt-cells = <4>; 295 #redistributor-regions = <1>; 296 interrupt-parent = <&gic>; 297 interrupt-controller; 298 reg = <0 0x0c000000 0 0x40000>, 299 <0 0x0c040000 0 0x200000>; 300 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 301 302 ppi-partitions { 303 ppi_cluster0: interrupt-partition-0 { 304 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 305 }; 306 307 ppi_cluster1: interrupt-partition-1 { 308 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 309 }; 310 }; 311 }; 312 313 topckgen: syscon@10000000 { 314 compatible = "mediatek,mt8195-topckgen", "syscon"; 315 reg = <0 0x10000000 0 0x1000>; 316 #clock-cells = <1>; 317 }; 318 319 infracfg_ao: syscon@10001000 { 320 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 321 reg = <0 0x10001000 0 0x1000>; 322 #clock-cells = <1>; 323 #reset-cells = <1>; 324 }; 325 326 pericfg: syscon@10003000 { 327 compatible = "mediatek,mt8195-pericfg", "syscon"; 328 reg = <0 0x10003000 0 0x1000>; 329 #clock-cells = <1>; 330 }; 331 332 pio: pinctrl@10005000 { 333 compatible = "mediatek,mt8195-pinctrl"; 334 reg = <0 0x10005000 0 0x1000>, 335 <0 0x11d10000 0 0x1000>, 336 <0 0x11d30000 0 0x1000>, 337 <0 0x11d40000 0 0x1000>, 338 <0 0x11e20000 0 0x1000>, 339 <0 0x11eb0000 0 0x1000>, 340 <0 0x11f40000 0 0x1000>, 341 <0 0x1000b000 0 0x1000>; 342 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 343 "iocfg_br", "iocfg_lm", "iocfg_rb", 344 "iocfg_tl", "eint"; 345 gpio-controller; 346 #gpio-cells = <2>; 347 gpio-ranges = <&pio 0 0 144>; 348 interrupt-controller; 349 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 350 #interrupt-cells = <2>; 351 }; 352 353 scpsys: syscon@10006000 { 354 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 355 reg = <0 0x10006000 0 0x1000>; 356 357 /* System Power Manager */ 358 spm: power-controller { 359 compatible = "mediatek,mt8195-power-controller"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 #power-domain-cells = <1>; 363 364 /* power domain of the SoC */ 365 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 366 reg = <MT8195_POWER_DOMAIN_MFG0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #power-domain-cells = <1>; 370 371 power-domain@MT8195_POWER_DOMAIN_MFG1 { 372 reg = <MT8195_POWER_DOMAIN_MFG1>; 373 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 374 clock-names = "mfg"; 375 mediatek,infracfg = <&infracfg_ao>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 #power-domain-cells = <1>; 379 380 power-domain@MT8195_POWER_DOMAIN_MFG2 { 381 reg = <MT8195_POWER_DOMAIN_MFG2>; 382 #power-domain-cells = <0>; 383 }; 384 385 power-domain@MT8195_POWER_DOMAIN_MFG3 { 386 reg = <MT8195_POWER_DOMAIN_MFG3>; 387 #power-domain-cells = <0>; 388 }; 389 390 power-domain@MT8195_POWER_DOMAIN_MFG4 { 391 reg = <MT8195_POWER_DOMAIN_MFG4>; 392 #power-domain-cells = <0>; 393 }; 394 395 power-domain@MT8195_POWER_DOMAIN_MFG5 { 396 reg = <MT8195_POWER_DOMAIN_MFG5>; 397 #power-domain-cells = <0>; 398 }; 399 400 power-domain@MT8195_POWER_DOMAIN_MFG6 { 401 reg = <MT8195_POWER_DOMAIN_MFG6>; 402 #power-domain-cells = <0>; 403 }; 404 }; 405 }; 406 407 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 408 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 409 clocks = <&topckgen CLK_TOP_VPP>, 410 <&topckgen CLK_TOP_CAM>, 411 <&topckgen CLK_TOP_CCU>, 412 <&topckgen CLK_TOP_IMG>, 413 <&topckgen CLK_TOP_VENC>, 414 <&topckgen CLK_TOP_VDEC>, 415 <&topckgen CLK_TOP_WPE_VPP>, 416 <&topckgen CLK_TOP_CFG_VPP0>, 417 <&vppsys0 CLK_VPP0_SMI_COMMON>, 418 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 419 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 420 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 421 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 422 <&vppsys0 CLK_VPP0_GALS_INFRA>, 423 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 424 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 425 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 426 <&vppsys0 CLK_VPP0_SMI_REORDER>, 427 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 428 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 429 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 430 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 431 <&vppsys0 CLK_VPP0_SMI_RSI>, 432 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 433 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 434 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 435 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 436 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 437 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 438 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 439 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 440 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 441 "vppsys0-12", "vppsys0-13", "vppsys0-14", 442 "vppsys0-15", "vppsys0-16", "vppsys0-17", 443 "vppsys0-18"; 444 mediatek,infracfg = <&infracfg_ao>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 #power-domain-cells = <1>; 448 449 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 450 reg = <MT8195_POWER_DOMAIN_VDEC1>; 451 clocks = <&vdecsys CLK_VDEC_LARB1>; 452 clock-names = "vdec1-0"; 453 mediatek,infracfg = <&infracfg_ao>; 454 #power-domain-cells = <0>; 455 }; 456 457 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 458 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 459 mediatek,infracfg = <&infracfg_ao>; 460 #power-domain-cells = <0>; 461 }; 462 463 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 464 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 465 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 466 <&vdosys0 CLK_VDO0_SMI_GALS>, 467 <&vdosys0 CLK_VDO0_SMI_COMMON>, 468 <&vdosys0 CLK_VDO0_SMI_EMI>, 469 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 470 <&vdosys0 CLK_VDO0_SMI_LARB>, 471 <&vdosys0 CLK_VDO0_SMI_RSI>; 472 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 473 "vdosys0-2", "vdosys0-3", 474 "vdosys0-4", "vdosys0-5"; 475 mediatek,infracfg = <&infracfg_ao>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 #power-domain-cells = <1>; 479 480 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 481 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 482 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 483 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 484 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 485 clock-names = "vppsys1", "vppsys1-0", 486 "vppsys1-1"; 487 mediatek,infracfg = <&infracfg_ao>; 488 #power-domain-cells = <0>; 489 }; 490 491 power-domain@MT8195_POWER_DOMAIN_WPESYS { 492 reg = <MT8195_POWER_DOMAIN_WPESYS>; 493 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 494 <&wpesys CLK_WPE_SMI_LARB8>, 495 <&wpesys CLK_WPE_SMI_LARB7_P>, 496 <&wpesys CLK_WPE_SMI_LARB8_P>; 497 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 498 "wepsys-3"; 499 mediatek,infracfg = <&infracfg_ao>; 500 #power-domain-cells = <0>; 501 }; 502 503 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 504 reg = <MT8195_POWER_DOMAIN_VDEC0>; 505 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 506 clock-names = "vdec0-0"; 507 mediatek,infracfg = <&infracfg_ao>; 508 #power-domain-cells = <0>; 509 }; 510 511 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 512 reg = <MT8195_POWER_DOMAIN_VDEC2>; 513 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 514 clock-names = "vdec2-0"; 515 mediatek,infracfg = <&infracfg_ao>; 516 #power-domain-cells = <0>; 517 }; 518 519 power-domain@MT8195_POWER_DOMAIN_VENC { 520 reg = <MT8195_POWER_DOMAIN_VENC>; 521 mediatek,infracfg = <&infracfg_ao>; 522 #power-domain-cells = <0>; 523 }; 524 525 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 526 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 527 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 528 <&vdosys1 CLK_VDO1_SMI_LARB2>, 529 <&vdosys1 CLK_VDO1_SMI_LARB3>, 530 <&vdosys1 CLK_VDO1_GALS>; 531 clock-names = "vdosys1", "vdosys1-0", 532 "vdosys1-1", "vdosys1-2"; 533 mediatek,infracfg = <&infracfg_ao>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 #power-domain-cells = <1>; 537 538 power-domain@MT8195_POWER_DOMAIN_DP_TX { 539 reg = <MT8195_POWER_DOMAIN_DP_TX>; 540 mediatek,infracfg = <&infracfg_ao>; 541 #power-domain-cells = <0>; 542 }; 543 544 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 545 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 546 mediatek,infracfg = <&infracfg_ao>; 547 #power-domain-cells = <0>; 548 }; 549 550 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 551 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 552 clocks = <&topckgen CLK_TOP_HDMI_APB>; 553 clock-names = "hdmi_tx"; 554 #power-domain-cells = <0>; 555 }; 556 }; 557 558 power-domain@MT8195_POWER_DOMAIN_IMG { 559 reg = <MT8195_POWER_DOMAIN_IMG>; 560 clocks = <&imgsys CLK_IMG_LARB9>, 561 <&imgsys CLK_IMG_GALS>; 562 clock-names = "img-0", "img-1"; 563 mediatek,infracfg = <&infracfg_ao>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 #power-domain-cells = <1>; 567 568 power-domain@MT8195_POWER_DOMAIN_DIP { 569 reg = <MT8195_POWER_DOMAIN_DIP>; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@MT8195_POWER_DOMAIN_IPE { 574 reg = <MT8195_POWER_DOMAIN_IPE>; 575 clocks = <&topckgen CLK_TOP_IPE>, 576 <&imgsys CLK_IMG_IPE>, 577 <&ipesys CLK_IPE_SMI_LARB12>; 578 clock-names = "ipe", "ipe-0", "ipe-1"; 579 mediatek,infracfg = <&infracfg_ao>; 580 #power-domain-cells = <0>; 581 }; 582 }; 583 584 power-domain@MT8195_POWER_DOMAIN_CAM { 585 reg = <MT8195_POWER_DOMAIN_CAM>; 586 clocks = <&camsys CLK_CAM_LARB13>, 587 <&camsys CLK_CAM_LARB14>, 588 <&camsys CLK_CAM_CAM2MM0_GALS>, 589 <&camsys CLK_CAM_CAM2MM1_GALS>, 590 <&camsys CLK_CAM_CAM2SYS_GALS>; 591 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 592 "cam-4"; 593 mediatek,infracfg = <&infracfg_ao>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 #power-domain-cells = <1>; 597 598 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 599 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 600 #power-domain-cells = <0>; 601 }; 602 603 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 604 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 605 #power-domain-cells = <0>; 606 }; 607 608 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 609 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 610 #power-domain-cells = <0>; 611 }; 612 }; 613 }; 614 }; 615 616 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 617 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 618 mediatek,infracfg = <&infracfg_ao>; 619 #power-domain-cells = <0>; 620 }; 621 622 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 623 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 629 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 630 #power-domain-cells = <0>; 631 }; 632 633 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 634 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 635 #power-domain-cells = <0>; 636 }; 637 638 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 639 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 640 clocks = <&topckgen CLK_TOP_SENINF>, 641 <&topckgen CLK_TOP_SENINF2>; 642 clock-names = "csi_rx_top", "csi_rx_top1"; 643 #power-domain-cells = <0>; 644 }; 645 646 power-domain@MT8195_POWER_DOMAIN_ETHER { 647 reg = <MT8195_POWER_DOMAIN_ETHER>; 648 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 649 clock-names = "ether"; 650 #power-domain-cells = <0>; 651 }; 652 653 power-domain@MT8195_POWER_DOMAIN_ADSP { 654 reg = <MT8195_POWER_DOMAIN_ADSP>; 655 clocks = <&topckgen CLK_TOP_ADSP>, 656 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 657 clock-names = "adsp", "adsp1"; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 mediatek,infracfg = <&infracfg_ao>; 661 #power-domain-cells = <1>; 662 663 power-domain@MT8195_POWER_DOMAIN_AUDIO { 664 reg = <MT8195_POWER_DOMAIN_AUDIO>; 665 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 666 <&topckgen CLK_TOP_AUD_INTBUS>, 667 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 668 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 669 clock-names = "audio", "audio1", "audio2", 670 "audio3"; 671 mediatek,infracfg = <&infracfg_ao>; 672 #power-domain-cells = <0>; 673 }; 674 }; 675 }; 676 }; 677 678 watchdog: watchdog@10007000 { 679 compatible = "mediatek,mt8195-wdt", 680 "mediatek,mt6589-wdt"; 681 mediatek,disable-extrst; 682 reg = <0 0x10007000 0 0x100>; 683 #reset-cells = <1>; 684 }; 685 686 apmixedsys: syscon@1000c000 { 687 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 688 reg = <0 0x1000c000 0 0x1000>; 689 #clock-cells = <1>; 690 }; 691 692 systimer: timer@10017000 { 693 compatible = "mediatek,mt8195-timer", 694 "mediatek,mt6765-timer"; 695 reg = <0 0x10017000 0 0x1000>; 696 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 697 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 698 }; 699 700 pwrap: pwrap@10024000 { 701 compatible = "mediatek,mt8195-pwrap", "syscon"; 702 reg = <0 0x10024000 0 0x1000>; 703 reg-names = "pwrap"; 704 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 705 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 706 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 707 clock-names = "spi", "wrap"; 708 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 709 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 710 }; 711 712 spmi: spmi@10027000 { 713 compatible = "mediatek,mt8195-spmi"; 714 reg = <0 0x10027000 0 0x000e00>, 715 <0 0x10029000 0 0x000100>; 716 reg-names = "pmif", "spmimst"; 717 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 718 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 719 <&topckgen CLK_TOP_SPMI_M_MST>; 720 clock-names = "pmif_sys_ck", 721 "pmif_tmr_ck", 722 "spmimst_clk_mux"; 723 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 724 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 725 }; 726 727 scp: scp@10500000 { 728 compatible = "mediatek,mt8195-scp"; 729 reg = <0 0x10500000 0 0x100000>, 730 <0 0x10720000 0 0xe0000>, 731 <0 0x10700000 0 0x8000>; 732 reg-names = "sram", "cfg", "l1tcm"; 733 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 734 status = "disabled"; 735 }; 736 737 scp_adsp: clock-controller@10720000 { 738 compatible = "mediatek,mt8195-scp_adsp"; 739 reg = <0 0x10720000 0 0x1000>; 740 #clock-cells = <1>; 741 }; 742 743 adsp: dsp@10803000 { 744 compatible = "mediatek,mt8195-dsp"; 745 reg = <0 0x10803000 0 0x1000>, 746 <0 0x10840000 0 0x40000>; 747 reg-names = "cfg", "sram"; 748 clocks = <&topckgen CLK_TOP_ADSP>, 749 <&clk26m>, 750 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 751 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 752 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 753 <&topckgen CLK_TOP_AUDIO_H>; 754 clock-names = "adsp_sel", 755 "clk26m_ck", 756 "audio_local_bus", 757 "mainpll_d7_d2", 758 "scp_adsp_audiodsp", 759 "audio_h"; 760 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 761 mbox-names = "rx", "tx"; 762 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 763 status = "disabled"; 764 }; 765 766 adsp_mailbox0: mailbox@10816000 { 767 compatible = "mediatek,mt8195-adsp-mbox"; 768 #mbox-cells = <0>; 769 reg = <0 0x10816000 0 0x1000>; 770 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 771 }; 772 773 adsp_mailbox1: mailbox@10817000 { 774 compatible = "mediatek,mt8195-adsp-mbox"; 775 #mbox-cells = <0>; 776 reg = <0 0x10817000 0 0x1000>; 777 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 778 }; 779 780 afe: mt8195-afe-pcm@10890000 { 781 compatible = "mediatek,mt8195-audio"; 782 reg = <0 0x10890000 0 0x10000>; 783 mediatek,topckgen = <&topckgen>; 784 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 785 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 786 resets = <&watchdog 14>; 787 reset-names = "audiosys"; 788 clocks = <&clk26m>, 789 <&apmixedsys CLK_APMIXED_APLL1>, 790 <&apmixedsys CLK_APMIXED_APLL2>, 791 <&topckgen CLK_TOP_APLL12_DIV0>, 792 <&topckgen CLK_TOP_APLL12_DIV1>, 793 <&topckgen CLK_TOP_APLL12_DIV2>, 794 <&topckgen CLK_TOP_APLL12_DIV3>, 795 <&topckgen CLK_TOP_APLL12_DIV9>, 796 <&topckgen CLK_TOP_A1SYS_HP>, 797 <&topckgen CLK_TOP_AUD_INTBUS>, 798 <&topckgen CLK_TOP_AUDIO_H>, 799 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 800 <&topckgen CLK_TOP_DPTX_MCK>, 801 <&topckgen CLK_TOP_I2SO1_MCK>, 802 <&topckgen CLK_TOP_I2SO2_MCK>, 803 <&topckgen CLK_TOP_I2SI1_MCK>, 804 <&topckgen CLK_TOP_I2SI2_MCK>, 805 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 806 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 807 clock-names = "clk26m", 808 "apll1_ck", 809 "apll2_ck", 810 "apll12_div0", 811 "apll12_div1", 812 "apll12_div2", 813 "apll12_div3", 814 "apll12_div9", 815 "a1sys_hp_sel", 816 "aud_intbus_sel", 817 "audio_h_sel", 818 "audio_local_bus_sel", 819 "dptx_m_sel", 820 "i2so1_m_sel", 821 "i2so2_m_sel", 822 "i2si1_m_sel", 823 "i2si2_m_sel", 824 "infra_ao_audio_26m_b", 825 "scp_adsp_audiodsp"; 826 status = "disabled"; 827 }; 828 829 uart0: serial@11001100 { 830 compatible = "mediatek,mt8195-uart", 831 "mediatek,mt6577-uart"; 832 reg = <0 0x11001100 0 0x100>; 833 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 834 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 835 clock-names = "baud", "bus"; 836 status = "disabled"; 837 }; 838 839 uart1: serial@11001200 { 840 compatible = "mediatek,mt8195-uart", 841 "mediatek,mt6577-uart"; 842 reg = <0 0x11001200 0 0x100>; 843 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 844 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 845 clock-names = "baud", "bus"; 846 status = "disabled"; 847 }; 848 849 uart2: serial@11001300 { 850 compatible = "mediatek,mt8195-uart", 851 "mediatek,mt6577-uart"; 852 reg = <0 0x11001300 0 0x100>; 853 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 854 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 855 clock-names = "baud", "bus"; 856 status = "disabled"; 857 }; 858 859 uart3: serial@11001400 { 860 compatible = "mediatek,mt8195-uart", 861 "mediatek,mt6577-uart"; 862 reg = <0 0x11001400 0 0x100>; 863 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 864 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 865 clock-names = "baud", "bus"; 866 status = "disabled"; 867 }; 868 869 uart4: serial@11001500 { 870 compatible = "mediatek,mt8195-uart", 871 "mediatek,mt6577-uart"; 872 reg = <0 0x11001500 0 0x100>; 873 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 874 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 875 clock-names = "baud", "bus"; 876 status = "disabled"; 877 }; 878 879 uart5: serial@11001600 { 880 compatible = "mediatek,mt8195-uart", 881 "mediatek,mt6577-uart"; 882 reg = <0 0x11001600 0 0x100>; 883 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 884 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 885 clock-names = "baud", "bus"; 886 status = "disabled"; 887 }; 888 889 auxadc: auxadc@11002000 { 890 compatible = "mediatek,mt8195-auxadc", 891 "mediatek,mt8173-auxadc"; 892 reg = <0 0x11002000 0 0x1000>; 893 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 894 clock-names = "main"; 895 #io-channel-cells = <1>; 896 status = "disabled"; 897 }; 898 899 pericfg_ao: syscon@11003000 { 900 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 901 reg = <0 0x11003000 0 0x1000>; 902 #clock-cells = <1>; 903 }; 904 905 spi0: spi@1100a000 { 906 compatible = "mediatek,mt8195-spi", 907 "mediatek,mt6765-spi"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 reg = <0 0x1100a000 0 0x1000>; 911 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 912 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 913 <&topckgen CLK_TOP_SPI>, 914 <&infracfg_ao CLK_INFRA_AO_SPI0>; 915 clock-names = "parent-clk", "sel-clk", "spi-clk"; 916 status = "disabled"; 917 }; 918 919 spi1: spi@11010000 { 920 compatible = "mediatek,mt8195-spi", 921 "mediatek,mt6765-spi"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 reg = <0 0x11010000 0 0x1000>; 925 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 926 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 927 <&topckgen CLK_TOP_SPI>, 928 <&infracfg_ao CLK_INFRA_AO_SPI1>; 929 clock-names = "parent-clk", "sel-clk", "spi-clk"; 930 status = "disabled"; 931 }; 932 933 spi2: spi@11012000 { 934 compatible = "mediatek,mt8195-spi", 935 "mediatek,mt6765-spi"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 reg = <0 0x11012000 0 0x1000>; 939 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 940 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 941 <&topckgen CLK_TOP_SPI>, 942 <&infracfg_ao CLK_INFRA_AO_SPI2>; 943 clock-names = "parent-clk", "sel-clk", "spi-clk"; 944 status = "disabled"; 945 }; 946 947 spi3: spi@11013000 { 948 compatible = "mediatek,mt8195-spi", 949 "mediatek,mt6765-spi"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 reg = <0 0x11013000 0 0x1000>; 953 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 954 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 955 <&topckgen CLK_TOP_SPI>, 956 <&infracfg_ao CLK_INFRA_AO_SPI3>; 957 clock-names = "parent-clk", "sel-clk", "spi-clk"; 958 status = "disabled"; 959 }; 960 961 spi4: spi@11018000 { 962 compatible = "mediatek,mt8195-spi", 963 "mediatek,mt6765-spi"; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 reg = <0 0x11018000 0 0x1000>; 967 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 968 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 969 <&topckgen CLK_TOP_SPI>, 970 <&infracfg_ao CLK_INFRA_AO_SPI4>; 971 clock-names = "parent-clk", "sel-clk", "spi-clk"; 972 status = "disabled"; 973 }; 974 975 spi5: spi@11019000 { 976 compatible = "mediatek,mt8195-spi", 977 "mediatek,mt6765-spi"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 reg = <0 0x11019000 0 0x1000>; 981 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 982 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 983 <&topckgen CLK_TOP_SPI>, 984 <&infracfg_ao CLK_INFRA_AO_SPI5>; 985 clock-names = "parent-clk", "sel-clk", "spi-clk"; 986 status = "disabled"; 987 }; 988 989 spis0: spi@1101d000 { 990 compatible = "mediatek,mt8195-spi-slave"; 991 reg = <0 0x1101d000 0 0x1000>; 992 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 993 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 994 clock-names = "spi"; 995 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 996 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 997 status = "disabled"; 998 }; 999 1000 spis1: spi@1101e000 { 1001 compatible = "mediatek,mt8195-spi-slave"; 1002 reg = <0 0x1101e000 0 0x1000>; 1003 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1004 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1005 clock-names = "spi"; 1006 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1007 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1008 status = "disabled"; 1009 }; 1010 1011 xhci0: usb@11200000 { 1012 compatible = "mediatek,mt8195-xhci", 1013 "mediatek,mtk-xhci"; 1014 reg = <0 0x11200000 0 0x1000>, 1015 <0 0x11203e00 0 0x0100>; 1016 reg-names = "mac", "ippc"; 1017 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1018 phys = <&u2port0 PHY_TYPE_USB2>, 1019 <&u3port0 PHY_TYPE_USB3>; 1020 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1021 <&topckgen CLK_TOP_SSUSB_XHCI>; 1022 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1023 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1024 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1025 <&topckgen CLK_TOP_SSUSB_REF>, 1026 <&apmixedsys CLK_APMIXED_USB1PLL>, 1027 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1028 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 1029 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1030 wakeup-source; 1031 status = "disabled"; 1032 }; 1033 1034 mmc0: mmc@11230000 { 1035 compatible = "mediatek,mt8195-mmc", 1036 "mediatek,mt8183-mmc"; 1037 reg = <0 0x11230000 0 0x10000>, 1038 <0 0x11f50000 0 0x1000>; 1039 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1040 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1041 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1042 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1043 clock-names = "source", "hclk", "source_cg"; 1044 status = "disabled"; 1045 }; 1046 1047 mmc1: mmc@11240000 { 1048 compatible = "mediatek,mt8195-mmc", 1049 "mediatek,mt8183-mmc"; 1050 reg = <0 0x11240000 0 0x1000>, 1051 <0 0x11c70000 0 0x1000>; 1052 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1053 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1054 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1055 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1056 clock-names = "source", "hclk", "source_cg"; 1057 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1058 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1059 status = "disabled"; 1060 }; 1061 1062 mmc2: mmc@11250000 { 1063 compatible = "mediatek,mt8195-mmc", 1064 "mediatek,mt8183-mmc"; 1065 reg = <0 0x11250000 0 0x1000>, 1066 <0 0x11e60000 0 0x1000>; 1067 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1068 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1069 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1070 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1071 clock-names = "source", "hclk", "source_cg"; 1072 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1073 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1074 status = "disabled"; 1075 }; 1076 1077 xhci1: usb@11290000 { 1078 compatible = "mediatek,mt8195-xhci", 1079 "mediatek,mtk-xhci"; 1080 reg = <0 0x11290000 0 0x1000>, 1081 <0 0x11293e00 0 0x0100>; 1082 reg-names = "mac", "ippc"; 1083 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1084 phys = <&u2port1 PHY_TYPE_USB2>; 1085 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1086 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1087 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1088 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1089 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1090 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1091 <&apmixedsys CLK_APMIXED_USB1PLL>, 1092 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1093 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 1094 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1095 wakeup-source; 1096 status = "disabled"; 1097 }; 1098 1099 xhci2: usb@112a0000 { 1100 compatible = "mediatek,mt8195-xhci", 1101 "mediatek,mtk-xhci"; 1102 reg = <0 0x112a0000 0 0x1000>, 1103 <0 0x112a3e00 0 0x0100>; 1104 reg-names = "mac", "ippc"; 1105 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1106 phys = <&u2port2 PHY_TYPE_USB2>; 1107 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1108 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1109 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1110 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1111 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1112 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1113 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1114 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1115 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1116 wakeup-source; 1117 status = "disabled"; 1118 }; 1119 1120 xhci3: usb@112b0000 { 1121 compatible = "mediatek,mt8195-xhci", 1122 "mediatek,mtk-xhci"; 1123 reg = <0 0x112b0000 0 0x1000>, 1124 <0 0x112b3e00 0 0x0100>; 1125 reg-names = "mac", "ippc"; 1126 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1127 phys = <&u2port3 PHY_TYPE_USB2>; 1128 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1129 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1130 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1131 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1132 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1133 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1134 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1135 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 1136 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1137 wakeup-source; 1138 status = "disabled"; 1139 }; 1140 1141 nor_flash: spi@1132c000 { 1142 compatible = "mediatek,mt8195-nor", 1143 "mediatek,mt8173-nor"; 1144 reg = <0 0x1132c000 0 0x1000>; 1145 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1146 clocks = <&topckgen CLK_TOP_SPINOR>, 1147 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1148 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1149 clock-names = "spi", "sf", "axi"; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 efuse: efuse@11c10000 { 1156 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1157 reg = <0 0x11c10000 0 0x1000>; 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1161 reg = <0x184 0x1>; 1162 bits = <0 5>; 1163 }; 1164 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1165 reg = <0x184 0x2>; 1166 bits = <5 5>; 1167 }; 1168 u3_intr_p0: usb3-intr@185 { 1169 reg = <0x185 0x1>; 1170 bits = <2 6>; 1171 }; 1172 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1173 reg = <0x186 0x1>; 1174 bits = <0 5>; 1175 }; 1176 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1177 reg = <0x186 0x2>; 1178 bits = <5 5>; 1179 }; 1180 comb_intr_p1: usb3-intr@187 { 1181 reg = <0x187 0x1>; 1182 bits = <2 6>; 1183 }; 1184 u2_intr_p0: usb2-intr-p0@188,1 { 1185 reg = <0x188 0x1>; 1186 bits = <0 5>; 1187 }; 1188 u2_intr_p1: usb2-intr-p1@188,2 { 1189 reg = <0x188 0x2>; 1190 bits = <5 5>; 1191 }; 1192 u2_intr_p2: usb2-intr-p2@189,1 { 1193 reg = <0x189 0x1>; 1194 bits = <2 5>; 1195 }; 1196 u2_intr_p3: usb2-intr-p3@189,2 { 1197 reg = <0x189 0x2>; 1198 bits = <7 5>; 1199 }; 1200 }; 1201 1202 u3phy2: t-phy@11c40000 { 1203 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1204 #address-cells = <1>; 1205 #size-cells = <1>; 1206 ranges = <0 0 0x11c40000 0x700>; 1207 status = "disabled"; 1208 1209 u2port2: usb-phy@0 { 1210 reg = <0x0 0x700>; 1211 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1212 clock-names = "ref"; 1213 #phy-cells = <1>; 1214 }; 1215 }; 1216 1217 u3phy3: t-phy@11c50000 { 1218 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 ranges = <0 0 0x11c50000 0x700>; 1222 status = "disabled"; 1223 1224 u2port3: usb-phy@0 { 1225 reg = <0x0 0x700>; 1226 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1227 clock-names = "ref"; 1228 #phy-cells = <1>; 1229 }; 1230 }; 1231 1232 i2c5: i2c@11d00000 { 1233 compatible = "mediatek,mt8195-i2c", 1234 "mediatek,mt8192-i2c"; 1235 reg = <0 0x11d00000 0 0x1000>, 1236 <0 0x10220580 0 0x80>; 1237 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1238 clock-div = <1>; 1239 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1240 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1241 clock-names = "main", "dma"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 i2c6: i2c@11d01000 { 1248 compatible = "mediatek,mt8195-i2c", 1249 "mediatek,mt8192-i2c"; 1250 reg = <0 0x11d01000 0 0x1000>, 1251 <0 0x10220600 0 0x80>; 1252 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1253 clock-div = <1>; 1254 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1255 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1256 clock-names = "main", "dma"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 i2c7: i2c@11d02000 { 1263 compatible = "mediatek,mt8195-i2c", 1264 "mediatek,mt8192-i2c"; 1265 reg = <0 0x11d02000 0 0x1000>, 1266 <0 0x10220680 0 0x80>; 1267 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1268 clock-div = <1>; 1269 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1270 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1271 clock-names = "main", "dma"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 imp_iic_wrap_s: clock-controller@11d03000 { 1278 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1279 reg = <0 0x11d03000 0 0x1000>; 1280 #clock-cells = <1>; 1281 }; 1282 1283 i2c0: i2c@11e00000 { 1284 compatible = "mediatek,mt8195-i2c", 1285 "mediatek,mt8192-i2c"; 1286 reg = <0 0x11e00000 0 0x1000>, 1287 <0 0x10220080 0 0x80>; 1288 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1289 clock-div = <1>; 1290 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1291 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1292 clock-names = "main", "dma"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c1: i2c@11e01000 { 1299 compatible = "mediatek,mt8195-i2c", 1300 "mediatek,mt8192-i2c"; 1301 reg = <0 0x11e01000 0 0x1000>, 1302 <0 0x10220200 0 0x80>; 1303 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1304 clock-div = <1>; 1305 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1306 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1307 clock-names = "main", "dma"; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 status = "disabled"; 1311 }; 1312 1313 i2c2: i2c@11e02000 { 1314 compatible = "mediatek,mt8195-i2c", 1315 "mediatek,mt8192-i2c"; 1316 reg = <0 0x11e02000 0 0x1000>, 1317 <0 0x10220380 0 0x80>; 1318 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1319 clock-div = <1>; 1320 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1321 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1322 clock-names = "main", "dma"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c3: i2c@11e03000 { 1329 compatible = "mediatek,mt8195-i2c", 1330 "mediatek,mt8192-i2c"; 1331 reg = <0 0x11e03000 0 0x1000>, 1332 <0 0x10220480 0 0x80>; 1333 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1334 clock-div = <1>; 1335 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1336 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1337 clock-names = "main", "dma"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 i2c4: i2c@11e04000 { 1344 compatible = "mediatek,mt8195-i2c", 1345 "mediatek,mt8192-i2c"; 1346 reg = <0 0x11e04000 0 0x1000>, 1347 <0 0x10220500 0 0x80>; 1348 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1349 clock-div = <1>; 1350 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1351 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1352 clock-names = "main", "dma"; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 status = "disabled"; 1356 }; 1357 1358 imp_iic_wrap_w: clock-controller@11e05000 { 1359 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1360 reg = <0 0x11e05000 0 0x1000>; 1361 #clock-cells = <1>; 1362 }; 1363 1364 u3phy1: t-phy@11e30000 { 1365 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1366 #address-cells = <1>; 1367 #size-cells = <1>; 1368 ranges = <0 0 0x11e30000 0xe00>; 1369 status = "disabled"; 1370 1371 u2port1: usb-phy@0 { 1372 reg = <0x0 0x700>; 1373 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1374 <&clk26m>; 1375 clock-names = "ref", "da_ref"; 1376 #phy-cells = <1>; 1377 }; 1378 1379 u3port1: usb-phy@700 { 1380 reg = <0x700 0x700>; 1381 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1382 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1383 clock-names = "ref", "da_ref"; 1384 nvmem-cells = <&comb_intr_p1>, 1385 <&comb_rx_imp_p1>, 1386 <&comb_tx_imp_p1>; 1387 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1388 #phy-cells = <1>; 1389 }; 1390 }; 1391 1392 u3phy0: t-phy@11e40000 { 1393 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1394 #address-cells = <1>; 1395 #size-cells = <1>; 1396 ranges = <0 0 0x11e40000 0xe00>; 1397 status = "disabled"; 1398 1399 u2port0: usb-phy@0 { 1400 reg = <0x0 0x700>; 1401 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1402 <&clk26m>; 1403 clock-names = "ref", "da_ref"; 1404 #phy-cells = <1>; 1405 }; 1406 1407 u3port0: usb-phy@700 { 1408 reg = <0x700 0x700>; 1409 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1410 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1411 clock-names = "ref", "da_ref"; 1412 nvmem-cells = <&u3_intr_p0>, 1413 <&u3_rx_imp_p0>, 1414 <&u3_tx_imp_p0>; 1415 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1416 #phy-cells = <1>; 1417 }; 1418 }; 1419 1420 ufsphy: ufs-phy@11fa0000 { 1421 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1422 reg = <0 0x11fa0000 0 0xc000>; 1423 clocks = <&clk26m>, <&clk26m>; 1424 clock-names = "unipro", "mp"; 1425 #phy-cells = <0>; 1426 status = "disabled"; 1427 }; 1428 1429 mfgcfg: clock-controller@13fbf000 { 1430 compatible = "mediatek,mt8195-mfgcfg"; 1431 reg = <0 0x13fbf000 0 0x1000>; 1432 #clock-cells = <1>; 1433 }; 1434 1435 vppsys0: clock-controller@14000000 { 1436 compatible = "mediatek,mt8195-vppsys0"; 1437 reg = <0 0x14000000 0 0x1000>; 1438 #clock-cells = <1>; 1439 }; 1440 1441 wpesys: clock-controller@14e00000 { 1442 compatible = "mediatek,mt8195-wpesys"; 1443 reg = <0 0x14e00000 0 0x1000>; 1444 #clock-cells = <1>; 1445 }; 1446 1447 wpesys_vpp0: clock-controller@14e02000 { 1448 compatible = "mediatek,mt8195-wpesys_vpp0"; 1449 reg = <0 0x14e02000 0 0x1000>; 1450 #clock-cells = <1>; 1451 }; 1452 1453 wpesys_vpp1: clock-controller@14e03000 { 1454 compatible = "mediatek,mt8195-wpesys_vpp1"; 1455 reg = <0 0x14e03000 0 0x1000>; 1456 #clock-cells = <1>; 1457 }; 1458 1459 vppsys1: clock-controller@14f00000 { 1460 compatible = "mediatek,mt8195-vppsys1"; 1461 reg = <0 0x14f00000 0 0x1000>; 1462 #clock-cells = <1>; 1463 }; 1464 1465 imgsys: clock-controller@15000000 { 1466 compatible = "mediatek,mt8195-imgsys"; 1467 reg = <0 0x15000000 0 0x1000>; 1468 #clock-cells = <1>; 1469 }; 1470 1471 imgsys1_dip_top: clock-controller@15110000 { 1472 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1473 reg = <0 0x15110000 0 0x1000>; 1474 #clock-cells = <1>; 1475 }; 1476 1477 imgsys1_dip_nr: clock-controller@15130000 { 1478 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1479 reg = <0 0x15130000 0 0x1000>; 1480 #clock-cells = <1>; 1481 }; 1482 1483 imgsys1_wpe: clock-controller@15220000 { 1484 compatible = "mediatek,mt8195-imgsys1_wpe"; 1485 reg = <0 0x15220000 0 0x1000>; 1486 #clock-cells = <1>; 1487 }; 1488 1489 ipesys: clock-controller@15330000 { 1490 compatible = "mediatek,mt8195-ipesys"; 1491 reg = <0 0x15330000 0 0x1000>; 1492 #clock-cells = <1>; 1493 }; 1494 1495 camsys: clock-controller@16000000 { 1496 compatible = "mediatek,mt8195-camsys"; 1497 reg = <0 0x16000000 0 0x1000>; 1498 #clock-cells = <1>; 1499 }; 1500 1501 camsys_rawa: clock-controller@1604f000 { 1502 compatible = "mediatek,mt8195-camsys_rawa"; 1503 reg = <0 0x1604f000 0 0x1000>; 1504 #clock-cells = <1>; 1505 }; 1506 1507 camsys_yuva: clock-controller@1606f000 { 1508 compatible = "mediatek,mt8195-camsys_yuva"; 1509 reg = <0 0x1606f000 0 0x1000>; 1510 #clock-cells = <1>; 1511 }; 1512 1513 camsys_rawb: clock-controller@1608f000 { 1514 compatible = "mediatek,mt8195-camsys_rawb"; 1515 reg = <0 0x1608f000 0 0x1000>; 1516 #clock-cells = <1>; 1517 }; 1518 1519 camsys_yuvb: clock-controller@160af000 { 1520 compatible = "mediatek,mt8195-camsys_yuvb"; 1521 reg = <0 0x160af000 0 0x1000>; 1522 #clock-cells = <1>; 1523 }; 1524 1525 camsys_mraw: clock-controller@16140000 { 1526 compatible = "mediatek,mt8195-camsys_mraw"; 1527 reg = <0 0x16140000 0 0x1000>; 1528 #clock-cells = <1>; 1529 }; 1530 1531 ccusys: clock-controller@17200000 { 1532 compatible = "mediatek,mt8195-ccusys"; 1533 reg = <0 0x17200000 0 0x1000>; 1534 #clock-cells = <1>; 1535 }; 1536 1537 vdecsys_soc: clock-controller@1800f000 { 1538 compatible = "mediatek,mt8195-vdecsys_soc"; 1539 reg = <0 0x1800f000 0 0x1000>; 1540 #clock-cells = <1>; 1541 }; 1542 1543 vdecsys: clock-controller@1802f000 { 1544 compatible = "mediatek,mt8195-vdecsys"; 1545 reg = <0 0x1802f000 0 0x1000>; 1546 #clock-cells = <1>; 1547 }; 1548 1549 vdecsys_core1: clock-controller@1803f000 { 1550 compatible = "mediatek,mt8195-vdecsys_core1"; 1551 reg = <0 0x1803f000 0 0x1000>; 1552 #clock-cells = <1>; 1553 }; 1554 1555 apusys_pll: clock-controller@190f3000 { 1556 compatible = "mediatek,mt8195-apusys_pll"; 1557 reg = <0 0x190f3000 0 0x1000>; 1558 #clock-cells = <1>; 1559 }; 1560 1561 vencsys: clock-controller@1a000000 { 1562 compatible = "mediatek,mt8195-vencsys"; 1563 reg = <0 0x1a000000 0 0x1000>; 1564 #clock-cells = <1>; 1565 }; 1566 1567 vencsys_core1: clock-controller@1b000000 { 1568 compatible = "mediatek,mt8195-vencsys_core1"; 1569 reg = <0 0x1b000000 0 0x1000>; 1570 #clock-cells = <1>; 1571 }; 1572 1573 vdosys0: syscon@1c01a000 { 1574 compatible = "mediatek,mt8195-mmsys", "syscon"; 1575 reg = <0 0x1c01a000 0 0x1000>; 1576 #clock-cells = <1>; 1577 }; 1578 1579 vdosys1: syscon@1c100000 { 1580 compatible = "mediatek,mt8195-mmsys", "syscon"; 1581 reg = <0 0x1c100000 0 0x1000>; 1582 #clock-cells = <1>; 1583 }; 1584 }; 1585}; 1586