mt8195.dtsi (6aa5b46d1755a2e3db86fa6bd3f3d15d3c012594) mt8195.dtsi (2b515194bf0cb8f380586e96d2530a51b1878e6a)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
13#include <dt-bindings/power/mt8195-power.h>
13
14/ {
15 compatible = "mediatek,mt8195";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 cpus {

--- 312 unchanged lines hidden (view full) ---

333 gpio-controller;
334 #gpio-cells = <2>;
335 gpio-ranges = <&pio 0 0 144>;
336 interrupt-controller;
337 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
338 #interrupt-cells = <2>;
339 };
340
14
15/ {
16 compatible = "mediatek,mt8195";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {

--- 312 unchanged lines hidden (view full) ---

334 gpio-controller;
335 #gpio-cells = <2>;
336 gpio-ranges = <&pio 0 0 144>;
337 interrupt-controller;
338 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
339 #interrupt-cells = <2>;
340 };
341
342 scpsys: syscon@10006000 {
343 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
344 reg = <0 0x10006000 0 0x1000>;
345
346 /* System Power Manager */
347 spm: power-controller {
348 compatible = "mediatek,mt8195-power-controller";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 #power-domain-cells = <1>;
352
353 /* power domain of the SoC */
354 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
355 reg = <MT8195_POWER_DOMAIN_MFG0>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 #power-domain-cells = <1>;
359
360 power-domain@MT8195_POWER_DOMAIN_MFG1 {
361 reg = <MT8195_POWER_DOMAIN_MFG1>;
362 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
363 clock-names = "mfg";
364 mediatek,infracfg = <&infracfg_ao>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 #power-domain-cells = <1>;
368
369 power-domain@MT8195_POWER_DOMAIN_MFG2 {
370 reg = <MT8195_POWER_DOMAIN_MFG2>;
371 #power-domain-cells = <0>;
372 };
373
374 power-domain@MT8195_POWER_DOMAIN_MFG3 {
375 reg = <MT8195_POWER_DOMAIN_MFG3>;
376 #power-domain-cells = <0>;
377 };
378
379 power-domain@MT8195_POWER_DOMAIN_MFG4 {
380 reg = <MT8195_POWER_DOMAIN_MFG4>;
381 #power-domain-cells = <0>;
382 };
383
384 power-domain@MT8195_POWER_DOMAIN_MFG5 {
385 reg = <MT8195_POWER_DOMAIN_MFG5>;
386 #power-domain-cells = <0>;
387 };
388
389 power-domain@MT8195_POWER_DOMAIN_MFG6 {
390 reg = <MT8195_POWER_DOMAIN_MFG6>;
391 #power-domain-cells = <0>;
392 };
393 };
394 };
395
396 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
397 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
398 clocks = <&topckgen CLK_TOP_VPP>,
399 <&topckgen CLK_TOP_CAM>,
400 <&topckgen CLK_TOP_CCU>,
401 <&topckgen CLK_TOP_IMG>,
402 <&topckgen CLK_TOP_VENC>,
403 <&topckgen CLK_TOP_VDEC>,
404 <&topckgen CLK_TOP_WPE_VPP>,
405 <&topckgen CLK_TOP_CFG_VPP0>,
406 <&vppsys0 CLK_VPP0_SMI_COMMON>,
407 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
408 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
409 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
410 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
411 <&vppsys0 CLK_VPP0_GALS_INFRA>,
412 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
413 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
414 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
415 <&vppsys0 CLK_VPP0_SMI_REORDER>,
416 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
417 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
418 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
419 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
420 <&vppsys0 CLK_VPP0_SMI_RSI>,
421 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
422 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
423 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
424 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
425 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
426 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
427 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
428 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
429 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
430 "vppsys0-12", "vppsys0-13", "vppsys0-14",
431 "vppsys0-15", "vppsys0-16", "vppsys0-17",
432 "vppsys0-18";
433 mediatek,infracfg = <&infracfg_ao>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 #power-domain-cells = <1>;
437
438 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
439 reg = <MT8195_POWER_DOMAIN_VDEC1>;
440 clocks = <&vdecsys CLK_VDEC_LARB1>;
441 clock-names = "vdec1-0";
442 mediatek,infracfg = <&infracfg_ao>;
443 #power-domain-cells = <0>;
444 };
445
446 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
447 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
448 mediatek,infracfg = <&infracfg_ao>;
449 #power-domain-cells = <0>;
450 };
451
452 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
453 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
454 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
455 <&vdosys0 CLK_VDO0_SMI_GALS>,
456 <&vdosys0 CLK_VDO0_SMI_COMMON>,
457 <&vdosys0 CLK_VDO0_SMI_EMI>,
458 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
459 <&vdosys0 CLK_VDO0_SMI_LARB>,
460 <&vdosys0 CLK_VDO0_SMI_RSI>;
461 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
462 "vdosys0-2", "vdosys0-3",
463 "vdosys0-4", "vdosys0-5";
464 mediatek,infracfg = <&infracfg_ao>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 #power-domain-cells = <1>;
468
469 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
470 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
471 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
472 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
473 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
474 clock-names = "vppsys1", "vppsys1-0",
475 "vppsys1-1";
476 mediatek,infracfg = <&infracfg_ao>;
477 #power-domain-cells = <0>;
478 };
479
480 power-domain@MT8195_POWER_DOMAIN_WPESYS {
481 reg = <MT8195_POWER_DOMAIN_WPESYS>;
482 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
483 <&wpesys CLK_WPE_SMI_LARB8>,
484 <&wpesys CLK_WPE_SMI_LARB7_P>,
485 <&wpesys CLK_WPE_SMI_LARB8_P>;
486 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
487 "wepsys-3";
488 mediatek,infracfg = <&infracfg_ao>;
489 #power-domain-cells = <0>;
490 };
491
492 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
493 reg = <MT8195_POWER_DOMAIN_VDEC0>;
494 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
495 clock-names = "vdec0-0";
496 mediatek,infracfg = <&infracfg_ao>;
497 #power-domain-cells = <0>;
498 };
499
500 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
501 reg = <MT8195_POWER_DOMAIN_VDEC2>;
502 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
503 clock-names = "vdec2-0";
504 mediatek,infracfg = <&infracfg_ao>;
505 #power-domain-cells = <0>;
506 };
507
508 power-domain@MT8195_POWER_DOMAIN_VENC {
509 reg = <MT8195_POWER_DOMAIN_VENC>;
510 mediatek,infracfg = <&infracfg_ao>;
511 #power-domain-cells = <0>;
512 };
513
514 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
515 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
516 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
517 <&vdosys1 CLK_VDO1_SMI_LARB2>,
518 <&vdosys1 CLK_VDO1_SMI_LARB3>,
519 <&vdosys1 CLK_VDO1_GALS>;
520 clock-names = "vdosys1", "vdosys1-0",
521 "vdosys1-1", "vdosys1-2";
522 mediatek,infracfg = <&infracfg_ao>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 #power-domain-cells = <1>;
526
527 power-domain@MT8195_POWER_DOMAIN_DP_TX {
528 reg = <MT8195_POWER_DOMAIN_DP_TX>;
529 mediatek,infracfg = <&infracfg_ao>;
530 #power-domain-cells = <0>;
531 };
532
533 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
534 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
535 mediatek,infracfg = <&infracfg_ao>;
536 #power-domain-cells = <0>;
537 };
538
539 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
540 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
541 clocks = <&topckgen CLK_TOP_HDMI_APB>;
542 clock-names = "hdmi_tx";
543 #power-domain-cells = <0>;
544 };
545 };
546
547 power-domain@MT8195_POWER_DOMAIN_IMG {
548 reg = <MT8195_POWER_DOMAIN_IMG>;
549 clocks = <&imgsys CLK_IMG_LARB9>,
550 <&imgsys CLK_IMG_GALS>;
551 clock-names = "img-0", "img-1";
552 mediatek,infracfg = <&infracfg_ao>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 #power-domain-cells = <1>;
556
557 power-domain@MT8195_POWER_DOMAIN_DIP {
558 reg = <MT8195_POWER_DOMAIN_DIP>;
559 #power-domain-cells = <0>;
560 };
561
562 power-domain@MT8195_POWER_DOMAIN_IPE {
563 reg = <MT8195_POWER_DOMAIN_IPE>;
564 clocks = <&topckgen CLK_TOP_IPE>,
565 <&imgsys CLK_IMG_IPE>,
566 <&ipesys CLK_IPE_SMI_LARB12>;
567 clock-names = "ipe", "ipe-0", "ipe-1";
568 mediatek,infracfg = <&infracfg_ao>;
569 #power-domain-cells = <0>;
570 };
571 };
572
573 power-domain@MT8195_POWER_DOMAIN_CAM {
574 reg = <MT8195_POWER_DOMAIN_CAM>;
575 clocks = <&camsys CLK_CAM_LARB13>,
576 <&camsys CLK_CAM_LARB14>,
577 <&camsys CLK_CAM_CAM2MM0_GALS>,
578 <&camsys CLK_CAM_CAM2MM1_GALS>,
579 <&camsys CLK_CAM_CAM2SYS_GALS>;
580 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
581 "cam-4";
582 mediatek,infracfg = <&infracfg_ao>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 #power-domain-cells = <1>;
586
587 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
588 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
589 #power-domain-cells = <0>;
590 };
591
592 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
593 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
594 #power-domain-cells = <0>;
595 };
596
597 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
598 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
599 #power-domain-cells = <0>;
600 };
601 };
602 };
603 };
604
605 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
606 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
607 mediatek,infracfg = <&infracfg_ao>;
608 #power-domain-cells = <0>;
609 };
610
611 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
612 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
613 mediatek,infracfg = <&infracfg_ao>;
614 #power-domain-cells = <0>;
615 };
616
617 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
618 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
619 #power-domain-cells = <0>;
620 };
621
622 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
623 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
624 #power-domain-cells = <0>;
625 };
626
627 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
628 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
629 clocks = <&topckgen CLK_TOP_SENINF>,
630 <&topckgen CLK_TOP_SENINF2>;
631 clock-names = "csi_rx_top", "csi_rx_top1";
632 #power-domain-cells = <0>;
633 };
634
635 power-domain@MT8195_POWER_DOMAIN_ETHER {
636 reg = <MT8195_POWER_DOMAIN_ETHER>;
637 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
638 clock-names = "ether";
639 #power-domain-cells = <0>;
640 };
641
642 power-domain@MT8195_POWER_DOMAIN_ADSP {
643 reg = <MT8195_POWER_DOMAIN_ADSP>;
644 clocks = <&topckgen CLK_TOP_ADSP>,
645 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
646 clock-names = "adsp", "adsp1";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 mediatek,infracfg = <&infracfg_ao>;
650 #power-domain-cells = <1>;
651
652 power-domain@MT8195_POWER_DOMAIN_AUDIO {
653 reg = <MT8195_POWER_DOMAIN_AUDIO>;
654 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
655 <&topckgen CLK_TOP_AUD_INTBUS>,
656 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
657 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
658 clock-names = "audio", "audio1", "audio2",
659 "audio3";
660 mediatek,infracfg = <&infracfg_ao>;
661 #power-domain-cells = <0>;
662 };
663 };
664 };
665 };
666
341 watchdog: watchdog@10007000 {
342 compatible = "mediatek,mt8195-wdt",
343 "mediatek,mt6589-wdt";
344 mediatek,disable-extrst;
345 reg = <0 0x10007000 0 0x100>;
346 };
347
348 apmixedsys: syscon@1000c000 {

--- 788 unchanged lines hidden --- 		667 watchdog: watchdog@10007000 {
668 compatible = "mediatek,mt8195-wdt",
669 "mediatek,mt6589-wdt";
670 mediatek,disable-extrst;
671 reg = <0 0x10007000 0 0x100>;
672 };
673
674 apmixedsys: syscon@1000c000 {

--- 788 unchanged lines hidden ---