1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13 14/ { 15 compatible = "mediatek,mt8195"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a55"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 performance-domains = <&performance 0>; 30 clock-frequency = <1701000000>; 31 capacity-dmips-mhz = <578>; 32 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 33 next-level-cache = <&l2_0>; 34 #cooling-cells = <2>; 35 }; 36 37 cpu1: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a55"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 performance-domains = <&performance 0>; 43 clock-frequency = <1701000000>; 44 capacity-dmips-mhz = <578>; 45 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 46 next-level-cache = <&l2_0>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu2: cpu@200 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x200>; 54 enable-method = "psci"; 55 performance-domains = <&performance 0>; 56 clock-frequency = <1701000000>; 57 capacity-dmips-mhz = <578>; 58 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 59 next-level-cache = <&l2_0>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu3: cpu@300 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x300>; 67 enable-method = "psci"; 68 performance-domains = <&performance 0>; 69 clock-frequency = <1701000000>; 70 capacity-dmips-mhz = <578>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu4: cpu@400 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78"; 79 reg = <0x400>; 80 enable-method = "psci"; 81 performance-domains = <&performance 1>; 82 clock-frequency = <2171000000>; 83 capacity-dmips-mhz = <1024>; 84 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 85 next-level-cache = <&l2_1>; 86 #cooling-cells = <2>; 87 }; 88 89 cpu5: cpu@500 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a78"; 92 reg = <0x500>; 93 enable-method = "psci"; 94 performance-domains = <&performance 1>; 95 clock-frequency = <2171000000>; 96 capacity-dmips-mhz = <1024>; 97 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 98 next-level-cache = <&l2_1>; 99 #cooling-cells = <2>; 100 }; 101 102 cpu6: cpu@600 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a78"; 105 reg = <0x600>; 106 enable-method = "psci"; 107 performance-domains = <&performance 1>; 108 clock-frequency = <2171000000>; 109 capacity-dmips-mhz = <1024>; 110 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 111 next-level-cache = <&l2_1>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu7: cpu@700 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a78"; 118 reg = <0x700>; 119 enable-method = "psci"; 120 performance-domains = <&performance 1>; 121 clock-frequency = <2171000000>; 122 capacity-dmips-mhz = <1024>; 123 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu-map { 129 cluster0 { 130 core0 { 131 cpu = <&cpu0>; 132 }; 133 134 core1 { 135 cpu = <&cpu1>; 136 }; 137 138 core2 { 139 cpu = <&cpu2>; 140 }; 141 142 core3 { 143 cpu = <&cpu3>; 144 }; 145 }; 146 147 cluster1 { 148 core0 { 149 cpu = <&cpu4>; 150 }; 151 152 core1 { 153 cpu = <&cpu5>; 154 }; 155 156 core2 { 157 cpu = <&cpu6>; 158 }; 159 160 core3 { 161 cpu = <&cpu7>; 162 }; 163 }; 164 }; 165 166 idle-states { 167 entry-method = "psci"; 168 169 cpu_off_l: cpu-off-l { 170 compatible = "arm,idle-state"; 171 arm,psci-suspend-param = <0x00010001>; 172 local-timer-stop; 173 entry-latency-us = <50>; 174 exit-latency-us = <95>; 175 min-residency-us = <580>; 176 }; 177 178 cpu_off_b: cpu-off-b { 179 compatible = "arm,idle-state"; 180 arm,psci-suspend-param = <0x00010001>; 181 local-timer-stop; 182 entry-latency-us = <45>; 183 exit-latency-us = <140>; 184 min-residency-us = <740>; 185 }; 186 187 cluster_off_l: cluster-off-l { 188 compatible = "arm,idle-state"; 189 arm,psci-suspend-param = <0x01010002>; 190 local-timer-stop; 191 entry-latency-us = <55>; 192 exit-latency-us = <155>; 193 min-residency-us = <840>; 194 }; 195 196 cluster_off_b: cluster-off-b { 197 compatible = "arm,idle-state"; 198 arm,psci-suspend-param = <0x01010002>; 199 local-timer-stop; 200 entry-latency-us = <50>; 201 exit-latency-us = <200>; 202 min-residency-us = <1000>; 203 }; 204 }; 205 206 l2_0: l2-cache0 { 207 compatible = "cache"; 208 next-level-cache = <&l3_0>; 209 }; 210 211 l2_1: l2-cache1 { 212 compatible = "cache"; 213 next-level-cache = <&l3_0>; 214 }; 215 216 l3_0: l3-cache { 217 compatible = "cache"; 218 }; 219 }; 220 221 dsu-pmu { 222 compatible = "arm,dsu-pmu"; 223 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 224 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 225 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 226 }; 227 228 clk26m: oscillator-26m { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <26000000>; 232 clock-output-names = "clk26m"; 233 }; 234 235 clk32k: oscillator-32k { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <32768>; 239 clock-output-names = "clk32k"; 240 }; 241 242 performance: performance-controller@11bc10 { 243 compatible = "mediatek,cpufreq-hw"; 244 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 245 #performance-domain-cells = <1>; 246 }; 247 248 pmu-a55 { 249 compatible = "arm,cortex-a55-pmu"; 250 interrupt-parent = <&gic>; 251 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 252 }; 253 254 pmu-a78 { 255 compatible = "arm,cortex-a78-pmu"; 256 interrupt-parent = <&gic>; 257 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 258 }; 259 260 psci { 261 compatible = "arm,psci-1.0"; 262 method = "smc"; 263 }; 264 265 timer: timer { 266 compatible = "arm,armv8-timer"; 267 interrupt-parent = <&gic>; 268 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 269 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 270 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 271 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 272 }; 273 274 soc { 275 #address-cells = <2>; 276 #size-cells = <2>; 277 compatible = "simple-bus"; 278 ranges; 279 280 gic: interrupt-controller@c000000 { 281 compatible = "arm,gic-v3"; 282 #interrupt-cells = <4>; 283 #redistributor-regions = <1>; 284 interrupt-parent = <&gic>; 285 interrupt-controller; 286 reg = <0 0x0c000000 0 0x40000>, 287 <0 0x0c040000 0 0x200000>; 288 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 289 290 ppi-partitions { 291 ppi_cluster0: interrupt-partition-0 { 292 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 293 }; 294 295 ppi_cluster1: interrupt-partition-1 { 296 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 297 }; 298 }; 299 }; 300 301 topckgen: syscon@10000000 { 302 compatible = "mediatek,mt8195-topckgen", "syscon"; 303 reg = <0 0x10000000 0 0x1000>; 304 #clock-cells = <1>; 305 }; 306 307 infracfg_ao: syscon@10001000 { 308 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 309 reg = <0 0x10001000 0 0x1000>; 310 #clock-cells = <1>; 311 #reset-cells = <1>; 312 }; 313 314 pericfg: syscon@10003000 { 315 compatible = "mediatek,mt8195-pericfg", "syscon"; 316 reg = <0 0x10003000 0 0x1000>; 317 #clock-cells = <1>; 318 }; 319 320 pio: pinctrl@10005000 { 321 compatible = "mediatek,mt8195-pinctrl"; 322 reg = <0 0x10005000 0 0x1000>, 323 <0 0x11d10000 0 0x1000>, 324 <0 0x11d30000 0 0x1000>, 325 <0 0x11d40000 0 0x1000>, 326 <0 0x11e20000 0 0x1000>, 327 <0 0x11eb0000 0 0x1000>, 328 <0 0x11f40000 0 0x1000>, 329 <0 0x1000b000 0 0x1000>; 330 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 331 "iocfg_br", "iocfg_lm", "iocfg_rb", 332 "iocfg_tl", "eint"; 333 gpio-controller; 334 #gpio-cells = <2>; 335 gpio-ranges = <&pio 0 0 144>; 336 interrupt-controller; 337 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 338 #interrupt-cells = <2>; 339 }; 340 341 watchdog: watchdog@10007000 { 342 compatible = "mediatek,mt8195-wdt", 343 "mediatek,mt6589-wdt"; 344 mediatek,disable-extrst; 345 reg = <0 0x10007000 0 0x100>; 346 }; 347 348 apmixedsys: syscon@1000c000 { 349 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 350 reg = <0 0x1000c000 0 0x1000>; 351 #clock-cells = <1>; 352 }; 353 354 systimer: timer@10017000 { 355 compatible = "mediatek,mt8195-timer", 356 "mediatek,mt6765-timer"; 357 reg = <0 0x10017000 0 0x1000>; 358 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 359 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 360 }; 361 362 pwrap: pwrap@10024000 { 363 compatible = "mediatek,mt8195-pwrap", "syscon"; 364 reg = <0 0x10024000 0 0x1000>; 365 reg-names = "pwrap"; 366 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 367 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 368 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 369 clock-names = "spi", "wrap"; 370 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 371 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 372 }; 373 374 scp_adsp: clock-controller@10720000 { 375 compatible = "mediatek,mt8195-scp_adsp"; 376 reg = <0 0x10720000 0 0x1000>; 377 #clock-cells = <1>; 378 }; 379 380 uart0: serial@11001100 { 381 compatible = "mediatek,mt8195-uart", 382 "mediatek,mt6577-uart"; 383 reg = <0 0x11001100 0 0x100>; 384 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 385 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 386 clock-names = "baud", "bus"; 387 status = "disabled"; 388 }; 389 390 uart1: serial@11001200 { 391 compatible = "mediatek,mt8195-uart", 392 "mediatek,mt6577-uart"; 393 reg = <0 0x11001200 0 0x100>; 394 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 395 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 396 clock-names = "baud", "bus"; 397 status = "disabled"; 398 }; 399 400 uart2: serial@11001300 { 401 compatible = "mediatek,mt8195-uart", 402 "mediatek,mt6577-uart"; 403 reg = <0 0x11001300 0 0x100>; 404 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 405 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 406 clock-names = "baud", "bus"; 407 status = "disabled"; 408 }; 409 410 uart3: serial@11001400 { 411 compatible = "mediatek,mt8195-uart", 412 "mediatek,mt6577-uart"; 413 reg = <0 0x11001400 0 0x100>; 414 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 415 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 416 clock-names = "baud", "bus"; 417 status = "disabled"; 418 }; 419 420 uart4: serial@11001500 { 421 compatible = "mediatek,mt8195-uart", 422 "mediatek,mt6577-uart"; 423 reg = <0 0x11001500 0 0x100>; 424 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 425 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 426 clock-names = "baud", "bus"; 427 status = "disabled"; 428 }; 429 430 uart5: serial@11001600 { 431 compatible = "mediatek,mt8195-uart", 432 "mediatek,mt6577-uart"; 433 reg = <0 0x11001600 0 0x100>; 434 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 435 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 436 clock-names = "baud", "bus"; 437 status = "disabled"; 438 }; 439 440 auxadc: auxadc@11002000 { 441 compatible = "mediatek,mt8195-auxadc", 442 "mediatek,mt8173-auxadc"; 443 reg = <0 0x11002000 0 0x1000>; 444 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 445 clock-names = "main"; 446 #io-channel-cells = <1>; 447 status = "disabled"; 448 }; 449 450 pericfg_ao: syscon@11003000 { 451 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 452 reg = <0 0x11003000 0 0x1000>; 453 #clock-cells = <1>; 454 }; 455 456 spi0: spi@1100a000 { 457 compatible = "mediatek,mt8195-spi", 458 "mediatek,mt6765-spi"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0 0x1100a000 0 0x1000>; 462 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 463 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 464 <&topckgen CLK_TOP_SPI>, 465 <&infracfg_ao CLK_INFRA_AO_SPI0>; 466 clock-names = "parent-clk", "sel-clk", "spi-clk"; 467 status = "disabled"; 468 }; 469 470 spi1: spi@11010000 { 471 compatible = "mediatek,mt8195-spi", 472 "mediatek,mt6765-spi"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <0 0x11010000 0 0x1000>; 476 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 477 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 478 <&topckgen CLK_TOP_SPI>, 479 <&infracfg_ao CLK_INFRA_AO_SPI1>; 480 clock-names = "parent-clk", "sel-clk", "spi-clk"; 481 status = "disabled"; 482 }; 483 484 spi2: spi@11012000 { 485 compatible = "mediatek,mt8195-spi", 486 "mediatek,mt6765-spi"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 reg = <0 0x11012000 0 0x1000>; 490 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 491 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 492 <&topckgen CLK_TOP_SPI>, 493 <&infracfg_ao CLK_INFRA_AO_SPI2>; 494 clock-names = "parent-clk", "sel-clk", "spi-clk"; 495 status = "disabled"; 496 }; 497 498 spi3: spi@11013000 { 499 compatible = "mediatek,mt8195-spi", 500 "mediatek,mt6765-spi"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0 0x11013000 0 0x1000>; 504 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 505 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 506 <&topckgen CLK_TOP_SPI>, 507 <&infracfg_ao CLK_INFRA_AO_SPI3>; 508 clock-names = "parent-clk", "sel-clk", "spi-clk"; 509 status = "disabled"; 510 }; 511 512 spi4: spi@11018000 { 513 compatible = "mediatek,mt8195-spi", 514 "mediatek,mt6765-spi"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0 0x11018000 0 0x1000>; 518 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 519 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 520 <&topckgen CLK_TOP_SPI>, 521 <&infracfg_ao CLK_INFRA_AO_SPI4>; 522 clock-names = "parent-clk", "sel-clk", "spi-clk"; 523 status = "disabled"; 524 }; 525 526 spi5: spi@11019000 { 527 compatible = "mediatek,mt8195-spi", 528 "mediatek,mt6765-spi"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0 0x11019000 0 0x1000>; 532 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 533 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 534 <&topckgen CLK_TOP_SPI>, 535 <&infracfg_ao CLK_INFRA_AO_SPI5>; 536 clock-names = "parent-clk", "sel-clk", "spi-clk"; 537 status = "disabled"; 538 }; 539 540 spis0: spi@1101d000 { 541 compatible = "mediatek,mt8195-spi-slave"; 542 reg = <0 0x1101d000 0 0x1000>; 543 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 544 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 545 clock-names = "spi"; 546 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 547 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 548 status = "disabled"; 549 }; 550 551 spis1: spi@1101e000 { 552 compatible = "mediatek,mt8195-spi-slave"; 553 reg = <0 0x1101e000 0 0x1000>; 554 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 555 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 556 clock-names = "spi"; 557 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 558 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 559 status = "disabled"; 560 }; 561 562 xhci0: usb@11200000 { 563 compatible = "mediatek,mt8195-xhci", 564 "mediatek,mtk-xhci"; 565 reg = <0 0x11200000 0 0x1000>, 566 <0 0x11203e00 0 0x0100>; 567 reg-names = "mac", "ippc"; 568 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 569 phys = <&u2port0 PHY_TYPE_USB2>, 570 <&u3port0 PHY_TYPE_USB3>; 571 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 572 <&topckgen CLK_TOP_SSUSB_XHCI>; 573 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 574 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 575 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 576 <&topckgen CLK_TOP_SSUSB_REF>, 577 <&apmixedsys CLK_APMIXED_USB1PLL>, 578 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 579 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 580 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 581 wakeup-source; 582 status = "disabled"; 583 }; 584 585 mmc0: mmc@11230000 { 586 compatible = "mediatek,mt8195-mmc", 587 "mediatek,mt8183-mmc"; 588 reg = <0 0x11230000 0 0x10000>, 589 <0 0x11f50000 0 0x1000>; 590 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 591 clocks = <&topckgen CLK_TOP_MSDC50_0>, 592 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 593 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 594 clock-names = "source", "hclk", "source_cg"; 595 status = "disabled"; 596 }; 597 598 mmc1: mmc@11240000 { 599 compatible = "mediatek,mt8195-mmc", 600 "mediatek,mt8183-mmc"; 601 reg = <0 0x11240000 0 0x1000>, 602 <0 0x11c70000 0 0x1000>; 603 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 604 clocks = <&topckgen CLK_TOP_MSDC30_1>, 605 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 606 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 607 clock-names = "source", "hclk", "source_cg"; 608 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 609 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 610 status = "disabled"; 611 }; 612 613 mmc2: mmc@11250000 { 614 compatible = "mediatek,mt8195-mmc", 615 "mediatek,mt8183-mmc"; 616 reg = <0 0x11250000 0 0x1000>, 617 <0 0x11e60000 0 0x1000>; 618 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 619 clocks = <&topckgen CLK_TOP_MSDC30_2>, 620 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 621 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 622 clock-names = "source", "hclk", "source_cg"; 623 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 624 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 625 status = "disabled"; 626 }; 627 628 xhci1: usb@11290000 { 629 compatible = "mediatek,mt8195-xhci", 630 "mediatek,mtk-xhci"; 631 reg = <0 0x11290000 0 0x1000>, 632 <0 0x11293e00 0 0x0100>; 633 reg-names = "mac", "ippc"; 634 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 635 phys = <&u2port1 PHY_TYPE_USB2>; 636 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 637 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 638 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 639 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 640 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 641 <&topckgen CLK_TOP_SSUSB_P1_REF>, 642 <&apmixedsys CLK_APMIXED_USB1PLL>, 643 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 644 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 645 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 646 wakeup-source; 647 status = "disabled"; 648 }; 649 650 xhci2: usb@112a0000 { 651 compatible = "mediatek,mt8195-xhci", 652 "mediatek,mtk-xhci"; 653 reg = <0 0x112a0000 0 0x1000>, 654 <0 0x112a3e00 0 0x0100>; 655 reg-names = "mac", "ippc"; 656 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 657 phys = <&u2port2 PHY_TYPE_USB2>; 658 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 659 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 660 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 661 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 662 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 663 <&topckgen CLK_TOP_SSUSB_P2_REF>, 664 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 665 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 666 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 667 wakeup-source; 668 status = "disabled"; 669 }; 670 671 xhci3: usb@112b0000 { 672 compatible = "mediatek,mt8195-xhci", 673 "mediatek,mtk-xhci"; 674 reg = <0 0x112b0000 0 0x1000>, 675 <0 0x112b3e00 0 0x0100>; 676 reg-names = "mac", "ippc"; 677 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 678 phys = <&u2port3 PHY_TYPE_USB2>; 679 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 680 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 681 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 682 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 683 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 684 <&topckgen CLK_TOP_SSUSB_P3_REF>, 685 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 686 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 687 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 688 wakeup-source; 689 status = "disabled"; 690 }; 691 692 nor_flash: spi@1132c000 { 693 compatible = "mediatek,mt8195-nor", 694 "mediatek,mt8173-nor"; 695 reg = <0 0x1132c000 0 0x1000>; 696 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 697 clocks = <&topckgen CLK_TOP_SPINOR>, 698 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 699 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 700 clock-names = "spi", "sf", "axi"; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 status = "disabled"; 704 }; 705 706 efuse: efuse@11c10000 { 707 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 708 reg = <0 0x11c10000 0 0x1000>; 709 #address-cells = <1>; 710 #size-cells = <1>; 711 u3_tx_imp_p0: usb3-tx-imp@184,1 { 712 reg = <0x184 0x1>; 713 bits = <0 5>; 714 }; 715 u3_rx_imp_p0: usb3-rx-imp@184,2 { 716 reg = <0x184 0x2>; 717 bits = <5 5>; 718 }; 719 u3_intr_p0: usb3-intr@185 { 720 reg = <0x185 0x1>; 721 bits = <2 6>; 722 }; 723 comb_tx_imp_p1: usb3-tx-imp@186,1 { 724 reg = <0x186 0x1>; 725 bits = <0 5>; 726 }; 727 comb_rx_imp_p1: usb3-rx-imp@186,2 { 728 reg = <0x186 0x2>; 729 bits = <5 5>; 730 }; 731 comb_intr_p1: usb3-intr@187 { 732 reg = <0x187 0x1>; 733 bits = <2 6>; 734 }; 735 u2_intr_p0: usb2-intr-p0@188,1 { 736 reg = <0x188 0x1>; 737 bits = <0 5>; 738 }; 739 u2_intr_p1: usb2-intr-p1@188,2 { 740 reg = <0x188 0x2>; 741 bits = <5 5>; 742 }; 743 u2_intr_p2: usb2-intr-p2@189,1 { 744 reg = <0x189 0x1>; 745 bits = <2 5>; 746 }; 747 u2_intr_p3: usb2-intr-p3@189,2 { 748 reg = <0x189 0x2>; 749 bits = <7 5>; 750 }; 751 }; 752 753 u3phy2: t-phy@11c40000 { 754 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges = <0 0 0x11c40000 0x700>; 758 status = "disabled"; 759 760 u2port2: usb-phy@0 { 761 reg = <0x0 0x700>; 762 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 763 clock-names = "ref"; 764 #phy-cells = <1>; 765 }; 766 }; 767 768 u3phy3: t-phy@11c50000 { 769 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 ranges = <0 0 0x11c50000 0x700>; 773 status = "disabled"; 774 775 u2port3: usb-phy@0 { 776 reg = <0x0 0x700>; 777 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 778 clock-names = "ref"; 779 #phy-cells = <1>; 780 }; 781 }; 782 783 i2c5: i2c@11d00000 { 784 compatible = "mediatek,mt8195-i2c", 785 "mediatek,mt8192-i2c"; 786 reg = <0 0x11d00000 0 0x1000>, 787 <0 0x10220580 0 0x80>; 788 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 789 clock-div = <1>; 790 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 791 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 792 clock-names = "main", "dma"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 i2c6: i2c@11d01000 { 799 compatible = "mediatek,mt8195-i2c", 800 "mediatek,mt8192-i2c"; 801 reg = <0 0x11d01000 0 0x1000>, 802 <0 0x10220600 0 0x80>; 803 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 804 clock-div = <1>; 805 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 806 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 807 clock-names = "main", "dma"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 i2c7: i2c@11d02000 { 814 compatible = "mediatek,mt8195-i2c", 815 "mediatek,mt8192-i2c"; 816 reg = <0 0x11d02000 0 0x1000>, 817 <0 0x10220680 0 0x80>; 818 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 819 clock-div = <1>; 820 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 821 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 822 clock-names = "main", "dma"; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 imp_iic_wrap_s: clock-controller@11d03000 { 829 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 830 reg = <0 0x11d03000 0 0x1000>; 831 #clock-cells = <1>; 832 }; 833 834 i2c0: i2c@11e00000 { 835 compatible = "mediatek,mt8195-i2c", 836 "mediatek,mt8192-i2c"; 837 reg = <0 0x11e00000 0 0x1000>, 838 <0 0x10220080 0 0x80>; 839 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 840 clock-div = <1>; 841 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 842 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 843 clock-names = "main", "dma"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 status = "disabled"; 847 }; 848 849 i2c1: i2c@11e01000 { 850 compatible = "mediatek,mt8195-i2c", 851 "mediatek,mt8192-i2c"; 852 reg = <0 0x11e01000 0 0x1000>, 853 <0 0x10220200 0 0x80>; 854 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 855 clock-div = <1>; 856 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 857 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 858 clock-names = "main", "dma"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 i2c2: i2c@11e02000 { 865 compatible = "mediatek,mt8195-i2c", 866 "mediatek,mt8192-i2c"; 867 reg = <0 0x11e02000 0 0x1000>, 868 <0 0x10220380 0 0x80>; 869 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 870 clock-div = <1>; 871 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 872 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 873 clock-names = "main", "dma"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 status = "disabled"; 877 }; 878 879 i2c3: i2c@11e03000 { 880 compatible = "mediatek,mt8195-i2c", 881 "mediatek,mt8192-i2c"; 882 reg = <0 0x11e03000 0 0x1000>, 883 <0 0x10220480 0 0x80>; 884 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 885 clock-div = <1>; 886 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 887 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 888 clock-names = "main", "dma"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 i2c4: i2c@11e04000 { 895 compatible = "mediatek,mt8195-i2c", 896 "mediatek,mt8192-i2c"; 897 reg = <0 0x11e04000 0 0x1000>, 898 <0 0x10220500 0 0x80>; 899 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 900 clock-div = <1>; 901 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 902 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 903 clock-names = "main", "dma"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 909 imp_iic_wrap_w: clock-controller@11e05000 { 910 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 911 reg = <0 0x11e05000 0 0x1000>; 912 #clock-cells = <1>; 913 }; 914 915 u3phy1: t-phy@11e30000 { 916 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges = <0 0 0x11e30000 0xe00>; 920 status = "disabled"; 921 922 u2port1: usb-phy@0 { 923 reg = <0x0 0x700>; 924 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 925 <&clk26m>; 926 clock-names = "ref", "da_ref"; 927 #phy-cells = <1>; 928 }; 929 930 u3port1: usb-phy@700 { 931 reg = <0x700 0x700>; 932 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 933 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 934 clock-names = "ref", "da_ref"; 935 nvmem-cells = <&comb_intr_p1>, 936 <&comb_rx_imp_p1>, 937 <&comb_tx_imp_p1>; 938 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 939 #phy-cells = <1>; 940 }; 941 }; 942 943 u3phy0: t-phy@11e40000 { 944 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 945 #address-cells = <1>; 946 #size-cells = <1>; 947 ranges = <0 0 0x11e40000 0xe00>; 948 status = "disabled"; 949 950 u2port0: usb-phy@0 { 951 reg = <0x0 0x700>; 952 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 953 <&clk26m>; 954 clock-names = "ref", "da_ref"; 955 #phy-cells = <1>; 956 }; 957 958 u3port0: usb-phy@700 { 959 reg = <0x700 0x700>; 960 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 961 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 962 clock-names = "ref", "da_ref"; 963 nvmem-cells = <&u3_intr_p0>, 964 <&u3_rx_imp_p0>, 965 <&u3_tx_imp_p0>; 966 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 967 #phy-cells = <1>; 968 }; 969 }; 970 971 ufsphy: ufs-phy@11fa0000 { 972 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 973 reg = <0 0x11fa0000 0 0xc000>; 974 clocks = <&clk26m>, <&clk26m>; 975 clock-names = "unipro", "mp"; 976 #phy-cells = <0>; 977 status = "disabled"; 978 }; 979 980 mfgcfg: clock-controller@13fbf000 { 981 compatible = "mediatek,mt8195-mfgcfg"; 982 reg = <0 0x13fbf000 0 0x1000>; 983 #clock-cells = <1>; 984 }; 985 986 vppsys0: clock-controller@14000000 { 987 compatible = "mediatek,mt8195-vppsys0"; 988 reg = <0 0x14000000 0 0x1000>; 989 #clock-cells = <1>; 990 }; 991 992 wpesys: clock-controller@14e00000 { 993 compatible = "mediatek,mt8195-wpesys"; 994 reg = <0 0x14e00000 0 0x1000>; 995 #clock-cells = <1>; 996 }; 997 998 wpesys_vpp0: clock-controller@14e02000 { 999 compatible = "mediatek,mt8195-wpesys_vpp0"; 1000 reg = <0 0x14e02000 0 0x1000>; 1001 #clock-cells = <1>; 1002 }; 1003 1004 wpesys_vpp1: clock-controller@14e03000 { 1005 compatible = "mediatek,mt8195-wpesys_vpp1"; 1006 reg = <0 0x14e03000 0 0x1000>; 1007 #clock-cells = <1>; 1008 }; 1009 1010 vppsys1: clock-controller@14f00000 { 1011 compatible = "mediatek,mt8195-vppsys1"; 1012 reg = <0 0x14f00000 0 0x1000>; 1013 #clock-cells = <1>; 1014 }; 1015 1016 imgsys: clock-controller@15000000 { 1017 compatible = "mediatek,mt8195-imgsys"; 1018 reg = <0 0x15000000 0 0x1000>; 1019 #clock-cells = <1>; 1020 }; 1021 1022 imgsys1_dip_top: clock-controller@15110000 { 1023 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1024 reg = <0 0x15110000 0 0x1000>; 1025 #clock-cells = <1>; 1026 }; 1027 1028 imgsys1_dip_nr: clock-controller@15130000 { 1029 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1030 reg = <0 0x15130000 0 0x1000>; 1031 #clock-cells = <1>; 1032 }; 1033 1034 imgsys1_wpe: clock-controller@15220000 { 1035 compatible = "mediatek,mt8195-imgsys1_wpe"; 1036 reg = <0 0x15220000 0 0x1000>; 1037 #clock-cells = <1>; 1038 }; 1039 1040 ipesys: clock-controller@15330000 { 1041 compatible = "mediatek,mt8195-ipesys"; 1042 reg = <0 0x15330000 0 0x1000>; 1043 #clock-cells = <1>; 1044 }; 1045 1046 camsys: clock-controller@16000000 { 1047 compatible = "mediatek,mt8195-camsys"; 1048 reg = <0 0x16000000 0 0x1000>; 1049 #clock-cells = <1>; 1050 }; 1051 1052 camsys_rawa: clock-controller@1604f000 { 1053 compatible = "mediatek,mt8195-camsys_rawa"; 1054 reg = <0 0x1604f000 0 0x1000>; 1055 #clock-cells = <1>; 1056 }; 1057 1058 camsys_yuva: clock-controller@1606f000 { 1059 compatible = "mediatek,mt8195-camsys_yuva"; 1060 reg = <0 0x1606f000 0 0x1000>; 1061 #clock-cells = <1>; 1062 }; 1063 1064 camsys_rawb: clock-controller@1608f000 { 1065 compatible = "mediatek,mt8195-camsys_rawb"; 1066 reg = <0 0x1608f000 0 0x1000>; 1067 #clock-cells = <1>; 1068 }; 1069 1070 camsys_yuvb: clock-controller@160af000 { 1071 compatible = "mediatek,mt8195-camsys_yuvb"; 1072 reg = <0 0x160af000 0 0x1000>; 1073 #clock-cells = <1>; 1074 }; 1075 1076 camsys_mraw: clock-controller@16140000 { 1077 compatible = "mediatek,mt8195-camsys_mraw"; 1078 reg = <0 0x16140000 0 0x1000>; 1079 #clock-cells = <1>; 1080 }; 1081 1082 ccusys: clock-controller@17200000 { 1083 compatible = "mediatek,mt8195-ccusys"; 1084 reg = <0 0x17200000 0 0x1000>; 1085 #clock-cells = <1>; 1086 }; 1087 1088 vdecsys_soc: clock-controller@1800f000 { 1089 compatible = "mediatek,mt8195-vdecsys_soc"; 1090 reg = <0 0x1800f000 0 0x1000>; 1091 #clock-cells = <1>; 1092 }; 1093 1094 vdecsys: clock-controller@1802f000 { 1095 compatible = "mediatek,mt8195-vdecsys"; 1096 reg = <0 0x1802f000 0 0x1000>; 1097 #clock-cells = <1>; 1098 }; 1099 1100 vdecsys_core1: clock-controller@1803f000 { 1101 compatible = "mediatek,mt8195-vdecsys_core1"; 1102 reg = <0 0x1803f000 0 0x1000>; 1103 #clock-cells = <1>; 1104 }; 1105 1106 apusys_pll: clock-controller@190f3000 { 1107 compatible = "mediatek,mt8195-apusys_pll"; 1108 reg = <0 0x190f3000 0 0x1000>; 1109 #clock-cells = <1>; 1110 }; 1111 1112 vencsys: clock-controller@1a000000 { 1113 compatible = "mediatek,mt8195-vencsys"; 1114 reg = <0 0x1a000000 0 0x1000>; 1115 #clock-cells = <1>; 1116 }; 1117 1118 vencsys_core1: clock-controller@1b000000 { 1119 compatible = "mediatek,mt8195-vencsys_core1"; 1120 reg = <0 0x1b000000 0 0x1000>; 1121 #clock-cells = <1>; 1122 }; 1123 1124 vdosys0: syscon@1c01a000 { 1125 compatible = "mediatek,mt8195-mmsys", "syscon"; 1126 reg = <0 0x1c01a000 0 0x1000>; 1127 #clock-cells = <1>; 1128 }; 1129 1130 vdosys1: syscon@1c100000 { 1131 compatible = "mediatek,mt8195-mmsys", "syscon"; 1132 reg = <0 0x1c100000 0 0x1000>; 1133 #clock-cells = <1>; 1134 }; 1135 }; 1136}; 1137